JPS605088B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device that selects a channel using data for each channel stored in a memory.

Recently, new channel selection methods have been proposed, such as digital methods or logic circuit methods using large-capacity memories and microcomputers.

As an example, the tuning voltage (analog voltage) for each channel to be applied to an electronic tuner using a variable capacitance diode is converted into digital data using an A/○ converter, etc., and converted into a non-volatile large capacitor. Store each channel in memory at a different address,
When selecting a channel, input the desired channel from the keyboard, etc., specify the memory address, retrieve the digital data stored at that address, and use the ○/A comparator to select the analog voltage. There is a method in which a desired channel is selected by converting the voltage into a local voltage and applying it to an electronic tuner. This is commonly called the "voltage synthesizer method." Another method is the phase-locked loop (P
LL) circuit, the frequency division ratio for each channel in the programmable frequency divider in the PLL loop is stored as digital data in a nonvolatile large capacity memory at a different address for each channel, and then selected. When broadcasting, the desired channel is entered from the keyboard, etc., and the corresponding address digital data is read out, and the desired channel is selected by setting the division ratio of the programmable frequency divider. There is something.

This is commonly called the "frequency synthesizer method." However, in these various channel selection devices, when the data at one of the addresses is no longer needed in the memory that stores digital data for channel selection and is to be erased, the digital data at that address is erased. At the same time, there is a drawback that all digital data after that address must be rewritten.

Therefore, an object of the present invention is to provide a device that eliminates such drawbacks, and when erasing digital data at any address in memory, all digital data from the next address onward is erased for one address. The device is characterized in that by transferring data in such a manner as to increment the data, there is no vacant address in the middle and there is no need for rewriting. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing one embodiment thereof.

This embodiment is an example used in a voltage synthesizer type tuning device of the above two types, and FIG. 1 shows its block diagram. Here, we will explain using a hardware logic circuit, but it goes without saying that it may also be implemented using a microcomputer with similar effects.First, in FIG. 1, 1 uses a variable capacitance diode as a tuning element; 2 is a VIF circuit, 3 is a video detection circuit, 4 is a video amplification circuit, 5 is a color reproduction circuit, and 6 is a color cathode ray tube. are similar to those of a normal color television receiver.The remaining parts are the features of this device, and 7 is a digital signal that digitizes the channel selection voltage for selecting each channel. This is a non-volatile memory that stores data in separate addresses for each channel.Here, for example, address 1
~ has n address storage locations up to address n;
It is assumed that each can store digital data of X bits. That is, it is capable of storing digital data for up to n channels. Reference numeral 8 denotes a tuning voltage setting circuit for setting the tuning voltage to be written and stored in the memory 7. For example, a variable resistor that divides the power supply voltage is used to set the tuning voltage of an analog voltage.

This channel selection voltage is converted into x-bit, for example, 16-bit digital data by the A/D converter 9, and written into the x-bit buffer memory 0. At the same time, the D/A converter 11 reconverts the analog voltage into a tuning voltage and applies it to the electronic tuner. The switch 12 is kept open at times other than when setting. On the other hand, 13 is an address designation circuit for inputting the address of the channel to be selected when selecting a channel, or for specifying and inputting the address to be written when writing digital data for channel selection as described above.
A keyboard, n switches, etc. are used.

The address control circuit 14 converts the input address designation signal into a signal suitable for controlling the memory 7, such as a binary signal, and adds it to the address terminal ADR of the memory 7 to designate the read or write address. . Furthermore, 15 sets the memory 7 to the display mode.
A mode selector for switching between rubbing and writing mode, which is normally set to read mode and changes to write mode only when a command is input from manual write switch 16.

Now, when first storing the digital data of each channel in the memory 7 prior to use, the switch 12 is closed and the analog channel selection voltage set by the channel selection voltage setting circuit 8 is set as described above. is converted into digital data by A/○ converter 9, and this is stored in buffer memory 0.
1 write, add it from the buffer memory 10 to the input/output terminal 1/0 of the main memory 7, input the address to write this from the address designation circuit 13, and write the address of the memory 7 via the address control circuit 14. specify.

In this state, operate the write switch 16 and select the mode selector 1.
If the memory 7 is set to the write mode in Step 5, the digital data set above can be written and stored in the storage location of the designated address in the memory 7. By repeating this write operation while switching the addresses from 1 to n and setting the channel selection voltage for each address, digital data is written to the storage locations of all addresses in the memory 7 for each channel. Store.

After storing the digital data in the memory 7 in this manner, the switch 12 is left open and the address corresponding to the desired channel is designated from the address designation circuit 13.

Then, the designated address of the memory 7 is designated via the address control circuit 14, and the digital data stored at that address is read from the input/output terminals 1/0 and written into the buffer memory 1. Further D/A
The voltage is applied to the converter 11 and converted into an analog channel selection voltage, and then applied to the electronic tuner 1 to select the desired channel. Next, erasing and line-up transfer of digital data in such an apparatus will be explained.

Here, the digital data stored at the i-th address i in the memory 7 is erased, and the next address (
Assume that the digital data stored from address i+1) to address n is moved up one address at a time and transferred from address i to address (n-1). The flow of operations at this time is shown in the flowchart of FIG. In this case, first input and designate the address i to be erased from the address designation circuit 13.

Next, 'B}, an input for erasing and line raising commands is made from the separately provided advance switch 17. Then, 'C},
A mode select pulse is generated from the timing circuit 18 and applied to the mode selector 15, and the main memory 7 is set to the select mode. Next, an instruction pulse is applied from the timing circuit 18 to the address incrementer 19, and an address increment pulse is applied to the address control circuit 141, so that the address in the main memory 7 specified by the address control circuit 14 becomes one address. The address (i+1) is specified. Then, the n determination circuit 20 determines whether 'E}, this address (i+1), is less than or equal to address n, and if it is i+1 min, {F}, the address (i+1) in the main memory 7 is determined. The stored digital data is extracted, written into the buffer memory, and stored. Subsequently, (G), an instruction pulse is applied from the timing circuit 18 to the address decrement 21, and an address decrement pulse is applied to the address control circuit 14, so that the number of addresses specified by the address control circuit 14 is increased by one address. , and address i is designated again. Also, at this time (H), a mode enable pulse is applied from the timing circuit 18 to the mode selector 15, and the main memory 7 is put into the write mode. As a result, (1), the address (i+1) that had been stored in the buffer memory until then is . Digital data is now written and stored at address i. At the time of this writing, the digital data previously stored at address i is automatically erased. Thus, the address (i
+1) to address i has been transferred. When this writing is completed (J), a mode switching pulse is again applied from the timing circuit 18 to the mode selector 15, and the main memory 7 is returned to the read mode. After that, (K), further timing circuit 18
is added to the address incrementer 19, and the designated address from the address control circuit 14 becomes address (i+1).
One transfer operation is completed with the address incremented to , and the process returns to the first address increment step D. By repeating the above-mentioned operations D to K, the address is incremented by one address at each cycle, and the digital data is transferred and re-stored by increasing the line by one address.

In the determination process E by the n determination circuit 20, when it is detected that the specified address N has exceeded the address n, it is determined that all transfers up to the address n in the main memory 7 have been completed. (L), the timing circuit 18 is controlled by the output of the determination, and the digital data transfer operation is completed.

In this manner, according to this device, by simply operating the address designation circuit 13 to input the address to be erased and operating the line up switch 17, not only the digital data at that address can be erased, but also the digital data at that address can be erased. The digital data stored in subsequent addresses can be automatically and sequentially raised and re-stored, making it possible to realize a channel selection device with good operability.

It should be noted that the present invention can be implemented using any circuit configuration other than the one described in the above embodiments, which provides similar effects. It goes without saying that the present invention can also be implemented in devices where data is stored in a digital memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a channel selection device according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the device. 1...Electronic tuner, 7...Main memory, 10.
．．・Buffer memory, 11...D/A converter, 13...
Address designation circuit, 14...Address control circuit, 15
...Mode selector, 17...Line up switch, 1
8...Timing circuit, 19...Address incrementer, 20...N discrimination circuit, 21...Address decrementer. Figure 1 Figure 2

Claims (1)

[Claims] 1 Equipped with a memory that stores digital data for selecting each channel in a storage location of a separate address for each channel, and selects the corresponding address in the memory according to the input desired channel selection. In a tuning device that reads out the data from the memory and controls the tuner using the data to select the desired channel, when one of the addresses in the memory is specified and an advance command is issued. Transfer means that, when input, erases the data stored at the address, transfers the data stored after the address next to the address, and re-stores the data sequentially moved up one address at a time. A channel selection device comprising: