JPS60501477A - Method and pitch conversion device for changing the pitch of an audio signal - Google Patents

Abstract

Digital processing of speech signals for compression/expansion pitch change is provided by writing and reading a ROM at different rates and controlling the discard/repeat segments of memory to be integral multiples of the pitch period.

Description

[Detailed description of the invention] Audio signal processing method and device using pitch period control The present invention relates to a digital audio signal processing method and apparatus. Regarding pitch conversion processing in processing, the conversion processing is based on the pinch frequency of the audio being processed. This can be controlled depending on the period.

Background of the invention Real-time pinch conversion or audio compression of audio signals and/or delayed i.e. recording Pinch recovery of audio signals created by speed or slow playback of sound) It is a matter of modern awareness how useful an economical system of implementation is. child An early form of such a system was an electromechanical tape with a movable magnetic reading end. -Can be seen by the player.

These systems divide the recording tape into short segments and alternate segments. He was creating something equivalent to putting pieces together. However, these initial configurations has been completely replaced by an Electro-X system. For example, Schiff Mann, U.S. Pat. No. 3,786,195, has been widely used commercially. His U.S. Patent No. 3,936,610, which has been utilized, is published in Ru.

Schiffman's method was like this, but most other systems also use pinch changes. I've been using a method called tin rice. i.e. lower the audio pinch If a regular segment of the signal is stretched and changes pitch, the intervening remainder had been deleted, which caused a discontinuity based on this deletion. Conversely, the voice pitch When increasing, the repeated pinch changes are occupied by the signal segment This is done by compressing the time interval, resulting in gigang, and this signal compression Since it is necessary to fill in the gigang caused by It's here.

This pinch change-splice method is used to improve the quality of the voice. Much work has been done, most of which has focused on improving splicing methods. Ta. These improvement proposals are more from a microscopic perspective, and are based on the instantaneous effects of processed waveforms. The time characteristics are unrelated to the overall characteristics and are generally determined by system limitations. It usually included waveform analysis at Rice Point. That is, work The focal point of the waveform parameters (level, slope, slow foot direction (fi nature), etc.) an instantaneous value and the end of the segment with respect to one or more of its values; Comes aimed at taking pine tincture etc. with the tip of the next segment connected to Ta. and zero closon splice method (if polarity matches, if not ), level matching, superposition method, and many others have been tested. However, the improvement in audio quality has generally been lower than expected.

Lee U.S. Patent No. 3,803,363 describes the digital zero energy level. An example of a lumatting method can be seen. In this method, the audio signal is converted to a tall representation, stored in random access memory, and written to this memory. A method is used to read data at a rate different from the write rate when data is written.

In other words, the addresses where memory accesses for writing and reading are being performed are concentrated. (due to write/read differences), a low energy level or Migrate (jump) to a new address selected by Narudame method is adopted.

Another device that writes and reads at different rates in digital memory. Digital processing methods delay jumps until proper matching between waveforms is achieved. When the address is focused on checking the signals in memory, the jump is delayed. I'm trying to make sure that the drop occurs. This U.S. permit No. 4,121,058 by Jusko et al. The number has another feature. It's no good looking back at specific parts of the story. looping feature and a menu to hold segments while facing It has a function to prevent input to the harpoon. In Lee and Jusko et al. In the method described above, the new address of the read specifier (pointer) in memory is A jump to the signal level indicates that the initial difference between the write and read pointers is small fluctuations caused by microscopic investigations and adjustments made to match the It is assumed that virtually all of the memory capacity is utilized, excluding the difference due to The sea urchins are pre-selected.

According to research carried out by Ian Bennent, audio signals are peach), if the signal is stretched or compressed by the processing circuit. If the signal segment is a synchronized pinch period of the fundamental audio frequency, the sound quality of the processed sound will be greatly improved. (If you extract and examine the fundamental audio frequency, the pinch period will be Note that it is the period of the audio frequency). But full (unfiltered) The audio waveform, even for vocalized sounds, is not a pure sine wave, but rather a repeating pattern. epoch, each period of which is generally followed by a weakened waveform for the remainder of the epoch. Pruning begins with a glottal pulse. Yes about pitch synchronization processing method Several proposals have been made, but at the beginning of the epoch (i.e., the Grontal Pulse) Because point detection is required, the methods generally tend to be precise and complex. of Ibader proposes a new cut-splice method. According to Neuberg, When lowering the pinch, it doesn't matter whether the segment begins or ends. - If you want to remove multiple segments with the same length as the threshold epoch, increase the pinch. Good results can be obtained by repeating the procedure (if applicable).

This means that for many utterances, successive epochs span many pitch periods. This is explained by the fact that it contains repetitions of almost the same waveform with the same pinch period. can be explained. Therefore, any segment of length equal to the pitch period Even if you delete a bin, it will still contain the periodic cadence (the falling tone of the voice). It becomes. This method takes into consideration the matching of waveform parameters from a microscopic perspective. As what could not be obtained from the crushing tin rising method, and Great improvements in VC ties that are theoretically easier to achieve than true pinch synchronization systems. It has been described as such. Furthermore, this method allows the pinch period and waveform to be calculated for each epoch. If the shape does not change, the end point of one segment and the other segment The starting point of the pitch (with one or two pitch periods removed) is the level, slot Waveform maps often match well, so even from a conventional perspective, waveform maps According to the present invention, the degree of twisting can be automatically improved by compression and stretching. delete or repeat intervals to fill each gap created by system that can process recorded tapes at selectable playback speeds. , in a system for real-time pinch Zofteinder, using epoch natural splices. glottals that can be derived from the actual audio signal to realize the benefits of ・Pitch change/cant that can be controlled according to pulse signals and mass-produced at low cost A splice system is provided. In the present invention, the conventional mi Applying microprocessor logic to perform necessary audio sampling, data conversion, and storage. In addition to multiplication and reading, writing is also possible in both compression and expansion modes. jump in memory, which is required when the read pointer is concentrated. A grossotal pulse signal whose periodicity is used to control the period. An audio signal analysis of the drawer is also performed. In many variants, there is no vocalization sound. and a second read point closely linked to the write pointer position. I am using a printer.

Therefore, especially in compressed mode, pinch period deletion makes pitch period calculations sound Notes, such as when done from a voice input signal (given to the write pointer) The audio signals are spaced apart by the depth of the current readout from memory. It is more accurately related to the audio signal being used.

Drawing description FIG. 1 is a conceptual block diagram showing the entire system according to the present invention; FIG. 2 is a diagram showing a modified example of a ROM memory equipped with two read pointers, Figures 3A, 3B, and 30 are complete block diagrams of the basic system, and Figure 4A is the writing and reading Program and digital-to-analog converter to control the protrusion pointer A flowchart showing a cover sofa for use, Figure 4B shows the analog-to-digital conversion of the input audio signal and the conversion from the audio input signal. a flowchart showing glottal pulse pinch periodic signal induction; FIG. 5 is a partial block diagram corresponding to FIG. A diagram showing a modified example of the operation of FIG. 6 is a partial block diagram corresponding to FIG. FIG. 7 is a partial block diagram corresponding to FIG. 3, and shows a modification of the operation. FIG. 7 is a diagram illustrating a modification of using a larger memory in a periodic process.

Description of the invention Figure 1 shows the overall configuration of the present invention using random access memory RAMI. shows. RAM 17 receives the audio input signal from analog-digital converter 12. digitized sample, this digital word is placed at write pointer 1. Therefore, it is sequentially stored in memory. Memory is synchronized by read pointer 2. It is read at the first sea fence. A digital word read from memory is A digital-to-analog converter 16 converts the signal into an audio output.

The memory is under the control of an address register 3 which is actuated by control logic 4. Ru.

The control logic 4 sets the write rate equal to the fixed read rate signals fr and cf. Give f root signals.

Here, C is the compression ratio, there is no pinch change, and it is the unit for playback at the recording rate. defined as , greater than 1 in compressed mode and less than 1 in stretched mode Takes a value greater than 0. The current addresses of write and read voice/receivers are It can be used to control the operation of the / stem by the gic 4. Two quantities F, (tl and F The difference between the current address positions pointed to by w(t) is denoted by the angle θt, and the first In the diagram, write.

It is shown as the angular spacing between read pointers 1 and 2. Also, Figure 1 are the quantities θmax and 0m1 that define the sector on each opposite side of the write pointer 1. 0 is shown. The angle θt is one value, that is, the readout pointer is 0m10. When the write point reaches a value such that θInaX is smaller than θIna Conditions are met for the printer to jump to a new position. constitutes a decisive level of the invention. We will emphasize this motion control as a means of achieving this goal.

The width of the write pointer 71 according to the present invention is always an integral multiple of the pinch period, It is not an integer multiple of the synchronous pitch period. That is, the jump is in the grotstal pulse. Although there is no need to synchronize the global path, the period between the global path and This determines the size of the jump, along with other important factors that determine the number of pulse periods. It is necessary to do so. From this, Grontal Pulse 32 is controlled by Control Logic Fuku 4. Generates a pulse signal output that is supplied.

Fig. 2 shows a modification of the one shown in Fig. 1. In this case, the write pointer is always 1. A second reading pointer 5 that moves at the speed of pointer 1 is added separated by an angle θ\. is being given. In addition, the audio signal source detects the digital signal at position R of the second read pointer. It is obtained from a digitized audio signal input. This characteristic will be explained later. Ensures that the current value of the glontal pulse period is used by the system as .

Hereinafter, preferred embodiments of the present invention will be described with reference to Figures 3A, 3B, and 3C. do.

The configuration of this embodiment consists of five functional blocks: data control, address generator, and address generator. Access control process length.

The jump control and pitch period are divided into upper '+Oj'. these five The components work together to address the required short-term memory in a continuous loop. Conventional digital random access memory IJ (RAM) that performs memory Controls the flow of data within the i7.

The functions of each block described above are as follows.

data control Provides a digital data interface for analog audio input and output.

address generator Provide multiple addresses to RAM, including the address for the next input/output.

access control process Provides the necessary timing signals for regular read/write in RAM K .

jump control On the output side, give the "Smart) FIFOJ news part" and "when" and "where". Decide where to delete or fill in gaps. Still pitch cycle pro It also reads "runkuahead" (reflection) for SEP.

Pinch cycle proceb Determine how much for the jump control module and input voice input It operates on the signal and determines current information about the periodicity of the audio waveform. below, The individual functional blocks mentioned above will be explained in detail.

data control Data control is a straightforward process for dealing with sample data.

The write block is written at a frequency directly proportional to tape speed or other pressure. It's a legitimate signal. Therefore, we introduce a compression ratio C to control the pitch change, Decide how quickly and how input data will be digitized. Compression rate 1 :1 (c=1), the write clock has the same frequency as the read clock . c=l, 12.5KHz Nyquist -y-omblin The gray rate allows an audio bandwidth of 6KHz.

The maximum compression is 25:1, so the maximum frequency of the write clock is 31.25KH z, and the analog-to-digital converter 12 converts in 32 μs for each sample. Must work. A digitized data word is used for each sample. It is composed of 8 focal points. However, the A/D converter 12 and the D/A converter 16 It does not necessarily have to be a linear type, but the data of the formation field 8 focus ・Techniques may be used to maximize the operating range of the bus.

The input buffer 14 typically consumes a significant portion of the available processing time. This is an analog-to-digital conversion. This element has data control and access control. It is composed of ``Mail Bonks'' that do not need to wait for each other. Inner bag bag 14. While the A/D converter is fast enough and the access control requests new data. It's not necessary if you want to play.

Access the input strobe and output strobe from the The buffers 14, 15 are activated, but they do not necessarily have to be regular. stomach. However, to ensure regular write printers, input samples should be must be in a fixed phase relationship with the Similarly, the output samples read It is only allowed to change in a fixed phase relationship with the clock. Bag 7a14 and output buffer 15 provide this function.

address generator The depth of RAM 17 consists of 512 8-pin samples. death Therefore, each access to RAM requires 9 pin addresses.

A 9-pin sequential counter provides RAM write addresses for input samples. I can do it. Considering the simplest recognition of this counter function, the counter is connected to the command signal W Proceeded by CNT. This command is a flowchart of the writing process (Figure 4A). may be the last term of the write block for the next sent address. Almost all cycles are allowed.

A 9-bit reset counter 19 registers the read address and Provide non-sequential intelligent access. This counter is access control and the timing signal from the jump control is under the synthesis command.

Either of these two counter outputs is connected to a 9-pin pointer called pointer MUX1B. The output is output to the RAM at different times through the parallel multiplex length of the component.

access control processor This functional block provides detailed timing and access to data in RAM17. The decision logic for This processor has a processor clock 25 and time-shared by two asynchronous writes/reads. It is a single processor with functions and structure similar to that of a mini or microcomputer. The blocking mechanism is similar.

The flowchart of FIG. 4A shows the idle state of the access control processor at terminal WAI of the flowchart. Indicated by T2.

In this state, the processor uses either the write block or the read clock. , or waiting for orders from both at the same time.

When a single length command is issued independently, the hardware flip block 2 3 is a requested service, i.e., the process is performed according to a write or read command. be placed in an appropriate state according to the reason.

If service commands occur at the same time, the flip 70 knob 23 will Select only one action for a service request. (RAM can handle only one at a time). Regardless of the process, When it is completed, a processing completion notification is issued. This notification clears the request made The action to start the process and the action to reset the hardware device. It is becoming more and more. These devices are called TICK registers (21, 22), and most In most cases, it can be implemented with a simple 1-bit memory device. stop Therefore, its effect is only one length bit per period of a write or read block. The goal is to give the request. Since this register has memory, it has its own block. It stands between the lock and the access control processor and acts as a mailbox. I will do it. Therefore, if the read clock makes a new boobis request If the access control is in the middle of a write operation, the service request is It is placed in a waiting state until it returns to rwAITJ.

There is no set priority for bamboo when it comes to writing and reading lengths and screws. You should be careful.

Logic circuits intentionally set the next non-sequential (jump) address for an output access. create a It is under the control of the access control processor and reads, It includes the minimum control memory that adjusts the functions of the two processes of writing. There is.

Refer to the next flow diagram, FIG. 4A, D I G I TAL. In each RAM and on every write access, W/P MUX 31 (in the flowchart) Then ΔMUX) is set to w” and (±/-) is set to (-). The sign adder 26 compares the write pointer and the read pointer by . If the logic decides to jump, the read pointer will move by nΔP. to move (before or after). Here, ΔP is the pinch period and n is an integer.

The alert detector 27 examines the output of the sign adder and performs a JUMP flip. 70 Tsubu 29 to save.

Jump judgment is determined by whether the stem is set to compression or set to extension. It depends on what you are doing. The details are shown in the flowchart. Compressed mode or stretched mode The board is determined by the +/-7 flip-flop 2BVC, and this flip-flop The zero amplifier 28 compares the sign of the difference R-W. This evaluation indicates that the write pointer Determine whether the output pointer has moved into θml, t or 0max. 5 equivalent.

pitch period processor This module measures the glontal pulse period and adjusts it for the size of the jump. The central memory is RAM17, and the RAM requires an address. requests and exchanges data. Data control handles data and writes or reads it. Control the input and output of data according to the source. Write to a fixed address When executed, this address is specified by a stale pointer. reading is reading It is performed from the outgoing address. Programs write to or read from RAM. However, only one of them can be accessed, and both cannot be accessed at the same time. Therefore, the two addresses are multiplexed so that only one address reaches RAM. They must be combined by the support pointer MUXj8. In this case, access control coordinates writing and reading, so it is possible to distinguish between the two. Asynchronous communication i.e., the zorosen that can be driven by the write clock and read clock. There is no need for a phase to have any fixed relationship.

Writing and reading selections are made by a non-constant 4-state flip block 23. It is done. In that state (7) the two outputs from the 71J block are indistinguishable. do not have. Once the write block and/or read clock is recognized, Flip-flop 23 enters its defined state - and determines whether it is a write or a read. select.

Write and read blocks have periodicity. The tip of the writing ronku is Detected by flip-flop 21, that of the read clock is flipped ・Detected by 70 knob 22 (TICK register). Output of these circuits Qkej1@Include/read flip/70 nb23 set/'recent input Given. Therefore, the clock's upstream statement It triggers a flip-flop to decide whether to write or read. request If there is no input clip clock (i.e. after new work is completed) TICK register) enters the hibernation state. Therefore write/read crimp ・“tOW” is on the cent side of flop 23 and “Z0W11 reset side” Yes, the output is in an undefined state and no determination is made. But any of the st. As soon as one is released, one of the defined states is assumed. to this Therefore, either writing or reading is selected. This is, so to speak, a ``filter''. Write/Read Flip 7 The first block is a fielder, which provides both processes, write processing and read processing. can be done. This fielder's choice is performed when both requests occur at the same time. be exposed. Processing is completed in a short time, and as soon as one process is completed, the next process is requested and executed. It can be administered.

Process clock state machine (PC8M) Determine the individual order for the data pancage. Because: rf, RAM is It has 4 inputs/outputs - 4 pits, and writes 8-bit data in RAM1Cl. Two writes are required to load the data. In the same way, two 4-pin... linkage, that is, two 4-pin pins that together form one 8-pin output word. There are two processes to search for bulls.

gives an initial delay so that any process that does new work has a return time You can have it. Then a first 4-bit nibble occurs, and finally a second 4-bit nibble. A nibble is generated and the process is completed. Access control process Since we know whether it is reading or writing, the above During the 3-step process, you can see one of the tasks you are doing. . When clip-flop 21 or 22 starts PC8M, the access The control processor resets 21 or 22. In short, PC8M is one action. Once completed, check the completed operation. If an action that is not currently being performed is selected during the process, Once the work is completed, you will be able to start working on the completed work immediately. Preparations will be made.

The PC8M25 receives either a write clock coming from flip-flop 21 or 22, or has an asynchronous clock that can be started by any of the read clocks. ing. When both Ronku are completed, PC8M enters an idle state. a letter sent A single cycle of PC8M for each input clock and read clock It's promised.

The 9-pinto ripple counter 20 writes addresses one after the other in a simple sequential fashion. When the address 512 ends, the address returns to address O. for this counter There is no reset. Ripple counter 20 automatically rotates a 9-bit address. It is easy to create υ. On the other hand, the read counter 19 is a presettable counter. It is possible to activate the desired number of precents using the counter. the number can be obtained from the jump control as R,tnP, which is the output of the counter 19. This is the 9-pinto address of the recent one. Load control 30 is confirmed and R If the count's RCNT has a leading edge, an instruction to recognize the precent is recognized by the counter 19. Load control in jump control is by counter 19 and by the access control process length. This is part of the read/write timing. If PRESET LO If the AD signal is confirmed before the R count, the precent number of R+nΔP will be preset. A countable counter 19Vc is added, which constitutes a jump.

The operation of the 9-bit presettable counter 19 is as follows until a jump is required. It is exactly the same as the counter 20. That is, it It operates according to the command of the count signal RCNT. Therefore, before any readout The counter 19 counts and amplifies each address. access control process A 9-bit presettable counter 19 is used as the first order of operation. Give a delay time that takes into account the time to cents. And the address is the data Before receiving the strobe light according to the data control timing, the and must be sent to RAM17.

The output of the RAM is new only with respect to the leading edge of the signal from the read clock 11. It is allowed to assume different analog values. Therefore, the output bumper 15 is RAM buffering operation while the data is being read and the data must be routed to the output. I do.

Jump control determines the interval by an integer nΔP of the pitch period. Described later The pinch period proceb determines what that number is and creates a buffer called the nΔP bus. Put that number on the Therefore, the number of 9 pintos is continuously used in the upper layer of the nΔP bus. and determine the thickness of the jump whenever a jump is necessary. be able to. In compressed mode, jumps are made to higher memory. , in deferred mode it must return to an earlier memory. So Therefore, R+nΔP and l’L−nΔP correspond to compression and stretching, respectively. . To accomplish this jump, the current address from the 9-bit sign adder 26 must be address to nΔP, and add a new address to the RfnΔP bus to eliminate the need for a jump. It will be ready when needed. Malteprek v W/ΔP MUX31 is the same 9-bit Tsuto's sign adder not only creates a new address after the jump, but also Compare the address R that is being read and the address W that is currently being written. The system determines whether a pump is necessary. For each operation, the adder 26 writes Constantly monitors the read address and compares that address with the current value of the read address. compare. Jump flip to do this.

The signal from block 29 is normally relaxed (W/ΔPMUX is in the W-position). Therefore, the alert detector 27 always receives the readout values R and W. can be compared. Different algorithms are used for compression and stretching modes. The algorithm determines when a jump is necessary. But on one condition It is also possible to decide when to jump and whether to use compression or expansion mode.

An alert detector 27 monitors the output of the adder 26 and determines when an alarm condition occurs. Signal generated when the write pointer and read pointer match Determine when a jump is necessary to avoid discontinuities. When an alarm condition occurs , the load control 30 receives the signal and outputs a read/write timing signal R/W tie. The load signal is issued only once, just before the R count signal. did Therefore, only one jump is made each time the need for a jump arises. .

A plus/minus flip block 28 monitors the status of the alert detector. , thereby determining whether the motion is compression or stretching. In case of postponement, 9 The bit sign adder 26 assumes that the signal is currently of negative sign. Declare Cy (sensing the exclusive OR forming part of the 9-bit sign adder 26). I need to say it. In other words, the difference is R-nΔP. Similarly, The lip block 28 activates the jump flip block 29. must be in a negative state when comparing write and read addresses. It becomes important.

The jump fnΔP is determined by the pinch periodic process vVr. this circuit consists of analog and digital synthesis circuits. The input audio signal is Grontar pulse detector 32. Detector 32 detects various speeds that provide the value of C. It is often a filter that tracks incoming audio in a computer. tape record If there is a change in playback speed, as in the case of etc., and normalize the parameters to the first recorded frequency. Detector 32 monitors audio peaks and sends a signal to the start/stop transition logic 36. This will be reported every time a new peak is discovered.

The 9-bit ripple counter block 33 is connected to the write block WCNT. Continue counting continuously. and give the latest count to 9-bit latte 34. The count is restarted each time it receives a signal coming from the start/stop logic 36. start. The start/stop transition logic 36 is UPDATg INHIB Receives another input called IT from jump flip block 29 . This input is necessary to maintain ΔP from changes at the moment the jump occurs. Roru. In that case, the 9-bit ripple counter is asynchronous to the W count. Data transitions are held long enough to keep data available for read cycles. During this time, the latch 34 of 9 pins is not disturbed.

After this, an ampudito (renewal) action occurs. The limit detector 35 has a 9-pin lip. The current value of counter 33 (i11 is monitored. This counter reaches the minimum value of Continue counting until Until that minimum value is reached, even if other starts /Even if a stop signal occurs, it will be ignored. Beyond that minimum value, the detector New glontal pulse peak detection from 32 to start/stop transitions Let's start. The ripple counter 33 detects the global pulse by the detector 32. If a matching dog count is reached without detecting a peak, the limit detector 35 Reject the maximum number as too thick, in which case no update action will occur. child In this case, the final value in latte 34 is used. 9 bit lunch 34 is always , we have prepared a number that can be used for nΔP if necessary.

This flexibility is one of the requirements. This is because jump control Jumps that occur are required by the relationship between the read and write pointers, and are indicated by parentheses. The occurrence of a glontal pulse (or any This is because it is performed only when the signal level is 6, regardless of the signal level.

Limits ranging from 10m5 to 20m5 and normalized to the output signal It is known that limiting the detector 35 gives good results. effective glontal - This interval for the pulse period has a pitch of 50Hz to 100Hz (immediately (i.e., fundamental frequency) range. If the incoming audio signal is higher If the frequency is high, the nΔP that can be avoided will be close to the minimum limit value (10 m-a). . This means that the detected peak coming from detector 32 has a high frequency. It is caused by That is, when the limit detector 35 reaches its minimum number, a peak occurs. And start/stop 36 is close to that 10m5 with 9 pinto latte. In addition to 34, you will star another cycle by 1. Similarly, if there is no If vocal sounds occur (e.g. white noise), the minimum number is 9 bits of latching. It is accumulated to 34. A minimum value significantly smaller than 10m8 will result in an unavoidably high processing rate. Increasing the maximum value is limited by memory capacity. Main implementation 7 In the example, the maximum value is selected as the memory capacity H, and the 9-pin sign adder 26 is selected. This makes it convenient to determine the sign of these numbers.

As shown in Figures 4A and 4B, the system operates under program control. Then, when the write pointer approaches the read pointer, a jump is instructed.

The flowchart has two processors starting from WAITl and WAIT2. WA IT 1 is the lineage of Pro771, WA IT 2 is Shows the lineage of Pro 7″Fj2.

Because the system has separate hardware elements working together simultaneously, a single There is no Rosesa. The operation of the system is described below using the processor symbols WAIT1 and WAIT. 2. Use 2 to explain the process, showing that there are processes that occur simultaneously.

The access control processor shown in Figure 3C follows the flow chart starting at WA LT 2. The program is complete. There are two competing processes, namely the write clock process ( Figure 4B) and read clock process (Figure 4A), which are 7v, in standby state for A2. Pro 7 + j42 progresses reading and writing at the same time. It is a dedicated random access memory that cannot be used. Judgment block ANY TICK? J is on the wait loop while the access control processor is in the wait state And it's working. The access control processor has two TICK registers. 21.22 is provided, and when either tick register is set, the decision block is The lock becomes ``yes'' and the next block ``slips flops against the next one: Proceed to "Reading and other writing" (clip flop 23). Mazu ``writing'' book The program sends a signal to the A/D converter 12 and outputs the input cover software. (See Figure 4B, 1 Bumper in operation?''). Then, if the buffer is If it was working, clear the buffer after a certain period of time. This behavior is shown in the flow chart as "Clear Write Process Tick Register". child You can perform this operation at any time, but it is more convenient to do it at this stage. Then enter The buffer is transferred to random access memory. (If we say it in Figure 3A, the input The force buffer 14 is processed by the input strobe, and the data is passed through the bidirectional I10. and is written into the RAM 17 (). Then, perform the conversion operation within that specific time. If so, the A/D converter is cleared. Next step Hiro pointer a This is a check on Rato. This is a 9-pinto sign adder with no jump control. 26 is used to check whether the separation state of the two pointers is broken. . Since this collapse is not seen most of the time during the program progress, the pointer ・The alert judgment is “No”.

The remaining work in the write process is to advance the write pointer, which As a result, the 9-point glue counter 20 is counted up. Then, The program returns to WAIT2. Write process tick register is cleared Therefore, when the program returns to WAIT2, the judgment block ``Some tick (T ICK)? Go to j. There is no tick signal coming from the write clock. It should be. However, if the tick signal from the read clock is recognized, the The judgment block below is “Yes”, and the sentence “Reading, one of the other writing” is written. Proceed to step V, and since writing has been completed, select the "reading" step.

In the read process, pointer MUX is used as a switch to switch counters 19 to 9. It is necessary to select the read address of the bit. This step It is only performed during Seth. This is because the write process always ensures that the write address is available. I can do it because I can use it. Next, the program advances the read pointer to the R count. The signal RCNT is changed to set the counter 19 to R+1. In this case, even if It should be noted that the count will increase even if there is a pump. The next step is to Unconditional to confirm that the count has been fixed on the output line of counter 19 This step is a delay step. .

This step is the tick of the readout process that has started this readout signal. - This is a convenient stage to clear registers. by the specified address. data is read from the RAM to the output buffer. At this stage, reading is It is not a direct readout to the audio output. This is because the output is shattered (jitt ertng). So that the output is normal, Write the data read from RAM to the output buffer.

The output buffer 15 is connected to the D/A converter DAC 16, but the output buffer 15 is connected to the D/A converter DAC 16; Since it has a built-in launch circuit, even if a DAC is connected, the final data Up to parts are retained on the output. This is shown at the top right of the flow diagram.

The strobe always acts on the leading end of the read clock. The last one in Pan7a The value is co-located with the D/A converter 16 if it is the final read value. Transferred to the launch circuit. This read clock also triggers the tick register. trigger, so there is no read cycle that occupies that buffer at the same time. Become.

When the data has been read from RAM to the output buffer, the program ・Clip clock cent? "The process proceeds to the determination step ". jump chestnut The write clock is part of the write process. If this is cent If not, the judgment block output will be “no” and the read pointer MUX The program returns to WAITl again by returning to the incense selection. .

When the read process is completed, the program returns RCNT to “Low” once. Do not execute the read step until you go to ``h1gh'' and return to h1gh' again. As part of the read process, the write clock also loads the data into the tick register. the program will immediately follow suit and perform the write cycle again. . For write vehicle execution conditions, the pointer alert is normally at the W position. Readout using a 9-pin sign adder 26 with a W/P MUX that occupies the The address written in the write address is compared with this most recently written address. If the pointer If the alert is ``Yes, j'' (in other words, there is a collision between two pointers) ), the alert detector 27 receives a signal declared for that condition. , is used to set the jump flip-flop 28.

At the same time as the jump/flip/70 knob is set, W/P MUX is at ΔP level It is passed down from generation to generation. This is because the next step is to adopt hΔP for the readout process. This is because executing a jump using a step is a step. pointer alert One comparison step is required to set . That is, 0/-flip The push-70 knob 28 is normally set in a negative state. Because take the difference This is because it is an act that is equivalent to the act of comparison. jump flip clock When the jump is executed, the 9-bit signed adder is in a positive state as an adder. When the number is +1, a jump is executed in compressed mode. In that case, flip The flop is set positive.

Similarly, in the extension mode, it can be set to a negative value.

The method for determining polarity is to use the output of a 9-bit sign adder to see the sign of R-W. Adopt the method of investigation. All bits coming from the 9-bit sign adder are A verification formula can be used to determine whether is positive or negative. If those bits If it is small and positive, the pointer is moving in the direction of the forefoot, that is, in the direction of compression. If it is negative, it means that it is moving in the direction of extension. Because there is no doubt about it. Even if the sign is deterministic, the program There is no jump because it is located in Su.

During the process of reading the program jump clip 70 tubes The process proceeds to the determination step "Jump clip clock set?" Next In the read process of the program, the jump flip-flop is Decide. Then, since the set is completed, the process branches. This makes R If it is nΔP, the read pointer is jumped. Plus in this case, my Eggplant is determined by plus or minus J clip clock. This frame Rip-flops are sent in a compressed state during the write process. Ru.

When a jump occurs, the jump flip-flop is cleared and the write process Verify that the student did request a successful jump. In this way, The program executes the jump only once, and then executes the jump again until the conditions are met. Not performed.

Now, W/ΔP MUX31 has returned to its normal state at the write position, and the Las Minus Flip 70 Nbu 28 is clear type and in normal condition, that is, my Back to eggplant. For repetitive operation, there are two states in the writing process, viz. The state in the minus and W positions is W to determine if a jump is required. It is necessary to constantly compare R and R. The last step in Figure 4A is to point the pointer MtlX This is the step of advancing the data to the normal position, that is, WRITE.

The program for the A/D converter 12 follows the flow starting from WAITl in FIG. 4B. As shown in the figure. Tick register 21 monitors the write clock.

When the leading edge of the write clock occurs, this processor Verify it in the same way as the starting processor did. This processor's first Step clears this tick register and converts analog to digital This is the step to do this. input bar to decide whether to remember that data. It must be checked whether the buffer 14 is working. Because WAITl's This is because processes can access it simultaneously. If buffer 14 is free, If so, the determination in the determination step "Is the buffer in progress?" is "No". By this The A/D converter 12 executes the conversion, and the data is transferred to the input buffer 14. It gets absorbed. The program will return immediately and if the WAIT2 process Begins other transformations unless instructed to stay aud by Fa.

The same audio analog signal that is about to undergo digital conversion has an analog pitch The period detector 32 detects the glontal pulse and starts a pinch period. It is used to determine whether the

The flow starting at WAIT3 causes another processor (one counter and several ) is the interval between the glontal pulses of the audio input. count. First, the program disables the beak counter 33 and Companion the force pulse, cent the count to zero, then the new Grontal ・Wait for the pulse to appear. The counter 33 is in the start state, that is, reset to zero h-g It will be done. The final value of the counted pinch period is input to the 9-bit launch circuit 34. It will not be lost because it will be lost. Grottal pulse is an analog pulse detector When entering from 32, the program starts the ding pitch cycle? ” Judgment block The peak counter 33 is set to the enabled state. This allows W The count signal WCNT enters the right side of a 9-bit ripple counter 33. this The system monitors the glontal pulse and for each count the counter is Proceed and P becomes P+1. Does the limit detector 35 have an overrun in the upper limit count? Check if the count is greater than 384, which is 3/4 of the memory capacity. In other words, check whether it exceeds approximately 20m11. If the answer is 1 If the count exceeds the upper limit, there will be a long interval between glontal pulses. Bars (longer than one would think of in a regular speech) are rare. That is, This means that the speech (voice) was interrupted. Zeeyanbu has this belief. should not be carried out under this issue. Because it's not a steady state It is. In this case, the program can be canceled as is and return to WAIT 3. . Even if the program follows this branch, the number in the 9-pin launch circuit 34 will not change. It should be noted that this does not change.

If the number is less than its maximum value, the program determines whether the pitch period has ended. Ask about it. If there is a glontal pulse, the count is stopped and the P counter Find out if the number of counters is 95 and it is a dog. This is an arbitrary restriction, and here is equivalent to a minimum limit of 10 m5. If the number is that very small minimum If it is larger, it is called a good pitch period. The reason is that a good pinch cycle (immediate (i.e., voiced pinch) constitutes a voiced pinch if the number of P counters is equal to 384 or This is because it must be less than 96 and must be greater than 96. Then, The program asks for the cent status of Jump, 7 Limp, and 70 Lump. Jump・ If the clip block is set, it will not receive 2-bit 34Vi changes. what This is because the read cycle uses it at the same time. Jump Ku If the rip block is not set, the readout vehicle will use a 9-bit lattice. Since no attempt is made to use nΔP in Te34, the JP buffer is updated. the In this case, the number from the 9-bit ripple counter 33 is the 9-pint holding latte 34. is transferred to complete the cycle.

When one vehicle is finished, a new vehicle is started. The program is peak Disable the counter, set the counter to zero, and say "Start of pitch period?" Return to the judgment step. In this case, the decision is "yes" because one program The beginning of one rehearsal signals the end of another, or vice versa. young If yes, the program will proceed to the next step called [Enable P counter]. It remains in the loop, that is, in the "no" loop of the decision block "WCNT?". child This advances the P counter for each write vehicle until the other end of the pinch period increments the counter until it is found or the count exceeds the upper limit This is the waiting time. If the count is less than or equal to 384, the loop continues until the end of the pinch period. repeated. Then, if the judgment block (“Is the pitch period over?”) is negative, that is, the next Unless a glontal pulse occurs, the program continues in a new loop. KP counter is incremented every write count. In this way, the program Count the number of write cycles between the internal pulses and check this interval. When it is connected, it is applied to the 9-pin latch 34.

FIG. 5 VC shows a modification of the control of the two-pointer system shown in FIG. No. FIG. 5 shows the necessary parts for explaining this modification from FIG. 3.

This example is for detecting glontal pulses and jumping the read pointer. As a solution to the big time-luck problem that occurs when you use this love stick. This is what I will say here. According to this embodiment, constant Provide an auxiliary reading pointer with the positional relationship of The operation can be improved by using it only for the purpose of supplying data to the data detector 32. Good is done.

The data from this read pointer R2 is sent to another D/A converter DAC3. 7 and buffered by another output buffer 36. will be protected. Depending on the speed capabilities of the normal DAC, a single DAC may Note that it is possible to operate with multiple capacitance by preparing 2 analog data. should be taken into consideration.

Depending on whether you add DACs or go with a single multiplexed DAC, A strobe timing signal will be requested from the access control process.

This signal, called R2 strobe, is generated from the write clock on-do (ODD). Generated by the access control process in response to a request to access RAM It is something.

The write block 10 may be modified in its frequency for improvement purposes by this embodiment. This inevitably results in double operation. Divide-by-2 clip-flop 38 divides the two intersections. send a signal. That is the write clock even (EVEN). This means that the A/D converter 12 is operated in the same manner and at the same frequency as the system in Figure 3. used to give signals to How to write digital data to memory Access to the RAM is synchronized from this signal in a manner similar to the base system.

A new signal, odd write (ODD), is added to the read program between each write. access the RAM using an access control processor to perform the process; .

This new read process therefore runs at the same control rate as the write process. will be carried out. The write operation of the write process is the same as in the base system. However, since a new readout operation has been added, the audio input signal is can be effectively shifted along the time axis before being applied to the pulse detector 32. Wear.

For analog global pulses, additional DAC functionality is required. Ru. This additional function can be achieved by adding DAC37 or by adding DAC16 in Figure 3 as appropriate. What can be achieved by multiplexing followed by analog demultiplexing? I can do it.

For digital glontral noculus detectors, the All that is required is to add a readout.

Regardless of the type of data being processed, the following instructions apply to the audio input signals described above. It will be a story about doing the time axis software of the issue.

The 9-pin ripple counter 20 uses the same write pointer counter as the basic system. It's unta. 4-bit adder 39 and W/R2 selection multiplex lob 40 A new offset structure allows time axis shifting.

An example of an offset code of 128 is shown as an input to a 4-bit adder 39. . If this number is determined by the upper 4 bits of the 9-pinto code, then Any number is fine. 128 is taken as 1/4 of the writable address of 512. This is what happened. The smallest possible value of the 4 pinto offset codes is 32. This corresponds to the deep 6-chi of data memory. Another code with an additional 6-chi is also possible.

The second R2 analog data is the timing signal offset selection and write. Depending on the phase relationship of the clock even, it precedes or follows the honor pointer. can be selected to be read from memory after. If write even and de At the same time as the data is written to the memory, the offcent selection is performed by the adder 39 with 4 bits. declares selection of 4 bits from counter 20, while offcent selection is 4 pins from counter 20. If the writing R2 strobe occurs when direct selection is not declared, the R2 analog The recording data is delayed from the audio input by the amount of the offset code. On the other hand, offset If the phase relationship of the point selection matches that of the writing option, the audio input will be delayed. deer However, because the memory is in a circular storage format, it takes less memory than the amount of offset codes. R2 audio input data of the full size of the memory (for example 512) from the audio input This has a delaying effect.

Another feature of this improvement is the compression/stretching discriminator 45. This logic block The write rate compares the read rate and the write rate is compared to the read rate. If the value exceeds the current value, the logic signal COMP is declared. accessed by this The control processor uses this information to determine which phase should be added to the offset selection. to judge.

Offcent selection is constantly at a logic level, i.e. either true or not true. However, the address resulting from counter 2° is effectively write even and write It is the same for the offset code, and is zero off regardless of the value of the offset code. Give a set condition. This state of zero off cents means that the read pointer is Jump back from the included pointer and calculate the data from that pinch period This is desirable for extended modes that jump beyond .

In the case of compression, the read pointer tends to lag behind the write pointer; And this delay becomes progressively larger until a jump is required. Why is it circular? The full size of the memory is filled and the write pointer immediately exceeds the read pointer and becomes non-existent. This could lead to control jumps and undefined splices of sequential output data. This is because that. Therefore, this overrun condition occurs just before and then If the jump occurs by nΔP, then the read pointer becomes It is located deep in the memory. In fact, this "jump as necessary" This logic ensures that the read pointer comes before the write pointer in circular memory. Become so. This behavior means that the audio waveform is in steady state with respect to its pinch frequency. The time eζ is completely forgivable. However, the pinch period enters a new value (g 1+d+ng) or was generated from voice input. In this case, the most recently calculated pinch period is a considerable fraction of the read pointer. I'll be happy with what's next.

For such a situation, the modified embodiment shown in FIG. 5, the R2(W) modified example, is effective.

Set the offset so that the R2 analog data comes from data deep in circular memory. The calculation of the pinch period was almost in line with that of the memory section. data, and the read pointer is actually in that section. I'm going to go camping.

Therefore, the preferred embodiment of this improvement is the compression/expansion discriminator (45 ) indicates compression (COMP=O) and elongation (COMP=1), and write Activates the offset selection declared in phase with the clockwise quadrature, so that R 2 Analog data is placed ahead of the write pointer by the code magnitude of the offset. Steady level A for zero offset when extracted vertically, (7) Offset selection It is possible to realize the operation according to the following.

(Note: MSB and LSB are the output of 9-bit triple counter 20) Still other embodiments of the invention apply to the basic system of FIG. 3 and also to the R2 system of FIG. The improved embodiment according to (W) also has two distinct features.

This is shown in Figure 6.

The first young monk is a means of calculating the multiple for nΔP. Here, ΔpH is exactly two measured between glontal pulses, where n can be a fixed value or a second It is obtained from the sexual characteristics of Therefore, this first characteristic is as small as possible. Pitch circumference of one or more jump buoys, one or more parts, set at intervals of (n-4) period (n = 2 + 3 + etc.) than the value obtained by counting It is often available, and even if the pinch frequency changes rapidly, it may be more up-to-date. The purpose of this invention is to provide a means for obtaining a jump value that can represent the change.

The second feature lies in the means for controlling [securing the interval]. write pointer moves away from the read pointer rapidly, requiring frequent jumps and It can be guaranteed that the protruding pointer contains at least one glontal pulse. When it becomes impossible to handle segments of sufficient length, the value of the compression ratio C increases. The more you jump, the more important the intervals between jumps become. high like that The compression ratio is larger to ensure that the segments are of sufficient length. (Disposal) This will require the use of the segment. However, with low compression ratios, short The card segment is preferred. Therefore matrix ROM4 2 can be fully utilized for large Cs, and can be fully utilized for Cs close to 1. This provides a means to provide a large memory that can be used for several minutes. Therefore, de The design goal is the absolute value of the jump corresponding to the disk segment. what This is because "ΔP" is part of the matrix input method. read/write frequency The wave number discriminator 44 compares the write rate and the read rate, and determines the compression ratio C by pin 3. It is shown as a binary number. Therefore, the output 02 is for compression, C0.6 is for expansion, And cl shows normal playback with no pinch changes. The P counter is Grontal. Generates a 9-pinto binary number indicating the interval of address locations between pulses. . This binary number is frequently updated. A total of 12 of these are in focus Lookup address for matrix ROM 42 configure the The matrix ROM 42 serves as its lookup operand. Then, prepare a 4-bit data element representing a value from n-1 to n=15. Ru.

4x4 = 1.6K bins) ROM is sufficient. Certainly Malynx ROM4 Considering the size of 2, there is no need for that.

A complex logic function on 12 pint addresses P and C is used to reduce this memory requirement. can do.

P counter 46 is a 9-pin rimple counter 33, start/stop conversion The rosin circuit 36 and the analog global pulse detector 32 Configure an interval counter for write pulses that are exactly between two pulses. and a limit detector 33. This is reflected in the system shown in Figure 3. This is an interrogation of the nΔP counter, but the limit detector 33 is sufficient for n-1. I can't stand ow.

The ΔP counter also stores new data in the 9-bit ΔP buffer 46. , do it by sending a signal to a continuous summing sequencer where new data is available each time send.

After each data is read from RAM17 (Figure 3), continuous addition/-Kenbu is the same. Receives the expected start signal "reading complete". If new from ΔP counter If new data is available, perform continuous addition/-bamboo 2 length n times. and n It completes its operation before the next read vehicle that requires ΔP. pause signal The signal is sent to the nΔP memory 43 of the Hamadzu 9 pinto, and it is cleared to zero. This ze The count appears in the 9-bit adder 40 along with the new ΔP from the ΔP counter. vinegar A trobo signal is issued from the sequence +j40 to the nΔP memory 43, and the ΔP and take the sum of zero.

If 4Ln(ΔP, C) -1, the sequence is completed.

If n (Δp, c) ≧ 2, consecutive strobes can be used for only a short period of time between each strobe. Emitted at fixed time intervals. Therefore, nΔP memory is Δp+o−ΔP, ΔP +ΔP = 2ΔP, 2ΔP + ΔP = 3ΔP, etc., and accumulate this until n feels satisfied. Continue with. Here, the value of n is a value obtained from the matrix ROM 42. example For example, high C values require a large n, and large P values require a small n.

Another mode of operation of the operation described in FIG. 3 will now be described. Its purpose is shown in Figure 5. Same as mentioned above. In other words, pinch cycle information and reading in case of compression (C>1) The objective is to minimize the delay between the pointer and the pointer.

The configuration for this improvement is shown in the third section. @ Same as the one in Figure 4, but with only one access control Variations may be required regarding the timing signals that can be generated depending on the length of the process.

This improvement method performs a "trial jump" between each and every read access. You can think of it as something. Therefore, a second de facto alert pointer is created and read. It operates at a readout rate and runs in front of the read pointer by nΔP. alert detection Instead of operating with the quantity R-W, the device 27 operates with respect to the quantity R+nΔp-w. do. The criteria for the alert (when the jump should be made) is Instead of "jumping", we would say "jumping without missing an opportunity".

The corrections for improvement apply only in the case of compression.

There are no changes in the case of postponement. In other words, the alert logic is "Camp". But as the read rate supersedes the write pointer Then, the two pointers will be close to each other only in shallow memory.

Therefore, pinch cycle information obtained from voice input (in practical terms, the write pointer (equivalent to the information written to memory by It can now be used to determine jump distance without introducing errors.

The pinch period extracted from the audio input corresponds to the signal information stored in shallow memory. is the corresponding pinch period. This is a desirable feature. The reason is that When the pinch period changes, the audio waveform belonging to that change must be in the latest memory. This is because it means. If the jump occurs on the same waveform, it's good This results in a splice. This is because the pinch period information used does not actually jump. This is because it becomes pitch period information of the signal. However, if the read pointer If it is allowed to go deep into the harpoon, the waveform it jumps around will be around its pinch. This means that the measurement was taken early in the period, and if the pinch period changes. , and is updated continuously, the nΔP value for jumping is no longer Not available.

``Jump at the right time'' in the case of compression, and ``jump on demand'' in the case of expansion. ” is the strategy adopted by the present invention to always operate with shallow memory. .

Implementing this improvement means that the compression/stretching decisions are similar to the basic system described above. This is the easiest method if it is not required. The read/write frequency discriminator is It performs this function as follows. Therefore, this improvement plan is applicable to the system shown in Figure 3 in case of postponement. Return to Tim.

In the case of compression, an additional feature called read counting is required. In other words, “trial "Camp" function is required.

The read υ access in Figure 3 is 1\ without modification, but the access including *= is a trial. Extended to perform jump and alert tests. Beginning of write access , the data is not only written to memory, but also the trial jump is read. and is commanded regarding the address counter. W/ΔP malteplek length 31 is W and and reset to +/-1-. Therefore, the trial jump and the current write count A comparison is performed between the That is, it is an alert test. Results of this test determines whether the attempted jump is retained as an actual jump.

During the remaining extension of the write access, the read address counter It returns to the original value, or simply returns to the state of R+nΔP, i.e. it does not jump. You will be required to either complete or complete the following: Attempt jumps are canceled in alert tests. often conclude that it should be done. Therefore, W/ΔP multiplex'' After returning +j'31 to ΔP, a second command is issued. This second conditional instruction R=F, +nP=nΔP1, that is, the initial value of the read pointer.

The last work item of extended write access updates the nΔP counter 33 (upda te). The nΔP used for the trial jump is the cancellation of the trial jump. Note that you cannot change it until you use it.

The criteria for alert testing to decide whether to retain a trial jump is simple. The question is whether there is "room" for jumping. If the trial jump is an error If the pointer (R+ΔP) is moved past the #r write pointer, It's not time to hold the jump, the attempted jump will be cancelled. . This method allows the read pointer to be deeper in memory than it should be. I try not to get into it. Only nΔP without overtaking the write pointer If the read pointer goes deep enough that it can jump, it immediately A jump occurs. This result shows that the same shallow memory is used for both compression/stretching. It is obvious that it is working.

An alternative to the embodiment shown in FIG. 6 is shown in FIG. The system in Figure 7 is the one in Figure 6. It has all the characteristics of Furthermore, as an additional function, n under certain specific conditions Added is the ability to provide a predetermined default constant for ΔP.

This new form reduces the complexity of continuous addition sequences - Fj41 and large ROM5. The complexity of a 9-pinto sign adder using 0 is eliminated. Cost to calculate nΔP All values are then expressed in the matrix ROM (50).

Under the condition that nΔP is within a reasonable range KS, it is expressed in matrix ROM50. The value will simply be a multiple of ΔP by the most advantageous integer n for the rate of C.

Therefore, when matrix ROM50 is being questioned in real time, its multiplication is It has already been done.

If ΔP is in an unreasonable range, the tabulated value will be the maximum for a particular C rate. should also be the "default" value determined to be appropriate.

It will be obvious to those skilled in the art that various variations on the implementation described above are possible. be. All modifications that fall within the scope of the claims appended hereto are considered to be included in the present invention. Must be.

Brief description of the drawing “IGl , -111□--] Procedural amendment (amendment) −・　J　J 2. Name of the invention Audio signal processing method and device using pitch period control 3: Person performing correction Relationship to the case: Patent applicant 5, r # iE Q’n no. 11, April 30, 1985 Shi → Riblind actor Michi 11" 6 Target of correction

Claims (1)

[Claims] +1) Bump the audio signal at the first rate and randomize the continuous signal length. Steps for writing system access memo IJK; To recover the stored sample as an output signal, the trap is reading the memory in the same sequential order as the writing order; determining a pinch period of the audio signal; determining a write position in the memory; When the separation width between The readout start position for successively reading out the recorded samples from the The last readout is equal to the number of consecutive samples within an integer number of pinch periods. It consists of a step of resetting it to a position away from the original position. The first and second rates are ratios according to a desired pinch transform of the audio input. How to change the pinch. (2) means for sequentially producing samples of the audio signal; an addressable memory; writing the samples to the memory at a first rate for recording and playback thereof; means for storing the data from the memory in an order according to the first created fc sample; means for reading the sample at a second rate; means for determining a pinch period of the audio signal; a write position and a read position in the memory; When the separation width from the protruding position becomes smaller than the predetermined difference, the data is recorded from the memory. Set the readout start position for consecutively reading out the samples recorded in the record as described above. The number of continuous length samples within an integer of the pinch period is equal to y, and the last readout is means for resetting the position away from the position; Utilizing the sequence of signals read from said memory to obtain an output signal An audio signal pinch conversion device comprising means. (3) In the device according to claim 2, the second rate is larger, so that the read position in the memory is the write position. , the reset means sets the continuous reading start position in the order as described above. Apparatus for shifting back and repeating said sample in said output signal. (4) The device according to claim @2, wherein the second rate is the same as the second rate. This causes the write location to touch the read location in the memory. When the time is near, the reset means shifts the continuous reading start position forward in the order. an apparatus for multiplying the components of the samples occurring in the output signal; (5) A run with an address position that stores the de-table that represents the audio signal. Dumb access memory; sampling the audio signal to create samples sequentially; means for writing said samples to address locations in said memory at a first rate; and; reading the samples from address locations in the memory at a second rate; means for producing a sample output signal; means for determining the pinch period of the audio signal; and a difference between write and read positions. is less than a predetermined minimum value or greater than a predetermined maximum value, then Set the continuous readout start address of samples to a series within an integer of the pitch period. The number of subsequent samples is equal to the number of addresses away from the last read address. , and this reset causes the difference in the positions to be smaller than the minimum value. Pinch transformation of the audio signal to be greater than or less than the maximum value Device. (6) In the device according to claim 5, the audio signal is the pinch period determining means. A device that can be used for input. (Sword) The device according to claim 5 is located at an address location close to the current write address location. a second means for reading said samples at said first rate at said second rate; The output of the stage is an input to the means for determining the pinch period. (8) In the device according to claim 7, the second rate is higher than the first rate. and the second means writes the memo at a position slightly preceding the writing position. A device that allows reading from files. (9) The device according to claim 7, wherein the second rate is higher than the first route. the second means is adjacent to the writing position, or A device adapted to read from said memory slightly behind it. Cl0) The apparatus according to claim 7, wherein the second reading means is The readout is performed slightly in advance of the reading means, and includes a switch means. In response to the determination that the second route is smaller than the second rate, the 2. At the same time, the output of the readout means is separated from the input of the means for determining the pinch period. device for connecting the audio signal to the input of the pinch period determining means. (11) The device operation according to claim 5, 6, 7, 8 or 9 a device for determining whether the timing period is outside of predetermined upper and lower limit values; means for applying a correction to the reset means when the reset period is outside the limit value; equipment containing. (12) In the device according to claim 11, the means for modifying the reset may include a predetermined Discard a series of samples from the output according to the value above the upper limit of the output. means for responding to the determination that the timing period is large, and the output according to the second predetermined value. The pinch period is smaller than the lower limit for discarding a series of samples from and means for responding to the determination. (13) In the device according to claim 12, the predetermined value is the minimum pinch period. A device selected to be a multiple of the value. (14) The device according to claim 11 is such that the current value of the pinch cycle is within the limit value. A means to store the current value only when the pinch period is If the number of samples is within an integer, reset the number close to y or control the cent means. Therefore, the current value of the pitch period is less than the minimum value or thicker than the maximum value. and means for responding to a determination of a cuttlefish. (15) The device according to claim 5 has a length that is within an integral multiple of the last determined pinch period. Apparatus including means for controlling the amount of reset such that the number of bulls. (16) The device according to claim 12, 14, or 15, wherein the integer value or a multiple thereof is the value of said final determined pinch period or is being achieved A device determined as a function of the rate of pinch change CS or both. (17) In the device according to claim Wc5, the pinch period of the audio signal is determined. the means for detecting the start of a pinch period, and the means for detecting the start of a pinch period; means for summing a predetermined number of pinch periods, and a means for summing a predetermined number of pinch periods; Use the above sum to control the reset means to reset the number by a number close to and means for using the device. (18) A method for determining the pinch period of the audio signal in the device according to claim 5. The stage comprises means for detecting the start of a pinch period, and the means comprises one or more means to sum consecutive pitch periods over which this sum is a predetermined minimum or maximum. Provide a means to monitor whether it is within the major limit and store the latest value of this total. restarting the updateable accumulation means and said summing means; and restarting said accumulation means. to determine whether the sum is within the limit in order to accumulate the sum in the step the number of samples within said sum of the latest pitch period is The total value newly stored in the storage means that controls the reset means to be set. device that includes means for utilizing (19) The device according to claim 2 or 5, wherein the second rate is - an integer of the pinch period that is smaller than the root and the reading position is advanced by that number The write address location is read as many times as the number of consecutive samples in If the reset address location is preceded by the reset address location, then reset device comprising means for controlling means for controlling Engraving (no changes in content) 1