JPS6049318B2 - polyphonic electronic musical instrument - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multitone electronic musical instrument that uses digital technology to generate a desired number of tones.

Conventionally, in order to generate multiple tones in a monophonic musical instrument such as a synthesizer, a high/low tone priority selection circuit is used.

For example, as an analog circuit, a constant current from a constant current circuit is passed through a resistor group consisting of n series resistors, and n key switches are pulled out between each resistor and short-circuited. This system preferentially produces the highest and lowest two tones. However, analog circuits have manufacturing and characteristic problems, such as constant current circuit adjustment, key switch chattering, and high-precision resistor groups. Therefore, by filing a patent application dated December 28, 1932, the present applicant used a digital circuit to control the serial data from the key data generation circuit using a counter and a latch circuit, giving priority to the two high and low tones. We proposed a selection circuit. This solved most of the problems mentioned above, but
Previous priority selection circuits only produced two high and low tones, and were unable to produce three or more tones. There is also a method of using a voltage-controlled oscillator for each key switch to produce three or more notes, but this method has the problem of not being able to apply effects when multiple pronunciations change, such as the voltament effect, and is expensive. I'm getting used to it. SUMMARY OF THE INVENTION An object of the present invention is to provide a multitone electronic musical instrument that uses digital technology to generate a desired number of tones and that can apply effects when the pronunciation changes.

In order to achieve the above object, the multitone electronic musical instrument of the present invention generates a plurality of musical tones in response to a plurality of key presses, and converts the output clock pulse of a clock pulse generator into a time division pulse. a key data generation circuit that sequentially scans each key, outputs one scan j synchronization pulse for each scan, and outputs a time-division signal of key presses as a key press signal; a counter that counts pulses and is reset by the one-scan synchronization pulse; a predetermined number of storage circuits that read and store the value of the counter at that time in response to a key press signal from the key data generator; a comparison circuit provided corresponding to each of the memory circuits, which compares the input and output of the memory circuit and outputs a coincidence signal; and a key press signal from the key data generation circuit and a coincidence signal from the comparison circuit. a control signal generation circuit that outputs a control signal according to the control signal generation circuit; and a control signal generation circuit that outputs a key press detection signal according to the control signal from the control signal generation circuit; a key press detection circuit that operates so as not to output a key press detection signal under the control of the key press detection circuit; and a musical sound wave forming circuit that converts the contents of the memory circuit into a musical tone based on the key press detection signal of the key press detection circuit. and a command circuit that reads the value of the counter into the storage circuit under the control of a key press signal from the key data generation circuit, an output signal of the comparison circuit, and a key press detection signal from the key press detection circuit. , a temporary operation in which the operation of the key data generation circuit and the operation of the counter are stopped for a predetermined period of time in response to a key press signal from the key data generation circuit and an output signal of the comparison circuit when the command circuit is in operation; and stopping means, the command circuit receives the output clock pulse from the clock pulse generator as input, and when there is no matching signal from the comparison circuit when the key press signal is input from the key data generation circuit. the time-division pulse generating means for a predetermined number of the memory circuits, and the key press detection circuit does not output a key press detection signal when the key press signal is input from the key data generating circuit; The apparatus is characterized in that it comprises a read signal generating means for generating a read signal for reading the value of the counter into the memory circuit using a time division pulse from the time division generation means. The present invention will be described in detail below with reference to examples.

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In the embodiment, it is assumed that the number of keys is 61 and three tones are generated. In the figure, a clock pulse generation circuit 11
The clock pulse 1 from 1 is input into the key data generation circuit 12, which sequentially scans the 61 keys and outputs serial data (SD) 2, which is a time-division signal of key presses, and outputs one pulse every scanning time. 1 scan synchronization pulse 3 is output.

Further, the clock pulse 1 from the clock pulse generation circuit 11 is input into a counter 13 and counted. In the case of 61 keys, this counter 13 is used to count 7, that is, 64, and is changed depending on the number of keys. Next, circuits 301, 302, 30 corresponding to the three tones are shown surrounded by broken lines in the figure.
3 is provided.

Since these are the same circuits connected in parallel, the circuit 301
I will explain about it. The signal of the counter 13 mentioned above is input to the memory circuit 141, stored by a read signal described later, D/A converted by the D/A converter 161, opened/closed by the gate circuit 171, and input to the musical sound waveform forming circuit 25. .

Comparator 151 is input to counter 1 to memory circuit 141.
The signal 3 is compared with the output signal, and when they match, a match signal 4 is output. One of the coincidence signals 4 is logically ANDed with the output of the keytator generating circuit 12 by an AND circuit 201 and inputted to the key press detection circuit 181 . The key press detection circuit 181 uses, for example, a shift register having α and Q1 outputs.
The output of the ND circuit 201 is input to the reset (R) terminal. In addition, one scan synchronization pulse 3 is input to the clock (C) terminal of the shift register, and if the AND circuit 20
1 maintains a low level during one scan time, the first scan synchronization pulse 3 causes Q. The output is at a high level, and the second -Q1 output 5 is at a high level, which is input to the gate circuit 171 and also branched and input to the AND circuit 191. This gate circuit 171 operates to cut off and not output the human input signal when the control signal is at a high level, and to allow it to pass when the control signal is at a low level. When the AND circuit 201 becomes high level during one scanning period, the one scanning synchronizing pulse 3 causes Q.
Since it is reset even when the output becomes high level, the Q1 output 5 continues to maintain a low level, passes the D/A converted signal input to the gate circuit 171, and sends it to the musical waveform forming circuit 25. Then, the low level Q1 output is branched and input to the AND circuit 191 to turn off the read signal of the memory circuit 1. The other of the match signals from the comparator 151 is input to the NOR circuit 21 along with the match signals from the comparators 152 and 153 of other circuits 302 and 303, and its output is input to the AND circuit 22 together with the serial data 2 from the key data generation circuit 12. is input. The output of the M circuit 22 is input to the counter 23, and this counter 23
It operates when the output of the ND circuit 22 is at a high level, and stops when the output is at a low level. The output of the counter 23 is input to the decoder 24, which sequentially generates high level outputs 61 to 63 on three output lines of the decoder 24. The signal is input to an AND circuit 191 into which signals from the key data generation circuit 12 and the key press detection circuit 181 are input, and
This is the read signal. Therefore, when the AND circuit 22 outputs a high level, that is, the pulse of serial data 2 is output from the key data generation circuit 12 and the circuits 301 to 3
When a low level signal that does not match the signal stored in each memory circuit 141 to 143 of 03 is output from the comparators 151 to 153, the counter 23 operates and the high level outputs 61 to 63 of the decoder 24 are moved. , circuits 301-303
If the Q1 output 5 of the shift register of the key press detection circuits 181 to 183 of the circuit capable of storing data is outputting a high level, one of the memory circuits 151 to 153 is searched for and stored. The above configuration is a basic circuit according to another proposal filed simultaneously with the present invention.

As a result, it is possible to realize a function of specifying multiple tones, especially three or more tones, and giving them priority pronunciation. However, the difficulty with this configuration is that
As mentioned above, in order to search for a memory circuit that can store each sound, a circuit that emits three sounds requires a maximum of two scanning periods, and the larger the number of sounds, the longer it takes to produce all the sounds. It takes a while. The present invention improves this point, and the outputs of the comparators 151 to 153 are input to the AND circuit 22 together with the serial data 2 from the key data generation circuit 12 via the NOR circuit 21. The output of is branched and inputted to a newly provided waiting control circuit 26, and when this AND circuit 22 becomes high level, the operation of the key data generation circuit 12 and counter 13 connected to this waiting control circuit 26 is kept constant. It stops time and maintains the state at that time.

During this stopped state, the decoder 24
The memory circuits 151 to 153 that can be scanned and stored are searched for. In this case, a certain period of time means that the decoder 24
This is the time to scan all of 1 to 153, and after that time, this state is automatically released. Also, AND circuit 2
When 2 becomes low level, this state is similarly released 9.
The operation will be explained based on the above configuration of the present invention.

When the keyboard is not pressed, the 1-scan synchronization pulse 3 is input to the clock (C) terminal of the shift register of the key press detection circuits 18, ~183, the Q1 output 5 becomes high level, and the gate circuits 171 ~ 173 are turned off. and blocks the D/A converted signal. Now C. E. ．． Assume that you pressed the G note on the keyboard.

The key data generation circuit 12 scans the keyboard from low to high tones in order to obtain a key press signal, and when it scans the C note, it generates a pulse and outputs a pulse to the AND circuit 191 of the circuit 301.
is input to. (In this case, AND of circuits 302 and 303
It is also input to circuits 192 and 193. ) It is assumed that the high level output 61 of the decoder 24 at that time is input to the AND circuit 191. In addition, since the Q1 output 5 of the shift register of the key press detection circuit 181 is at a high level due to the 1-scan synchronization pulse 3 input to the clock (C) terminal, the output of the AND circuit 191 is synchronized with the serial data 2. A read pulse is generated, and the signal of the counter 13 corresponding to the C note at that time is stored in the storage circuit 141. The memory circuit 141 stores the instantaneous signal and sends it to the D/A converter 1.
61. At that time, the comparator 151 outputs the coincidence signal 4, branches it into two, inputs one of the outputs to the AND circuit 201, ANDs this and the serial data 2, and resets the shift register of the key press detection circuit 181 (R). Input to the terminal to reset. At that time, the Q1 output 5 of the shift register becomes low level, turning on the gate circuit 171,
The signal from the D/A converter 161 is transferred to the musical sound waveform forming circuit 25.
input. In this case, the other branch output of the output 4 of the comparator 151 is input to the NOR circuit 21, and the output of the AND circuit 22 is set to a low level, so that the counter 23 is not operated. Next, when the key data generating circuit 12 scans the E sound, a pulse is generated and the . It is input to AND circuits 191-193.

At that time, the high level output 61 of the decoder 24 is output to the AND circuit 191 of the circuit 301, but since the Q1 output 5 from the shift register of the key press detection circuit 181 is at a low level, the AND circuit 191 is turned off and the memory is not stored. Not memorized in circuit 1. Moreover, there is no matching signal in the three comparison circuits 151 to 153, and . Since the AND circuit 22 outputs a high level, the waiting control circuit 26 operates as described above, the counter 23 operates, and the decoder 24 outputs a high level 6. is the AND circuit 19 of the circuit 302. is output to. Since the shift register output 5 of the key press detection circuit 182 of the circuit 302 is at a high level, the AND circuit 19 is activated.
A read pulse synchronized with the serial data 2 is generated at the output of the circuit 30, and the signal of the counter 13 corresponding to the E sound at that time is sent to the circuit 30. The data is stored in the storage circuit 142 of. Memory circuit 1
42 instantaneously stores the signal and outputs it to the D/A converter 162. At that time, the match signal 4 of the comparator 152 is branched into two, one of which is input to the AND circuit 202, and the logical product with the serial data 2 is taken, and the result is output to the reset (R) terminal of the shift register of the key press detection circuit 18) 2. and reset. At that time, the key press detection circuit 18. Since the Q1 output 5 of the shift register is at a low level, the gate circuit 172 is turned on to input the signal from the D/A converter 162 to the tone waveform forming circuit 25. As mentioned above, comparator 15. The other branch output of the coincidence signal 4 is input to the NOR circuit 21, which sets the output of the AND circuit 22 to a low level and outputs the counter 23.
does not work. Similarly, the key data generation circuit 12
When the sound is made into a running sound, the value of the counter 13 is stored and outputted to the musical sound waveform forming circuit 25.

In this way, the key data generation circuit 1
2 is C. ．． E. ．． Outputs a key press signal when the sound is G.

After that, the outputs 5 of the pressed key detection circuits 181 to 183 are outputted at a low level, so as long as the key L continues to be pressed without being newly stored in the storage circuits 141 to 143, the three tones will be output. Now, C. ．． E. ．． From G sound to C,. E. ．． Suppose you change the keyboard to the F note. C from key data generation circuit 12
．． Circuits 301 and 30 in response to a key press signal of E note. storage circuits 141 and 14. Since the corresponding signal is stored in , the contents are maintained as is, as described above. When scanning the next F note, a key press signal is input, but since the signal on the counter 13 at that time does not match the signals stored in the circuits 301, 302, and 303, the comparator 151
~153 output a low level signal 4.

Therefore, a high level is outputted to the AND circuit 22 via the NOR circuit 21, and the queue control signal 25 is activated to stop the key data generation circuit 12 and the counter 13 and maintain the current state. During this time, the counter 23 is operated for one pulse, and the outputs 61 to 63 of the decoder 24 are moved to search for a memory circuit that can store data. That is, the high level output of the decoder 24 is transmitted to the circuit 30 together with the high level serial data 2.
1 to 303 are input to AND circuits 191 to 193, circuits 301 and 302 are key press detection circuits 18, 18. Since a low level is being output from the , it will not be stored. On the other hand, the circuit 303 outputs a high level from the key press detection circuit 183, so the high level of the decoder 24 is ANDed.
When input to the circuit 193, a read pulse is output, and the signal of the stopped counter 13 corresponding to the F sound is stored in the memory circuit 143 and output to the D/-A converter 163. At this time, the comparator 153 outputs the coincidence signal 4 and
The signal is input to the D circuit 203 and the AND of the match signal 4 and the serial data 2 is calculated. By putting the output into the reset (R) terminal of the shift register of the key press detection circuit 183 and resetting it, the Q1 output 5 goes to a low level, and the gate circuit 173 is turned on and the signal from the D/A converter 163 is reset. The signal is input to the musical sound waveform forming circuit 25. Comparator 1 at the same time
The coincidence signal 4 of 53 causes the output of the AND circuit 22 to go to a low level through the NOR circuit 21, turning off the queue control circuit 26 and putting the key data generation circuit 12 and counter 13 into operation again. Eventually, the rendezvous control circuit 26 uses the key data generation circuit 12 while the decoder 24 is searching for a circuit that can store data.
There is also a function for stopping the operation of the counter 13. As a result, although conventionally a predetermined number of scans were required to search for a memory circuit capable of storing data, this can be shortened to one scan period. If four or more notes are pressed in this configuration, the first three notes are stored as described above, but when the fourth key press signal is output to the serial data, the coincidence signal 4 from the comparators 151 to 153 is Since there is no output, the AND circuit 22 outputs a high level, turns on the queue control circuit 26, and stops the operation of the key data generation circuit 12 and counter 13.
During that time, the high level output of the decoder 24 is sequentially transmitted to the memory circuit 14.
1 to 143-, but the three key press detection circuits 181 to 18 already stored in the memory circuits 141 to 143 are scanned.
Since a low level is output from 3, the 4th note is not memorized. In this way, only three tones are prioritized and selected. The queuing control circuit 26 is a circuit that is turned on for a certain period of time (in the case of this embodiment, two clocks) when the input continues to maintain a high level, and is then turned off.

Generally, the fixed period of time during which the waiting control circuit 26 is turned on is approximately the time during which the decoder 24 scans all of the memory circuits, and the time is set to vary depending on the number of memory circuits to be provided. In the embodiment, after the decoder 24 scans the serial data for the fourth note, the queue control circuit 26 is turned off and the key data generation circuit 12 and counter 13 operate to output serial data for the fifth note and above. Since the fourth and subsequent notes are not stored, they are not produced by the tone waveform forming circuit 25.

FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the waiting control circuit 26. As shown in FIG. As shown in the figure, the inverted output of the AND circuit 22 is input to the reset (R) terminal of the single-shot multivibrator 33, and the output of the AND circuit 22 is passed through the delay circuit 31 and one input of the AND circuit 32. The signal is input to a single-shot multivibrator 33, and the output of the multivibrator 33 is sent to the data generation circuit 12 and the counter 13, and its inverted output is fed back to the other input of the AND circuit 32.

That is, when the output of the AND circuit 22 is at a low level, since a high level is input to the reset (R) terminal of the single-shot multivibrator 33, a low level is outputted to its output. ．． When a high level is output from the AND circuit 22, a low level is input to the reset terminal of the multivibrator 33, and therefore the output becomes a high level, and the delay circuit 31
A single pulse having a pulse width set by the delay time is generated. As described above, the pulse width of this single pulse is the time required for the decoder 24 to scan all the memory circuits. In addition, with this configuration, when a pulse with a small pulse width is output from the AND circuit 22, it is reset when the pulse becomes a low level, so there is an advantage that the output of the single-shot multivibrator 33 also becomes a small pulse in synchronization. A shift register may be used instead of the counter 23 and decoder 24 in the embodiment.

Further, although digital circuits are used in the embodiment as the memory circuits 9141 to 143, a D/A converter may be provided between the memory circuits 9141 and the counter 13, and an analog circuit such as a sample hold circuit may be used. As explained above, according to the present invention, the value of the counter at that time is read into the memory circuit group in response to the key press signal from the key data generation circuit, and the input and output of this memory circuit are put into the comparison circuit group and matched. A multitone electronic musical instrument that outputs a signal, detects a key press signal in a key press detection circuit group based on this coincidence signal, and uses this as a control signal to send the contents of the storage circuit to a musical waveform forming circuit and convert it into a musical tone, When a key press signal is input from the key data generation circuit, by sequentially scanning the memory circuits, a command circuit consisting of a counter, a decoder, etc., outputs read pulses to the memory circuits for which no key presses are detected from the key press detection circuit. Furthermore, a waiting control circuit is added to this command circuit to stop the operation of the key data generating circuit and the counter for a certain period of time.

As a result, it has a function of specifying a number of multiple tones, especially three or more tones, and giving priority to this number of tones, and conventionally, it takes a maximum of two scanning periods to search for a memory circuit that can store multiple tones, for example, three tones. However, by providing a waiting control circuit, the time can be shortened to a certain period within one scanning period.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of an embodiment of the waiting control circuit of FIG.
11 is a clock pulse generation circuit, 12 is a key data generation circuit, 13 and 23 are counters, 141 to 143 are memory circuits, 151 to 15 are comparators, and 161 to 163 are D/A
Converter, 171-173 are gate circuits, 181-183
are key press detection circuits, 191 to 193, 201 to 203, 2
2 is an AND circuit, 21 is a NOR circuit, 24 is a decoder,
Reference numeral 25 indicates a tone waveform forming circuit, and reference numeral 26 indicates a waiting control circuit.

Claims (1)

[Scope of Claims] 1. In a multitone electronic musical instrument that generates a plurality of musical tones in response to a plurality of keys pressed, each key is sequentially scanned by converting the output clock pulse of a clock pulse generator into a time division pulse,
a key data generation circuit 12 which outputs one scan synchronization pulse for each scan and outputs a key press time signal as a key press signal; A counter 13 that is reset by one scan synchronization pulse, a predetermined number of memory circuits 14 that read and store the value of the counter at that time in response to a key press signal from the key data generator, and a predetermined number of memory circuits 14 that each correspond to the memory circuit. a comparison circuit 15 which is provided to compare the input and output of the storage circuit and outputs a coincidence signal, and outputs a control signal based on the key press signal from the key data generation circuit and the coincidence signal from the comparison circuit. control signal generation circuit 20
and outputs a key press detection signal in response to a control signal from the control signal generation circuit, and outputs a key press detection signal under control by the one-scan synchronization pulse when there is no control signal from the control signal generation circuit. A key press detection circuit 18 that operates so as not to output any output; and a musical sound waveform forming circuit 16 that converts the contents of the memory circuit into musical tones based on the key press detection signal of the key press detection circuit.
, 17, 25, the value of the counter is read into the storage circuit under the control of a key press signal from the key data generation circuit, an output signal of the comparison circuit, and a key press detection signal from the key press detection circuit. command circuits 19, 23, and 24 to control the operation of the key data generation circuit and the operation of the counter according to the key press signal from the key data generation circuit and the output signal of the comparison circuit when the command circuit operates. a temporary operation stop means 26 for stopping the operation for a predetermined period of time, and the command circuits 19, 23, 24 receive the output clock pulse from the clock pulse generator and input the key press signal from the key data generation circuit. operates if there is no match signal from the comparison circuit when inputting
When a key press signal is input from the time division pulse generating means 23 and 24 for generating time division pulses for a predetermined number of the memory circuits and the key data generation circuit, a key press detection signal is output from the key press detection circuit. If not, read signal generating means 19 reads the value of the counter into the storage circuit using a time division pulse from the time division generation means and generates a signal.