JPS6047668B2 - Signal transmission control device - Google Patents
Signal transmission control deviceInfo
- Publication number
- JPS6047668B2 JPS6047668B2 JP53150886A JP15088678A JPS6047668B2 JP S6047668 B2 JPS6047668 B2 JP S6047668B2 JP 53150886 A JP53150886 A JP 53150886A JP 15088678 A JP15088678 A JP 15088678A JP S6047668 B2 JPS6047668 B2 JP S6047668B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- control device
- transmitting
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
本発明は信号伝送制御装置に関し、特に複数の記憶装置
から同時に信号が送出されるメモリシステムの信号伝送
制御装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal transmission control device, and more particularly to a signal transmission control device for a memory system in which signals are simultaneously sent from a plurality of storage devices.
従来、この種の記憶装置においては、中央処理装置から
動作要求信号を受け付けると、要求のあつた中央処理装
置に対して要求受付信号を送出するように制御を行つて
いた。Conventionally, in this type of storage device, when an operation request signal is received from a central processing unit, control is performed such that a request acceptance signal is sent to the central processing unit that has made the request.
この場合に、記憶装置を複数個使用してメモリシステム
を構成すると、リフレッシュ時においては通常全記憶装
置が同時に動作を開始し、要求受付番号が同時に送出さ
れる。このとき、要求受付信号の伝送素子として定電流
駆動素子を使用し、しかも要求受付信号の伝送線をバス
接続した場合には、リフレッシュ動作時において前記定
電流駆動素子が多数動作するので、中央処理装置の要求
受付信号の受信回路の受信素子の入力電流が過大になる
。このため、要求受付信号の受信が不可能になつたり、
また最悪の場合には、受信回路の受信素子の最大定格を
越える要求受付信号の電流によつて該受信素子を破壊す
るおそれがあるので、要求受付信号を伝送する信号線は
、記憶装置と個別に中央処理装置とリード接続していた
。In this case, if a memory system is configured using a plurality of storage devices, all the storage devices usually start operating at the same time during refresh, and request acceptance numbers are sent out at the same time. At this time, if a constant current drive element is used as a transmission element for the request acceptance signal, and the transmission line for the request acceptance signal is connected to a bus, many of the constant current drive elements operate during the refresh operation, so the central processing The input current of the receiving element of the receiving circuit for the request acceptance signal of the device becomes excessive. For this reason, it may become impossible to receive the request acceptance signal, or
In the worst case, the current of the request acceptance signal that exceeds the maximum rating of the receiving element of the receiving circuit may destroy the receiving element, so the signal line that transmits the request acceptance signal should be connected to the storage device separately. It had a lead connection to the central processing unit.
このため、記憶装置の増加にともなつて、要求受付信号
を伝送するリード接続した信号線数の増加および中央処
理装置内の受信回路数の増加のためメモリシステムが高
価となる欠点があつた。本発明の目的は、上記従来の九
色を除去するために、要求受信信号を伝送する信号線を
バス接続した信号伝送制御装置を提給することにある。For this reason, as the number of storage devices increases, the number of lead-connected signal lines for transmitting the request acceptance signal increases and the number of receiving circuits within the central processing unit increases, making the memory system expensive. SUMMARY OF THE INVENTION An object of the present invention is to provide a signal transmission control device in which signal lines for transmitting request reception signals are connected to a bus in order to eliminate the conventional nine colors.
本発明は、複数の記憶装置から同時に信号が送出される
メモリシステムにおいて、中央処理装置の受信回路と、
この受信回路へリフレッシュ時に選択された信号のみを
送出する前記記憶装置の送信回路と、この送信回路と前
記受信回路とを接続するバス接続した伝送路とを備えて
いることを特徴とする信号伝送制御装置を提供すること
にある。次に本発明の実施例について図面を参照して説
”明する。The present invention provides a memory system in which signals are simultaneously sent from a plurality of storage devices, including a receiving circuit of a central processing unit;
Signal transmission comprising: a transmitting circuit of the storage device that transmits only a signal selected at the time of refresh to the receiving circuit; and a bus-connected transmission line connecting the transmitting circuit and the receiving circuit. The purpose is to provide a control device. Next, embodiments of the present invention will be described with reference to the drawings.
第１図は回路図、第２図は第１図における回路のタイム
チャートを示す。FIG. 1 shows a circuit diagram, and FIG. 2 shows a time chart of the circuit in FIG.
これらの図面において、差動信号受信素子１０ａ〜１０
ｎおよび終端回路１００を有し中央処理装置の一部であ
る受信・回路１０は、バス接続された信号線２０、２１
に接続し、これらの信号線２０、２１には記憶装置の一
部である送信回路３１、３２・・・３ｎが接続している
。これらの送信回路３１、３２・・・３ｎは、差動出力
形定電流駆動素子３１ａ，３２ａ・・・３旭アンドゲー
ト３１ｂ，３２ｂ・・・３ｎｂ１アンドゲート３１ｃ，
３２ｃ・・・３ｎｃおよびオアゲート３１ｄ，３２ｄ・
・・３ｎｄから構成され、これらの送信回路３１，３２
・・・３ｎには終端回路４０が接続している。また、送
信回路３１，３２，３ｎにおけるＡｌ，ａ２・・・Ａ．
，は送信回路３１，３２・・・３ｎの要求受付信号、Ｂ
ｌ，ｂ２・・・Ｂｎは送出指定情報信号、Ｃｌ，Ｃ２・
・・Ｃｎはアンドゲート３１ｂ，３２ｂ・・・３ｎｂの
出力信号Ｄｌ，ｄ２・・・Ｄｎは定電流駆動素子３１ａ
，３２ａ・・・３ｎａの正出力信号、ｄ″１，ｄ″２，
・・・ｄ″。は定電流駆動素子３１ａ，３２ａ・・・３
ｎａの負出力信号、Ｒｅｆはリフレッシュ情報信号を示
し、Ｄは信号線２０に発生する信号、Ｄ″は信号線２１
に発生する信号を示している。上記構成の本発明に係る
信号伝送制御装置においては、リフレッシュ情報信号が
″０″レベル時で書込または読出動作要求が行われる場
合には、要求を受け付けた記憶装置の送信回路３１〜３
ｎの要求受付信号ａ１〜Ａｎが“゜１゛となり、送信回
路３１〜３ｎのオアゲート３１ｄ〜３ｎｄの出力が６′
ｒ１となるので、アンドゲート３１ｂ〜３油の出力Ｃ１
〜Ｃｎが“１゛レベルとなる。In these drawings, differential signal receiving elements 10a to 10
A receiving/circuit 10, which is part of a central processing unit and has a terminal circuit 100 and a terminal circuit 100, has signal lines 20, 21 connected to a bus.
These signal lines 20 and 21 are connected to transmitting circuits 31, 32, . . . 3n, which are part of the storage device. These transmitting circuits 31, 32...3n include differential output type constant current drive elements 31a, 32a...3 Asahi AND gates 31b, 32b...3nb1 AND gate 31c,
32c...3nc and or gate 31d, 32d.
...3nd, these transmitting circuits 31, 32
...3n is connected to the termination circuit 40. Furthermore, Al, a2...A.
, are request acceptance signals of the transmitting circuits 31, 32...3n, B
l, b2...Bn are transmission designation information signals, Cl, C2...
...Cn is the output signal Dl, d2...Dn of the AND gates 31b, 32b...3nb is the constant current drive element 31a
, 32a...3na positive output signals, d″1, d″2,
...d''. constant current drive elements 31a, 32a...3
negative output signal of na, Ref indicates a refresh information signal, D indicates a signal generated on the signal line 20, and D'' indicates the signal line 21.
It shows the signal generated in In the signal transmission control device according to the present invention having the above configuration, when a write or read operation request is made when the refresh information signal is at the "0" level, the transmission circuits 31 to 3 of the storage device that received the request are
The request acceptance signals a1 to An of n become "゜1", and the outputs of the OR gates 31d to 3nd of the transmitting circuits 31 to 3n become 6'.
Since it becomes r1, the output C1 of AND gate 31b~3 oil
~Cn becomes "1" level.
このため、送信回路３１〜３ｎの定電流駆動素子３１ａ
〜３ｎａが駆動され、この定電流駆動素子３１ａ〜３ｎ
ａの差動出力Ｄｌ，ｄ″１がインピーダンス状態から信
号伝達状態になり、信号線２０，２１に信号が伝送され
、中央処理装置の受信回路１０の差動信号受信素子１０
ａ〜１０ｎで受信される。次にリフレッシュ情報信号が
゜“１゛レベル時で！リフレッシュ動作要求が行われる
場合には、要求を受け付けた複数の記憶装置の送信回路
３１〜３ｎの要求受付信号ａ１〜Ａｎがそれぞれ“゜１
゛レベルとなる。また送信回路３１〜３ｎのそれぞれの
アンドゲート３１ｃ〜３ｎｃおよびオアゲート３１ｄ〜
３ｎｄによつて、送信回路３１〜３ｎのそれぞれの送出
指定情報信号ｂ１〜Ｂｎが有効となる。このため、送信
回路３１〜３ｎのそれぞれのアンドゲート３１ｂ〜３ｎ
ｂにより、それぞれの送出指定情報信号へ〜Ｂｎが゜゜
１゛レベルであるク送信回路３１〜３ｎの要求受付信号
ａ１〜Ａｎのみが有効となり、送信回路３１〜３ｎのそ
れぞれのアンドゲート３１ｂ〜３ｎｂの出力信号Ｃ１〜
Ｃｎが６゜１゛レベルとなる。このため出力信号ｑ−Ｃ
ｎが゜“１゛レベルとなつた送信回路３１〜３ｎの定電
流駆動素子３１ａ〜３Ｔ１ａのみが駆動されて、信号線
２０，２１上に同時に信号が送出される。この場合、送
出指定情報信号ｂ１〜Ｂｎの作成方法はたとえば各記憶
装置内でスイッチを使用して発生冫させてもよいし、ま
たレジスタに記憶させた情報を使用してもよい。このよ
うに本発明に係る信号伝送制御装置によれば、リフレッ
シュ動作時には、送出指定情報ｂ１〜Ｂｎで指定された
送信回路３１〜３ｎのみが動・作するので、多数の送信
回路３１〜３ｎが同時に動作しても受信回路１０の差動
受信素子１０ａ〜１０ｎを破壊したり、信号が伝送でき
なくなることがなくなる。Therefore, the constant current drive element 31a of the transmitting circuits 31 to 3n
~3na are driven, and these constant current drive elements 31a~3n
The differential output Dl, d''1 of a changes from an impedance state to a signal transmission state, and signals are transmitted to the signal lines 20 and 21, and the differential signal receiving element 10 of the receiving circuit 10 of the central processing unit
It is received at a to 10n. Next, when a refresh operation request is made when the refresh information signal is at the ゜1゛ level, the request acceptance signals a1 to An of the transmitting circuits 31 to 3n of the plurality of storage devices that have accepted the request are set to ゜1, respectively.
゛ level. Also, the AND gates 31c to 3nc and the OR gates 31d to 31 of the transmitting circuits 31 to 3n, respectively.
3nd, the transmission designation information signals b1 to Bn of the transmission circuits 31 to 3n become valid. For this reason, each of the AND gates 31b to 3n of the transmitting circuits 31 to 3n
As a result of b, only the request acceptance signals a1 to An of the transmission circuits 31 to 3n whose Bn is at the ゜゜1゛ level to the respective transmission designation information signals become valid, and the AND gates 31b to 3nb of the respective transmission circuits 31 to 3n The output signal C1~
Cn becomes 6°1° level. Therefore, the output signal q-C
Only the constant current drive elements 31a to 3T1a of the transmitting circuits 31 to 3n whose n has reached the level ゜"1" are driven, and signals are simultaneously sent out onto the signal lines 20 and 21. In this case, the sending designation information signal For example, b1 to Bn may be generated using a switch in each storage device, or information stored in a register may be used.In this way, the signal transmission control according to the present invention According to the device, during the refresh operation, only the transmitting circuits 31 to 3n specified by the transmission designation information b1 to Bn operate, so even if a large number of transmitting circuits 31 to 3n operate at the same time, the difference in the receiving circuits 10 will be ignored. This prevents the dynamic receiving elements 10a to 10n from being destroyed and signals not being able to be transmitted.
なお、本発明は上記実施例に限定されることなく種々の
応用例および変形例があり、たとえば送信回路に差動出
力形定電流駆動素子の代わりに一出力形定電流駆動素子
を使用してもよく、また中央処理装置は２台以上の場合
も同様な機能を発揮する。It should be noted that the present invention is not limited to the above-mentioned embodiments, but has various applications and modifications. For example, a single output type constant current drive element may be used instead of a differential output type constant current drive element in the transmitting circuit. Furthermore, the same function can be achieved even when there are two or more central processing units.
本発明は以上説明したように送信回路が同時に動作して
も受信回路を破壊したり、信号が伝送できなくなること
がなくなり、要求受付信号を伝送する信号線はバス接続
が可能となるので、信号線数および受信回路数の削減が
図れてメモリシステムが経済的になる効果を有する。As explained above, in the present invention, even if the transmitting circuits operate simultaneously, the receiving circuit will not be destroyed or the signal will not be transmitted, and the signal line for transmitting the request acceptance signal can be connected to a bus, so the signal This has the effect of reducing the number of lines and receiving circuits, making the memory system more economical.
図面は本発明に係る信号伝送制御装置の一実施例を示し
、第１図は回路図、第２図は第１図に示した回路のタイ
ムチャートである。
１０・・・・・受信回路、１０ａ〜１０ｎ・・・・・・
差動信号受信素子、２０，２１・・・・・信号線、３１
〜３ｎ・・送信回路、３１ａ〜３１１ａ・・・・・・定
電流駆動素子、３１ｂ〜３ｎｂ，３１ｃ〜３ｎｃ・・・
・・・アンドゲート、３１ｄ〜３ｎｄ・・・・・・オア
ゲート。The drawings show an embodiment of the signal transmission control device according to the present invention, in which FIG. 1 is a circuit diagram and FIG. 2 is a time chart of the circuit shown in FIG. 1. 10... Receiving circuit, 10a to 10n...
Differential signal receiving element, 20, 21...signal line, 31
~3n...Transmission circuit, 31a~311a... Constant current drive element, 31b~3nb, 31c~3nc...
...and gate, 31d~3nd...or gate.
Claims (1)
システムにおいて、中央処理装置の受信回路と、この受
信回路へリフレッシュ時に選択された信号のみを送出す
る前記記憶装置の送信回路と、この送信回路と前記受信
回路とを接続するバス接続した伝送路とを備えているこ
とを特徴とする信号伝送制御装置。1. In a memory system in which signals are simultaneously sent from a plurality of storage devices, a receiving circuit of a central processing unit, a transmitting circuit of the storage device that sends only a signal selected at refresh time to this receiving circuit, and this transmitting circuit. A signal transmission control device comprising: a bus-connected transmission line connecting the receiving circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53150886A JPS6047668B2 (en) | 1978-12-05 | 1978-12-05 | Signal transmission control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53150886A JPS6047668B2 (en) | 1978-12-05 | 1978-12-05 | Signal transmission control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5577084A JPS5577084A (en) | 1980-06-10 |
| JPS6047668B2 true JPS6047668B2 (en) | 1985-10-23 |
Family
ID=15506524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53150886A Expired JPS6047668B2 (en) | 1978-12-05 | 1978-12-05 | Signal transmission control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047668B2 (en) |
-
1978
- 1978-12-05 JP JP53150886A patent/JPS6047668B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5577084A (en) | 1980-06-10 |
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