JPS6046606A - Delay circuit of signal - Google Patents

Abstract

PURPOSE:To make line length variable and to set up pulse delay time highly accurately by connecting two signal transmission lines formed on a multilayer interconnection substrate through a conductor. CONSTITUTION:Two printed circuit patterns 7, 8 form two L-shaped signal transmission lines in a ground layer 9. In said transmission lines, parallel line parts with a slight gap are connected through the conductor 11. Since the line length lcan be varied by changing the position of the conductor, the delay time of a signal can be changed and controlled highly accurately. The deterioration of frequency characteristics by the capacity of the lines can be prevented by dividing the lines like a slit and connecting them in series if necessary.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a signal delay circuit that uses a multilayer wiring board as a delay element to delay a pulse signal with high precision for an extremely short period of time, and is particularly applicable to memory, logic LSI, etc. This invention relates to a signal delay circuit that allows the timing of a test pulse signal to be controlled or adjusted with high precision during testing.

[Background of the invention]

Generally, in order to delay a pulse signal, for example, Fig. 1 (
As shown in a) and (b), the pulse signal Vt is connected to the resistor l.
and integrate in the integral (b) path which is the capacitor 2,
A comparator 3 compares the integrated output vi' with a comparison voltage Er obtained from a resistor 4 to which a constant voltage Vc is applied, thereby obtaining a delayed pulse signal Vo. In this case, the time td by which the pulse signal ■l is delayed is controlled by the time constant of the integrating circuit or the comparison voltage Er. For example, when the time constant of the integrating circuit is constant, the comparison voltage Erl
, Br2, the comparison voltage Erl,
The delayed pulse signals Vol and Vo2 are obtained after time tdr11 and tdr2 corresponding to Er2 have elapsed, respectively.

By the way, a problem in delaying the pulse signal in this manner is that the delay time cannot be set with high precision due to fluctuations in the input pulse signal υ waveform and the level of the comparison voltage.

Furthermore, the pulse width of the delayed pulse signal does not match that of the input pulse signal and changes. 1st
As shown in Figure (b), it can be seen that the rising delay time tdrl and the falling delay time tdf1 do not match. Similarly, the rising delay time tdr2 and the falling delay time tdf2 do not match, and the direction of change is generally opposite to that of the falling delay time and the falling delay time. , the pulse width of the delayed pulse signal may no longer match that of the input pulse signal.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal delay circuit in which the delay time can be set with high accuracy and the pulse width of the delayed pulse signal can be made the same as that of the input pulse signal. Another object of the present invention is to provide a signal delay circuit that can selectively obtain pulse signals having different delay times as variable delay times.

[Summary of the invention]

For this purpose, the present invention provides at least two signal transmission paths formed between a signal line layer and a ground layer so that at least a portion thereof is a parallel line adjacent to the substrate surface in a vertical or horizontal direction. Route - installed on multilayer wiring board,
The signal line layer in the parallel line portion can be connected at any position. Further, in the present invention, at least two or more transmission lines are provided in series on the same multilayer wiring board so that the positions of the series connection can be changed, and signals from a predetermined transmission line portion are selectively extracted as delayed pulse signals.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 2 and 6.

First, before going into a detailed explanation of the present invention, its principle is explained in Fig. 2 (
1k) l The explanation based on (b) is as follows.

That is, the principle is that if a pulse signal Vt is applied to the input end of a coaxial cable 5 with line length t as a signal transmission path,
A coaxial cable 5 is placed on the output end terminated with a terminating resistor 16.
A delayed pulse signal Vo having the same waveform as the pulse signal v1 is obtained after a time td determined by the propagation speed at and the line length t. The delay time td in this case can be calculated as follows, where μ is the effective magnetic permeability of the line and ε is the dielectric constant.

t4 = z()7 ・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・(1) Therefore, when using a signal transmission line in which the delay time td is determined in this way, the line length t, magnetic permeability μ, and permittivity ε are 10 Since it is possible to easily achieve a certain degree of stability, it is possible to achieve extremely high stability compared to the case using an integrating circuit such as a resistor and a capacitor, and also to achieve highly accurate signal delay without waveform distortion. . However, it is clear that the delay time cannot be made variable unless the propagation speed on the signal transmission path is constant and the line length is made variable. Therefore, the present invention allows the line length to be easily varied when delaying a signal using such a signal transmission line.

FIGS. 3(a) and 3(b) show a plane and a partially omitted cross-section taken along line AA' of an example of the configuration of a signal delay circuit as a multilayer wiring board according to the present invention.

According to this, a ground layer 9 is formed on the lower surface of the base material 10, while a printed wiring pattern 7.8 is formed on the upper surface of the base material 10 as shown in the figure, and two L A letter-shaped signal transmission path is formed. As shown in the figure, since some of these signal transmission lines are parallel lines with a slight interval, by connecting these signal transmission lines with conductors 11 at arbitrary positions of this parallel line part, the line length t can be made variable.

In the example shown in FIG. 3(a), it is clear that the line length is determined as follows.

t=tl+t2+zt!・・・・・・Yamakawa・・・・
...+21 In formula (2), the line length t1. Since A2 is known and the line length tX is within a certain range, the line length t can also be varied within a certain range. As a result, in the case of a normal laminated printed wiring board, a change in the line length of 1 Otnn can result in a change in delay time of about picoseconds.

However, when configuring a signal delay circuit in this way, there are parallel line sections on the same plane, so electrostatic and electromagnetic coupling can cause distortion in the waveform in the case of a high-speed waveform with a large rising speed. This may cause a decrease in accuracy.

FIGS. 4(a) and 4(b) show a partially omitted perspective view and a partially omitted cross-section of a configuration in which such a problem has been solved. As shown in the figure, in this example, the ground layer 9 is formed in a single layer in the base material 10, and the printed wiring patterns 7 and 8 in FIGS. printed wiring pattern 77.8 in the parallel line portion
The connection is made by a rod-shaped conductor 13. The ground layer 9 blocks the coupling between the printed wiring patterns 7 and 8. The printed wiring pattern 7°8 in the parallel line portion is provided with holes 15 facing each other at regular intervals, and by selecting one of the holes 15,
Correspondingly, if the rod-shaped conductor 13 is passed through the slightly larger diameter hole 14 similarly drilled in the base material 10 and the ground layer 9, the printed wiring pattern 7°8 can be passed through the rod-shaped conductor 13. It is something that is connected. Figure 4(c)
Two ground layers 9 are formed in the base material 10.

The situation is shown in Figure 4 (
It is similar to b). Note that the reference numeral 12 in FIG. 4(a) indicates a pattern for a terminal connected to the printed wiring pattern 8 via a rod-shaped conductor 13.

By the way, the problem with connecting parallel line sections as described above is that the shorter the delay time is obtained, the more the portion of the parallel line section that is not used as a delayed signal transmission path increases. It is electrically connected as a capacitive or inductive load to a portion used as a delayed signal transmission path. If the parallel line section is short, there is no particular problem, but if it is long, the rise p of the delayed pulse signal is not good and the effective line length is longer than the geometric line length. This means that the variable range tends to become narrower.

FIG. 5 shows a signal delay circuit designed to alleviate such problems, taking the example shown in FIG. 3 as an example. As shown in the figure, the printed wiring pattern in the parallel line section is cut by slits 16 at regular intervals, and when the required line length is covered, the cut patterns are connected by conductors 17 as necessary. Moreover, the printed wiring patterns 7 and 8 are connected by the conductor 11. In this case, the portion not used as a delayed signal transmission path will be within a certain limit. In addition, by providing the slits 16 alternately as shown in FIG. 5, the number of connection points by the conductor 17 can be reduced, and the load effect is constant regardless of the connection position between the printed wiring patterns 7 and 8 by the conductor 11. Therefore, it can be said that it is preferable.

Finally, a signal delay circuit according to the present invention in which a delayed pulse signal can be selectively taken out will be described. FIG. 6 schematically shows the structure in a perspective view.

According to this, at least one ground layer (not shown) is formed in the base material of the multilayer wiring board 4.
Printed wiring patterns 21 to 2n are formed on the upper and lower surfaces of the multilayer wiring board 4 so as to have greatly variable line lengths and are connected in series, and are terminated by applying a resistor. In addition, printed wiring patterns 27, 21° 22
, 23. The connecting portion between u and 25, and furthermore, the terminal portion of the printed wiring pattern are connected to the multilayer wiring board 29.
It is designed to be drawn into a multiplexer 19 mounted on the top surface. Since the line length in the printed wiring patterns 21 to 26 is made variable by the rod-shaped conductor 13, the pulse signal applied to the input terminal is variable and delayed in each of the printed wiring patterns 21 to 26 via the printed wiring pattern n. It is transmitted to the rear end. The multiplexer 19 selectively outputs the delayed pulse signal from either the connection section or the termination section onto the output terminal 18, thereby producing a delayed pulse whose delay time is precisely controlled. This means that a signal can be obtained. When the multiplexer 19 is configured as an ECL, switching can be performed at a speed of 5 nanoseconds or less. Although slits are not provided in the parallel line portions in this example, it is of course possible to provide slits.

〔Effect of the invention〕

As explained above, the present invention is designed to make the line length of the signal transmission path formed in the multilayer wiring board variable. Therefore, according to the present invention, there is an effect that the delay time of the delayed pulse signal can be set with high accuracy while the pulse width is made the same as the pulse width of the input pulse signal. Furthermore, since the present invention selectively obtains pulse signals on a predetermined portion of a signal transmission path with variable line length, in addition to the above-mentioned effects, the delay time can be changed to provide different delay times. This has the effect of selectively obtaining pulse signals with

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams showing the configuration of an example of a signal delay circuit according to the prior art and input/output signal waveforms of an example of its main parts, and FIG. 2(&) r (b) 3(a) is a diagram showing a coaxial cable as a signal transmission path and its input/output signal waveforms for explaining the signal delay principle according to the present invention.
) l'(b) is a diagram showing a plane of an example of the signal delay circuit according to the present invention and a partially omitted cross-section along A-A'i thereof, and FIGS. FIG. 4(C) is a diagram illustrating a configuration of another example of a signal delay circuit and a cross-section of a partially omitted essential part, and FIG. FIG. 5 is a diagram for explaining a desirable pattern of the parallel line portion in the signal transmission line according to the present invention, and FIG. 6 is a diagram showing the present invention in which pulse signals having different delay times can be selectively extracted. 1 is a diagram illustrating a configuration of an example of a signal delay circuit according to FIG. 7.8.21-27...Printed wiring pattern, 9.
...Ground/W, 10... Base material, 13... Rod-shaped conductor, 19... Multiplexer agent Patent attorney Tadashi Akimoto Actual first cause (a) 1゜Figure 1 (b) 〉 Method 〈Two〉

Claims (1)

[Claims] (1) At least two signal transmission paths are formed between the signal line layer and the ground layer so that at least a portion of the line is a parallel line adjacent to the substrate surface in the vertical or horizontal direction.
A signal delay circuit characterized by a structure in which a transmission line can be connected in series on a layered wiring board with the same length, and a signal line layer in a parallel line portion can be connected at any position. 2. The signal delay circuit according to claim 1, wherein the signal line layer in the parallel line portion is cut at regular intervals. 3 At least two signal transmission paths formed between the signal line layer and the ground layer are connected in series on the same length layer wiring board so that at least a part of the signal transmission path is a parallel line adjacent to the board surface in the vertical or horizontal direction. With the signal line layers in the parallel line portion connected at arbitrary positions, the pulse signal on the predetermined signal transmission line 20 is selectively handled by a selection means mounted on the multilayer wiring board. A signal delay circuit characterized by a configuration in which 4. The signal delay circuit according to claim 3, wherein the signal line layer in the parallel line portion is cut at regular intervals.