JPS6046592B2 - Phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides horizontal AFC (AUTOMATIC FREQIJENCY CONTROL) for television receivers.
The present invention relates to a phase detection circuit of an OL) circuit.

The prior art will be explained below based on the drawings.

FIG. 1 is a loop block diagram of the AFC circuit. A voltage controlled oscillator (hereinafter abbreviated as VCO) 3 has a predetermined time constant (
1/horizontal oscillation frequency), and its output is shaped into a pulse waveform and amplified by the shaping output circuit 4. The output signal is converted into a sawtooth wave by the integrating circuit 5. The sawtooth wave comparison signal c and the reference input signal (horizontal synchronization signal) a are phase-compared by the phase detection circuit 1.
outputs a signal proportional to the set phase difference. The signal output from the phase detection circuit 1 is converted into a direct current by a low-pass filter 2. The output voltage of the low-pass filter 2 controls the oscillation frequency of the VCO 3, and the output signal of the shaping output circuit 4 is converted to a reference input signal a. Control is performed to obtain a predetermined phase relationship. FIG. 2 shows an example of a conventional phase detection circuit 1 in an AFC circuit having such a configuration. In the figure, transistors 6 and 7 constitute a differential switch circuit, and their bases are biased with the same voltage via resistors 13 and 14.

A comparison signal input terminal B is provided at the base of the transistor 7. A current mirror load constituted by transistors 8 and 9 and resistors 15 and 16 is connected to the collectors of transistors 6 and 7, respectively, and a single-ended push-pull output terminal C is provided at the collector of transistor 7. Transistor 10 and resistors 17, 18
, 19 constitute a constant flow circuit that draws in a constant flow determined by the magnitude of the input signal when the reference signal input terminal A receives an input. In this configuration, when a synchronizing pulse signal is input to the reference signal input terminal A, the transistor 10 outputs IEIO((VINX)-VBEIO)/R
17R18+R19 However, IEIO: Transistor 1
0 emitter current V, N: Synchronous pulse signal voltage VBEIO: A current 1E10 determined by the base-emitter voltage of the transistor 10 is drawn.

Therefore, according to the polarity of the comparison signal input from the comparison signal input terminal B to the base of the transistor 7, the same amount of current as IElO flows out or flows from the collector side output terminal C of the transistor 7. Here, the DC loop gain FO of the N°C circuit is: μ: detection sensitivity (μA/μSec)
β: Expressed as oscillation frequency control sensitivity (Hz/μA).

In addition, the detection sensitivity μ is, however, TD: width of horizontal synchronization signal TH: horizontal period The detection sensitivity P is proportional to IPeak.

The oscillation frequency detection sensitivity β is a characteristic specific to a VCO, and an example thereof is shown in FIG. Further, Ipeak is the same as HIO, and an example of the IElO characteristics according to the configuration shown in FIG. 2 is shown in FIG. Further, FIG. 5 shows an example of the characteristics of the detection sensitivity μ obtained from the IElO shown in FIG. 4. Further, FIG. 5 shows the DC loop gain F obtained by multiplying the oscillation frequency wave number control sensitivity β obtained from FIG. 3 by the detection sensitivity μ shown in FIG. was shown at the same time. As can be seen from FIG. 5, in the conventional layered circuit, at a voltage lower than the power supply voltage of around 6V, DC. It can be seen that the loop gain FO2 value decreases rapidly.

For example, power supply voltage ■. . DC loop gain F when is 5V. When compared with FO when the power supply voltage ①Cc is 3V, the latter is reduced to about 1/2.5 of the former. In this way, when a conventional phase detection circuit is operated at a low voltage, M°C
There was a drawback that the DC loop gain Fc of the circuit decreased. It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art, and to reduce the N°C
It is an object of the present invention to provide a phase detection circuit in which a decrease in DC loop gain FO of the circuit due to low voltage is reduced.

In order to achieve the above object, the present invention provides a circuit in which the current of a constant current circuit decreases logarithmically while β increases hyperbolically due to voltage reduction, and β and μ increase particularly at low voltage. Characteristics cancel each other out, resulting in F for changes in power supply voltage.
.

The feature is that the change in is minimized. Embodiments of the present invention will be described below based on the drawings.

FIG. 6 shows an embodiment of the present invention. The only difference from the prior art circuit example shown in FIG. 2 is the constant current circuit 26, which is indicated by a broken line. The emitter current 1E10 of transistor 10 in this circuit is) where VBE23
: Base-emitter voltage of transistor 23 IE23: Emitter of transistor 23
Current K: Boltzmann constant T: Absolute temperature q: Determined by solving for electron charge.

The thus determined Hl of the constant current circuit 26 of the phase detection circuit. An example of the characteristics is shown in FIG. In addition, the above (1)
) is obtained from the following equation.

However, ■B23: Base voltage of transistor 23
Voltage Rl7: Resistance value of resistor 17 VBEIO: Base of transistor 10
Emitter voltage.

, IC23: each transistor 10,
Collector current of 23: Collector junction reverse saturation current Therefore, if the detection sensitivity μ is calculated from the value of HlO in FIG. 7, it will be as shown in FIG.

This detection sensitivity μ and the oscillation frequency control sensitivity β shown in Figure 3
The DC loop gain Fc is determined by the product of , and this Fc is illustrated as shown in FIG. As is clear from FIG. 8, the DC loop gain F. The low voltage characteristics of , especially when the power supply voltage is low. . Is it 6V-? The power supply voltage is almost flat between V and V. There is almost no change in FO with respect to a change in c. As described above, according to the present invention, the constant current amount of the constant current circuit in the phase detection circuit is configured to change logarithmically as shown in FIG. 7 due to voltage reduction. DC loop gain F in low voltage operating range.

It is possible to configure an AFC circuit with little change in the amount of change.

[Brief explanation of the drawing]

Fig. 1 is a loop block diagram of the horizontal layer °C circuit of a television receiver, Fig. 2 is a circuit diagram of a phase detection circuit in the prior art, and Fig. 3 is the voltage reduction characteristic of the oscillation frequency control sensitivity β of the VCO. FIG. 4 shows the transistor 10 in FIG.
Figure 5 shows the voltage reduction characteristics of the emitter current of the detection sensitivity P.
FIG. 6 is a circuit diagram of a phase detection circuit which is an embodiment of the present invention, and FIG. FIG. 8 is a voltage reduction characteristic diagram of the emitter current of the transistor 10 of the phase detection circuit according to the present invention; FIG. 8 is a voltage decrease characteristic diagram of the detection sensitivity μ according to the present invention; and FIG.
DO loop gain F of C circuit.

Claims (1)

[Claims] 1. A first transistor whose collector is connected to the common emitter of the differential pair transistors constituting the switch circuit, and whose emitter is connected to a current adjustment resistor, whose base is connected to the base of the first transistor, A second transistor of the constant current bias circuit whose base and collector are short-circuited, and a reference signal source connected via a resistor from the base-collector connection point of the second transistor, A phase detection circuit characterized in that an emitter current changes logarithmically with respect to changes in power supply voltage.