JPS6046187A - Burst gate pulse generating circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of an AGC detecting circuit or the like by setting a level higher than the level, which falls a burst gate pusle, during an input synchronizing signal to cut off a means which rises the pulse. CONSTITUTION:An input terminal IN is connected to the base of a transistor (TR)Q1 through a resistance R13 and is connected to the base of a TRQ16. The collector of the TR Q16 is connected to a power source VCC, and the emitter is connected to emitters of TRs Q9 and Q10. A base potential VX of the TRQ16 at the time, when the synchronizing signal supplied to the input terminal IN is in the high level, is so set that V2<VX is true when the potential of a constant voltage source is denoted as V2. Consequently, when the input synchronizing signal is in the high level, the TR Q10 is cut off, and the burst gate pulse is not generated. That is, the burst gate pulse is not outputted during the vertical synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a circuit for generating a pulse for extracting a burst signal.

[Technical background of the invention and its problems]

Generally, BG (burst signal detection) signal generation circuits are used in television receivers and VTRs (video tape recorders).

The BG pulse obtained by the BG pulse generation circuit is used as a Gutnoculus for burst signal detection in a color synchronization circuit, and is used as a key pulse for AGC detection in an AGC (automatic gain control) circuit. In particular, in an AGC circuit, the sync signal amplitude must be kept constant by extracting the potential of the pedestal portion of the video signal, where the tip of the sync signal is flanged, using a BG pulse, and comparing that potential with a reference potential. It controls the gain of the AGC circuit.

In this way, the 13Q)4 pulse generation circuit is used as a circuit for creating reference signals for ACC (automatic color signal control) detection and AGC detection in television receivers and VTRs, and is used to control the pulse width of BG pulses and 9. This is a circuit where the position of the loops is very important.

FIG. 1 shows a conventional BQ z4 pulse generation circuit.

The input terminal IN to which the synchronous separation output signal is supplied is grounded via a resistor R1, and is connected to an NPN transor transistor Q1.
Connected to the pace of. The emitter of this transistor Q1 is grounded, and the collector is connected to the power supply V via a constant current source I.
It is also connected to the pace of the NPN type transoster Q2. The emitter of this transistor Q2 is grounded, and the collector is connected to the power supply V through a resistor R2. . It is also connected to ground via a capacitor C1, and to the pace of an NPN type transistor Q3. The collector of this transistor Q3 is connected to the power supply V via a resistor R3, and the emitter is grounded via a resistor R6. connected to the emitter. The pace of this transistor Q4 is grounded via a resistor R7, and is also connected to the collector of the transistor Q3 via a resistor R5. Also,
The collector of transistor Q4 is a PNP type transistor Q
5 collector and pace. The emitter of this transistor Q5 is connected to the power supply vco via a resistor R4. Furthermore, the pace of transistor Q5 is PNP
Connected to the pace of type transostor Q6. The emitter of this transistor Q6 is connected to the power supply V through a resistor R8. 0, and its collector is grounded via a resistor R9 and connected to the pace of an NPN transistor Q8.

The emitter of this transistor Q8 is grounded, and the collector is connected to the collector of the transistor Q1 and to the pace of the NPN transistor Q7. The emitter of this transistor Q7 is grounded, and the collector is connected to the pace of the transistor Q4.

On the other hand, the collector of the transistor Q2 is connected to the pace of the KidNPN type transistor Q9.

The collector of this transistor Q9 is connected to the power supply V, and the emitter is connected to the emitter of an NPN transistor Q1a, which together with this transistor Q9 constitutes the second differential amplifier A2, and is grounded via a constant current source 2. Ru. The pace of the transistor Q10 is grounded via a constant voltage source v2, and the collector is connected to the collector and pace of a PNP transistor Qll. The emitter of this transistor Qrt is connected to the power supply (2) via a resistor Rsok. Furthermore, the pace of this transistor Qll is connected to the pace of a PNP transistor Q12. This transistor Q12 is connected to the power supply Vcc via a resistor R11, and its collector is a third differential amplifier A, which constitutes a transistor QCs.
p Connected to the emitter of Q14.

Among these, the pace of the transistor Q1g is connected to the pace of the transistor Q9, and the collector is grounded.

Further, the base of the transistor Q14 is grounded via the constant voltage source Vlk, and the collector is connected to the NPN transistor Qss.
is connected to the collector and output terminal OUT of
It is grounded via a resistor R111. The transistor Q
1B emitter 15- The ivy is grounded and the pace is the transistor. 8 collector.

The operation of the above configuration will be explained using FIG. 3.

When a synchronization separation output signal as shown in FIG. 3(4) is input to the input terminal IN, the transistor Q1 is cut off when the synchronization signal is at a low level. Therefore, transistor Q2 # Q7 + Qso IQll・Q12・
(Q13 and Q15 are turned on) and the other transistors Qa, Q4, lQ5, and Q6.

Qs lQ9 eQs4 is cut off. At this time, the collector of the transistor Q+5 connected to the output terminal OUT becomes a low level.

Further, when the synchronization signal is at a high level, the transistor Q1 is turned on. Therefore, transistor Q2 eQ
r lQ15 is cut off.

At this time, the base potential of transistor Q4 is vccx (
Rs + R5)/(Rs + R5 + R7), the pace of transistor Q3 is charged by time constant R2C1. At this time, transistor Q3 is cut off and transistor Q4 is on. As a result, transistors Qs, Qs
=Qs turns on, transistor Q2 +Qy eQl
Continue to cut off s. This is the part a shown in Figure 3 (A).Next, in the part b of the same figure (~), transistors Q4 +Qs +Qs and Q8 continue to turn on, and transistors Q2 #Q7 #Q15 continue to be cut off. .At this time, the transistor QIOIQI□.

Q13 is on. When the pace potential of the transistor Q3 becomes vl, the transistor Q14 is turned on and BG/Grus shown in FIG. 30) rises. This is part C shown in the figure. Furthermore, transistor Q3
When the pace potential of transistor Q1o + becomes v2,
Qtte Q12 is cut off and transistor Q9 is turned on. At this time, the BG pulse falls as shown by d in Figure 3 (0).Furthermore, the transistor Q3
When the pace of the transistor Q4 becomes equal to the pace potential of the transistor Q4, Schmitt is activated, the transistor Q3 is turned on, and the transistor Q4 t Qs r Qs+Q8 is cut off. At this time, since the transistor Q1 is cut off, the transistor Qz eQy eQ
ls turns on. This is part e shown in FIG. 3(B), and returns to the original state. The waveform shown in FIG. 3(B) is the pace waveform of transistor Q15, fi, BG-
It acts as a dart for f.Russ. Also, the same figure (C)
is the waveform of the pace of transistor Q3, and ) in the figure is the waveform of the BQ pulse output terminal OUT. This is an operation during the horizontal synchronizing signal period and the equalization pulse period, and in the vertical synchronizing signal period, Schmitt is inverted at the part e' shown in Figure 3 (0), but since the synchronizing signal is at a high level, , transistor Q 2 m Q 7 *Q xsil: does not turn on, and the pace potential of transistor Q3 continues to charge.

Then, when the synchronization signal becomes low level (Fig. 3 (A)
) returns to its original state.

Made in this way] l Q no 4 Rus (Figure 3 (
(c) is also created during the equalization pulse period and the vertical synchronization signal period. When the B Q /4' pulse in such a state is input to the AGC detection circuit, the horizontal synchronizing signal period and the equivalent pulse period detect the (destal part) of the video signal, and the vertical synchronizing signal period detects the leading edge of the synchronizing signal. Resulting in.

At this time, the potentials of the pedestal portion and the tip of the synchronization signal are different.

By comparing this with a fixed reference potential, the detection output is detected, and in the AGC detection circuit, even if the signal is normal, the detection output is different between the vertical synchronization signal period and other periods, causing the AGC circuit to malfunction. There is a drawback.

Furthermore, in the ACC or APC detection circuit, the vertical synchronization signal period in which there is no burst signal is also darted with BG pulses and detected as 〇〇. During this period, there is no need for Ace detection, and by performing ACC detection, the 4-wavelength waveform is detected as an ACC detection output, which has the disadvantage of causing the AGC circuit to malfunction. In particular, in VTRs, the vertical synchronizing signal period is the head switching period, and the SN
(signal-to-noise) period. On the other hand, 9-ACC detection has the disadvantage of further worsening the SN.

Furthermore, if such a G pulse generation circuit is implemented within an IC (integrated circuit), there is a possibility that the BGi4 pulse rising edge may enter the synchronization signal period due to characteristic errors of the resistors and transistors within the IC. There is also a drawback that the AGC detection circuit and the ACC detection circuit malfunction.

[Purpose of the invention]

This invention was made based on the above circumstances, and its purpose is to prevent the malfunction of the AGC detection circuit, ACC detection circuit, etc., and to prevent the malfunction of the above circuit even when integrated into an IC. [Summary of the Invention] This invention aims to provide a burst gate pulse generation circuit capable of synchronously separating a BG pulse generated by triggering the leading edge of a synchronously separating output signal. By masking with the output signal, the BG pulse 10- is not output during the vertical synchronizing signal period and the synchronizing signal period.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and only the different parts will be explained.

In FIG. 2, the input terminal IN is connected to the pace of the transistor Q1 via the resistor R13, and is also connected to the pace of the NPN transistor Q16. The collector of this transistor Q16 is connected to the power supply V2, and the emitter is connected to the emitter of the transistor CQesQto.

In the above configuration, when the synchronization signal supplied to the input terminal IN is at a high level, the pace potential V of the transistor Q1g satisfies V2<Vx.

It is set so that Therefore, when the input synchronization signal is at a high level, transistor Ql.

is cut off and no BG pulse is generated.

Tsumashi, Figure 3 (as sometimes shown, the period of the vertical synchronization signal is 4
3 G) 4 pulses are not output. Also, when this circuit is made with an IC, the position of the BG pulse changes,
Even if the BG/f pulse enters the leading edge of the synchronizing signal, it is possible to prevent the BG/f pulse from being output only to the leading edge of the synchronizing signal.

According to the above embodiment, by masking the BGi4 pulse generated by triangulating the leading edge of the synchronization separation output signal with the synchronization separation output signal, the BGt4 pulse is prevented from being output during the vertical synchronization signal period. I have to. Therefore, the AGC detection circuit does not detect the tip of the synchronization signal during the vertical synchronization signal period, and can only detect the pedestal portion of the video signal outside the vertical synchronization signal period, so the AGC circuit operates stably. It is possible to do so.

Further, in the ACC detection circuit, detection is not performed during a vertical synchronization signal period in which there is no burst signal. Therefore, noise components are no longer detected as the ACC detection output, and deterioration of SN can be prevented.

Furthermore, the circuit shown in Figure 2 is created using an IC, and even if the rising edge of the BG pulse fluctuates due to characteristic errors in transistors and resistors, there is no possibility that a 13 Q pulse will enter within the synchronizing signal period. do not have. Therefore, there is no possibility that the 〇〇 detection circuit and the ACC detection circuit will malfunction.

〔Effect of the invention〕

As described in detail above, according to the present invention, the burst gate does not cause the AGC detection circuit, ACC detection circuit, etc. to malfunction, and can prevent malfunctions of the above circuits even when integrated circuits are implemented. A pulse generation circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional burst dart pulse generation circuit, FIG. 2 is a circuit diagram showing an embodiment of a burst dart pulse generation circuit according to the present invention, and FIG. FIG. 3 is a waveform diagram shown for detailed explanation of the invention. Al e A2 # A3... 1st. Second. Third differential -13- Amplifier &amp;Applicant's agent Patent attorney Takehiko Suzue-14~

Claims (1)

[Claims] circuit means for triggering a front edge of an input synchronization signal and generating a voltage increasing at a predetermined time constant from the leading edge of the synchronization signal; circuit means for raising a pulse at a low level of the generated voltage; In a burst gate pulse generation circuit comprising circuit means for causing the pulse to fall at a higher level among the generated voltages to generate a burst pulse of a predetermined width, 1. A burst gate pulse generation circuit comprising a circuit for cutting off circuit means for raising the pulse by setting the pulse to a high state.