JPS6046182A - Two-dimensional visual device - Google Patents

Abstract

PURPOSE:To reduce the number of bits of a counter and to improve a picture processing speed by generating Y coordinate and X coordinate from the first counter and the second counter respectively. CONSTITUTION:A luminance signal outputted from a video camera 11 is led to an edge signal generating circuit 12, and the first counter 16 counts a blanking signal BLK including no equivalent pulses of the video camera 11 to generate Y coodinate after being reset by a vertical synchronizing signal VP, and the second counter 15 counts a subcarrier signal SC1 of the video camera 11 to generate X coordinate after being reset by the blanking signal BLK. Thus, numbers of bits of counters 15 and 16 are reduced by about 17% and about 7% for X coordinate and Y coordinate respectively. Therefore, quantities of data to be stored in the first and the second RAMs 20 and 21 are reduced, and capacities of RAMs 20 and 21 are reduced. Consequently, the number of data in RAMs 20 and 21 which are read into a microcomputer is reduced, and the processing time is shortened.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a two-dimensional visual device that extracts the features of a two-dimensional image captured by a video camera, and is particularly suitable for low-cost robots and the like. Regarding.

[Background of the invention]

Conventionally, devices are known that recognize the image of a subject captured by a video camera, etc., and determine the positional deviation, dimension, area, angle, and shape. .

A conventional device of this type will be explained with reference to FIG.

In the figure, 1 is a video camera, and a luminance signal output from the video camera 1 is sent to an edge signal generation circuit 2. The edge signal generation circuit 2 differentiates the luminance signal, and the differentiated output is converted into a binary digital signal by the waveform shaping circuit B. As a result, the outline of the subject is extracted as an edge signal.

On the other hand, the horizontal synchronization signal output from video camera 1)
I-SYNC is input to the X coordinate generation counter 4 and counted by the counter 4. Note that this counter 4 is reset by the vertical synchronization signal -Qv-8YNC output from the video camera 1.

Further, the X coordinate generation counter 5 counts the clock signal generated by the video camera 1 or its frequency-divided signal. Then, the counter 5 of the horizontal synchronizing signal 1 (-8
Reset by YNC.

A binary digital signal representing the contour of the subject which is the output of the waveform shaping circuit 3, the output of the X coordinate generation counter 4, and the output of the X coordinate generation counter 5 are processed by a microcomputer (hereinafter abbreviated as microcomputer). The signal is input to the control circuit 6 consisting of the following components. The control circuit 6 has the above-mentioned 2
A digital signal of a value is assigned and stored in a memory bank 7 such as a RAM.

Thereafter, the data in the memory bank 7 is processed by the microcomputer 6, etc., and the above-mentioned positional deviation is detected.

Measurements such as dimension 1 area, angle, etc., and discrimination of 1 type of shape, etc. are performed.

In the above-mentioned conventional cylinder manufacturing method, the X, X coordinates are generated using the vertical synchronization signal and horizontal synchronization signal of the video camera, and the clock signal of the basic oscillator or a signal obtained by dividing these signals. , these synchronization signals and clock signals are constantly output, whereas the luminance signal has a retrace period, during which it is below the black level and at a constant level. Moreover, the timing of generation of the synchronization signal is in the middle of this retrace period. For this reason, the x,

In this case, 17% of the X coordinates and 7% of the X coordinates are invalid addresses.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a two-dimensional visual device that eliminates the drawbacks of the prior art described above, reduces the number of bits of a counter, and improves image processing speed.

[Summary of the invention]

In order to achieve the above object, the present invention guides a luminance signal output from a video camera to an edge signal generation circuit,
After the first counter is reset by the vertical synchronization signal,
The X coordinate is generated by counting the blanking signal that does not include the equivalent pulse of the video camera, and after being reset by the blanking signal, the second counter receives the clock signal of the basic oscillator of the video camera, or divides this. The X coordinate is generated by counting the signals generated by the edge signal, and at least one of the X, It is characterized by the fact that it is

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a time chart of the luminance signal Y, vertical synchronization signal vP, horizontal synchronization signal HP, and blanking signal BLK which are output from the video camera. However, the time axis has been changed for convenience of explanation.

In the case of NTSC system, the vertical synchronization signal vP is 16.7 m
The horizontal synchronizing signal HP is a pulse generated every 63.5 μs. The blanking signal BLK, which does not include an equivalent pulse, is a nine-wide signal that is at a low level when both signals are generated.

As shown, the vertical synchronization signal vP and the horizontal synchronization signal HP are located between the blanking signal BLK. Further, the brightness signal Y is generated when the blanking signal BLK is at a high level.

FIG. 3 is a block diagram showing an embodiment of the two-dimensional visual device of the present invention. The camera 11 sends the brightness signal Y' to the edge signal generation circuit 12, and also sends the subcarrier signal S C1 (3,
58Mllz square wave), vertical synchronization signal VP, blanking signal BLK, and even field signal FB to gate 14. The even field signal FB is also sent to the microcomputer 23.

The edge signal generation circuit 12 differentiates the luminance signal Y, shapes the waveform, and converts it into a binary digital signal.

Then, it is output as an edge signal indicating the outline of the subject. This edge signal is sent to the clock input of the edge counter 13 and the data input of the second RAM 21.

On the other hand, when the even field signal FB is low, the gate 14 passes the signals SC1, VP, l3LK'&, and when it is high, (the signal No. 8 SC1 and BLK are set to low level,
Also, the vertical synchronizing signal ■P is held at the full height level and output.

As a result, the X counter 15. X counter 16
The edge counter 16 operates only during even fields and is reset during odd fields.

The subcarrier signal SC1 that has passed through the gate 14 enters the clock input section of the X counter 15, and becomes the blanking signal BLK.
enters the clear input of the X counter 15 and the clock input of the X counter 16. Similarly, the vertical synchronizing signal P enters the clear inputs of the X counter 16 and the edge counter 13.

The X counter 15 is cleared when the blanking signal BLK is at a low level, and is cleared when the blanking signal BLK is at a high level.
Count the rising part of 1. The X counter 16 is cleared when the vertical synchronization signal vP is at a high level, and counts the rising edge of the blanking signal BLK when the vertical synchronization signal vP is at a low level.
After being cleared by , the subcarrier signal SC1 is counted and an X-coordinate address obtained by dividing one horizontal scanning period by 3.58 MHz is generated. On the other hand, the X counter 16 counts nine rising edges of the blanking signal BLK after being cleared by the vertical synchronizing signal vP, and generates a Y coordinate address.

The outputs of X counter 5 and X counter 6 are gate 1
7 to the data input/output section of the first RAM 20 and one input section of the second data selector 19.

The gate 17 is controlled by the microcomputer 23, and allows the input signal to pass when the signal a from the microcomputer 23 is low level, and makes the output part high impedance when the signal a is high level. Address data b is sent from the microcomputer 23 to the input section of one of the second data selector 19 and the first data selector 18. The output signal C of the edge counter 3 for counting edge signals is supplied to the other input section of the first data selector 18).

Note that the edge counter 3 is cleared when the vertical synchronization signal vP output from the gate 14 is at a high level.

Like the gate 17, the first and second data selectors 18 and 19 are controlled by the signal d8' from the microcomputer 23. When this signal is at a low level, the first data selector 18 selects the output of the edge counter 13, and the second data selector 19 selects the output of the gate 17, and when this signal is at a high level, it selects the address data from the microcomputer 23. Select b.

The signal selected in this way is transmitted to the first RAM M2O
and is supplied to the address input section of the second RAM 21. The output e of the second RAM 21 is supplied to the input section of the microcomputer 23, and the input/output section of the first RAM 20 is similarly connected to the input/output section of the microcomputer 23.

The timing generation circuit 22 generates a write enable signal and an output enable signal based on the subcarrier signal SC1 outputted from the gate 14 and the signal from the microcomputer 23, and supplies them to the first RAM 20 and the second RAM 21. If there is no signal from the microcomputer 23, a write enable signal is output from the subcarrier signal SC1, and if there is a signal, this signal is used to output a write enable signal or an output enable signal. Note that 24 is an input/output circuit connected to the microcomputer 23, and is used for inputting teaching data.

Next, the operation of the above embodiment will be explained.

The output signals SC1, VP, and BLK from the camera 11 pass through the gate 14 when the signal FB from the camera 11 is also at a low level, that is, when it is an even field. The X counter 15 is a counter for the X coordinate, and after being cleared by the blanking signals B T and K, the subcarrier signal S
Count c1. Therefore, the X counter 15 is 1
Generates the address of the X coordinate by dividing the horizontal scan by 3.58MH2〇On the other hand, the X counter 16 is a counter for the X coordinate,
The blanking signal BLK'e is counted after being cleared by the vertical synchronizing signal P.

That is, the number of horizontal scans in an even field of one vertical scan is counted, and the address of the X coordinate is generated.

A signal indicating the address of this image is supplied to the gate 17, and is supplied to the data input/output section of the first RAM 20, and is also sent to the second RA via the second data selector 19.
It is supplied to the address input section of M21.

On the other hand, the luminance signal Y, which is another output of the camera, is differentiated and waveform-shaped by the edge signal generation circuit 12.
It is considered to be a digital signal of value.

That is, the edge signal generation circuit 12 outputs an edge signal representing the outline of the subject. This edge signal is counted by the edge counter 13, and the count value is the first
The data is supplied to the address input section of the first RAM 20 through 18 data selectors. Also, the edge signal is directly connected to the second
is supplied to the data input section of RAM2i.

In this state, the timing generation circuit 22
A write enable signal is generated based on the subcarrier signal SC1, which is the output of the first T(, A
M20 and second RAM21. As a result,
The second RAM 21 stores the presence or absence of an edge signal for each X and Y1 coordinate, one bit at a time. Further, the first RAM 20 stores the X coordinate and the X coordinate of the second RAM 21 when the edge signal is generated, and serves as an index.

As mentioned above, the edge counter 1 is stored in the first RAM 20.
The X coordinate and the X coordinate are stored using the count value of 3 as an address. On the other hand, the second RAM 21 stores the X coordinate and the presence or absence of an edge signal using the X coordinate as an address.

Therefore, by operating the microcomputer 23 using the data stored in the first and second RAM M2O and 21, the object captured by the camera is recognized,
It is possible to measure positional deviations and determine shapes. .

〔Effect of the invention〕

According to the present invention, the first counter generates the X coordinate by counting blanking signals that do not include equivalent pulses after being reset by the vertical synchronization signal, and the second counter is reset by the blanking signal. Since the X coordinate is generated by counting the video camera's subcarrier signal 12 later, the number of bits in the counter can be reduced by 17% for the X coordinate and by 7 bits for the X coordinate. Therefore, the amount of data to be stored in the first and second RAMs is reduced, and the capacity of the RAMs can also be reduced.

Therefore, the amount of data read by the microcomputer from the RAM is reduced, resulting in faster processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional two-dimensional visual device; FIG. 2 is a time chart of a video camera's brightness signal, vertical and horizontal synchronization signals, and blanking signals; and FIG. 3 is an implementation of the two-dimensional visual device of the present invention. FIG. 2 is a block diagram illustrating an example. 11...Camera 12...Edge signal generation circuit 1
3... Edge counter 15... X coordinate counter 16... X coordinate counter 20, 21... 1st.
Second RAM 23...Akio Takahashi, patent attorney representing microcomputer

Claims (2)

[Claims] (1) A video camera, an edge signal generation circuit that differentiates the light intensity signal output from the video camera and converts it into a binary digital signal, which is reset by the vertical synchronization signal output from the video camera and contains equivalent pulses. a first counter that generates the X coordinate by counting blanking signal outputs that are not present; a first counter that is reset by the blanking signal output and counts the clock signal of the basic oscillator of the video camera or a signal obtained by dividing the clock signal of the basic oscillator of the video camera and generates the X coordinate; a second counter that generates a second counter, and the X coordinate and the X coordinate corresponding to the time when the output signal of the edge signal generation circuit is output;
A two-dimensional visual device characterized by comprising a memory puncture for storing at least one of the X coordinate and the output signal of the edge signal generation circuit corresponding to the X coordinate. (2) The two-dimensional visual device according to claim 1, wherein the first and second counters are operated only during either an even field or an odd field.