JPS6045514B2 - digital analog memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital analog memory that operates digitally and holds analog voltage values.

Automatic gain control to compensate for level fluctuations in the transmitted signal (
As a type of AGC) circuit, the P (pilot)-AGC method, in which M° C. is performed on the receiving side using the level of a pilot signal inserted into the band of a transmission signal as an index, is already widely used.

In such a P-AGC system, if the pilot signal disappears or its level drops for some reason, the M°C operation is performed using the level of the pilot signal as an indicator, so there is no possibility that the transmitted signal is at a normal level. Nevertheless, a malfunction occurs in which the gain abnormally increases. Conventionally, in order to prevent such malfunctions of the M°C circuit, the level of the pilot signal was held as the charging voltage of the capacitor of the CR time constant circuit, and abnormalities in the pilot signal were detected by means for determining the level of the pilot signal. At this time, a method is used in which M°C operation is continued by maintaining the pilot signal level.

However, in order to realize such an analog memory function, extremely high insulation resistance is required for the holding capacitor and high resistance of the CR time constant circuit, and the packaging container for these, which requires a large device. It was not economical as it led to

On the other hand, the present applicant has already applied for patent application No. 54-080767.
In JP-A No. 56-006516, an automatic gain control circuit equipped with a digital memory circuit, which digitizes the pilot signal level and holds it in the form of a digital signal, replaces such an analog memory function. is proposed.

Although this eliminates the disadvantages of analog memory functions mentioned above, this conventional digital memory circuit
Since the clock is out of synchronization with the up/down signals, there is a risk of malfunction. FIG. 1 is a block diagram showing the configuration of a conventional digital memory circuit.

In the figure, 1 is a comparator, 2 is a digital-to-analog (D/A) converter, 3 is an up/down counter, and 4 is a clock signal source. Also Vin and Vou
t are the input and output voltages of the circuit, respectively.
In FIG. 1, an input voltage Vin is applied to one input of a comparator 1 and compared with an output voltage VOut output from a D/A converter 2. In FIG. Comparator 1 digitizes the comparison result so that the input voltage Vin becomes the output voltage V.
When it exceeds Out, outputs 66r5, otherwise outputs ゜60゛ and increases up/down counter 3●
Add to down input. Up●down counter 3 has
A clock signal from a clock signal source 4 is applied to its clock input, and ゜“1” at the up and down inputs.
゛ or 4'0'', the count value is counted up or down for each clock signal.The count value of up◆down counter 3 is counted up or down by D/A converter 2.
, and is D/A converted to produce an output voltage VOut. In this way, the output voltage VOut of the digital memory circuit of FIG.
Follow in.

As is clear from the above-mentioned operating principle, changes in the output voltage VOut in the digital memory circuit of FIG. 1 occur stepwise with the period of the clock signal. The output voltage VOut thus generated is used as an AGC control voltage to control the amplifier. In case of pilot signal failure, up
Output a constant voltage according to the count value of the down counter, thereby continuing AGC operation. I can do it. However, in the digital memory circuit shown in Figure 1, when the up/down signals and the clock signal are not synchronized, erroneous up/down signals are generated and the counter malfunctions, resulting in fluctuations in the output voltage. It can become large.

In this way, when the output voltage of the digital memory circuit is accompanied by large fluctuations, the operation of the AGC circuit becomes unstable, which is undesirable. The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to sample the output state of a comparator that compares input and output voltages at a fixed time determined by a clock signal. An object of the present invention is to provide a digital memory circuit that does not malfunction by synchronizing with a clock signal.

To achieve this objective, the digital analog memory of the present invention includes a comparator that compares an input voltage and an output voltage and digitizes and outputs the comparison result;
a D-type flip-flop that reads and holds the output state of the comparator immediately before the rising edge of the clock signal; a frequency divider that divides the clock signal by two and outputs the divided signal; An up/down counter that counts up or down the count value according to the output state of the D-type flip-flop, and a digital that converts the count value of the up/down counter into digital-to-analog conversion to generate the output voltage. - an analog converter. Examples will be described below.

FIG. 2 is a block diagram showing the configuration of one embodiment of the digital analog memory of the present invention, and the same components as in FIG. 1 are designated by the same numbers.

5 and 6 are D-type flip-flops.

In FIG. 2, the comparator 1 compares the input voltage Vin and the output voltage VOut, and outputs ゜゜1゛ or ``0'' as in the case of FIG. 1.

The output of comparator 1 is applied to the D input of D-type flip-flop 5. D type flip-flop has trigger input T
When a clock signal is applied to the clock signal, the logic state of the D input terminal immediately before the rising edge of the clock signal is read to determine the logic state. Therefore, the D-type flip-flop 5 holds the output state of the comparator 1 immediately before the rise of the clock signal of the clock signal source 4 at its Q output and outputs it. A change in the state of the Q output of the D-type flip-flop 5 occurs every time the clock signal rises. Therefore, the period of the Q output is twice the period of the clock signal. The Q output of the D-type flip-flop 5 is given to the up/down counter 3 as an up/down signal. On the other hand, the clock signal from the clock signal source 4 is also applied to the trigger input T of the D-type flip-flop 6.

The D-type flip-flop 6 has its O output applied to its D input, thereby dividing the clock signal by two and outputting the divided clock signal to its Q terminal. The Q output of a D-type flip-flop is
It is added as a clock signal to the clock input of the up/down counter 3. The up●down counter 3 responds to “1゛or゜0゛” in the up●down input.
Counts up the count value for each clock input,
Or count down.

The count value of the up/down counter 3 is applied to the D/A converter 2, where it is D/A converted to produce an output voltage VOut. In this way, the digital analog memory shown in FIG.
produces t. In this case, sampling of the error signal in the comparator 1 is performed on the comparator output immediately before the rising edge of the clock signal of the clock source 4, and the previous sampling value is held at other times.
Since erroneous up/down signals that are not synchronized with the clock signal are not generated, the up/down counter 3 does not malfunction, and instability in the output of the D/A converter 2 is therefore eliminated. As explained above, according to the digital analog memory of the present invention, the clock signal and the up/down signals are synchronized, and the up/down counter will not malfunction, so its output voltage will not become unstable. do not have.

Therefore, when used in an AGC circuit or the like, it is extremely effective because its operation can be stabilized. Note that the digital analog memory of the present invention is not limited to N°C circuits.
It goes without saying that it can be used generally when it is necessary to store and hold analog voltage values.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional digital memory circuit, and FIG. 2 is a block diagram showing the configuration of an embodiment of the digital analog memory of the present invention. 1...Comparator, 2...Digital-
Analog (D/A) converter, 3... Up/down counter, 4... Clock signal source, 5, 6
...D type flip-flop.

Claims (1)

[Claims] 1 A comparator that compares the input voltage and output voltage and digitizes the comparison result and outputs it, a D-type flip-flop that reads and holds the output state of the comparator immediately before the rise of the clock signal, and 2 a frequency divider that divides and outputs the frequency; an up/down counter that uses the output signal of the frequency divider as a clock to count up or down according to the output state of the D-type flip-flop; - A digital-analog memory characterized by comprising a digital-to-analog converter that performs digital-to-analog conversion of the count value of a down counter to generate the output voltage.