JPS6045507B2 - associative memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory, and more particularly, it uses a variable resistance element whose resistance value changes irreversibly depending on applied voltage or current, or both, and a field effect transistor, and has a simple circuit configuration and low consumption. The invention relates to an associative memory that uses low power and stores information that is nonvolatile.

An associative memory compares input data with information stored in the associative memory and detects whether the two pieces of information match or do not match.

Figure 1 shows the conventional circuit configuration of this type of memory, where Q and ~Q are transistors that make up a flip-flop that stores information, and Q7 ~ QIO are transistors that form the information stored in the flip-flop and the input. Transistors used for verification with data, D0~Dn-7 are input data lines, D0~
Dn-1 is an inverted input data line, W0 to Wm- are write lines, and Mo-Mm- is a verification output line. In FIG. 1, when the information "0" (transistor Q1 is on and transistor Q2 is off) is stored in the flip-flop, the input data is "0" (input data line D).

is low potential, inverted input data line D. is at a high potential), transistors Q and QH are non-conductive, so no current bus is formed between the verification output line and the ground, and therefore the verification output line Mo is in an open state. It is possible to detect that the input data and the information stored in the flip-flop match. On the other hand, if the input data is "1" (the input data line D is at a high potential and the inverted input car data line D is at a low potential), the transistors Q and Q are conductive, so a verification output is generated. A current bus is formed between the line Mo and the ground, so the verification output line Mo is grounded, and it is possible to detect a mismatch between the input data and the information stored in the flip-flop. The disadvantages of conventional associative memory, as shown in the figure, are that the circuit configuration is complex and the number of elements is large, so it occupies a large area;
Consumption: Power consumption is large.

These drawbacks become very serious obstacles when increasing the capacity of the memory (that is, when increasing the number n of pairs of input data lines and inverted input data lines and the number m of matching output lines). Furthermore, when such a memory is configured and used on the same chip as other logic circuits or random access memory, etc., since the stored information is volatile, the information is written not at the time of product shipment, but after the device is mounted. This method has the disadvantage that it is inconvenient to use. In order to eliminate these drawbacks, the present invention collates stored information and input data using a semiconductor active element (variable resistance element and field effect transistor) whose resistance value changes irreversibly depending on applied voltage or current, or both. The illustrated embodiment will be described in detail below.

FIG. 2 shows one embodiment of the present invention, particularly showing a 1-bit circuit configuration.

In the figure, ,R, , ,R,2 are variable resistance elements, Qll
, Q12 are field effect transistors, Do and Do are input data lines and inverted input data lines, Mo is a node that is set to ground voltage when writing information and is separated from the ground voltage when reading information to serve as a verification output line, No is information is a node that is used as a write voltage when writing, and as a ground voltage when read. When the variable resistance element R, , R, 2 is applied with a voltage or current exceeding a critical value, or both, the resistance value changes irreversibly from an initial high resistance to a low resistance, or from an initial low resistance to a high resistance. It changes.

These R, , R, and O are variable resistances in which the resistance ratio between high resistance and low resistance is very large, and the current that flows in the case of high resistance is negligibly small compared to the current that flows in the case of low resistance. If you use an element and make a low resistance conductive,
High resistance can be considered a non-conducting state. That is,
Information ``1'' or ``o'' can be stored depending on whether variable resistance element R, R, or O has high resistance or low resistance. Regarding such variable resistance elements, for example, the 1930s General National Conference of the Institute of Electronics and Communication Engineers, Integrated Circuits Division, No. 35.
1. It is also explained in ``Polycrystalline silicon PROM''. First, a case of a variable resistance element whose resistance value changes from an initial high resistance to a low resistance will be described.

Now, the variable resistance element R, , has a low resistance and the variable resistance element R,
The case where 2 is high resistance is defined as information ``0''. Input data line D when writing information ``0''. to high voltage,
Inverted input data line D. The associative memo according to claim 3, characterized in that the variable resistance element R is set to a low voltage, and the voltage or current exceeds a critical value at which the variable resistance element R changes irreversibly from high resistance to low resistance. DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory, and more specifically, it uses a variable resistance element whose resistance value changes irreversibly depending on applied voltage or current, or both, and a field effect transistor, and has a simple circuit configuration and low consumption. The invention relates to an associative memory that uses low power and stores information that is nonvolatile.

An associative memory compares input data with information stored in the associative memory and detects whether the two pieces of information match or do not match.

Figure 1 shows the conventional circuit configuration of this type of memory, where Q1 to Q9 are transistors forming flip-flops that store information, and Q7 to Q1O are transistors that contain information stored in the flip-flops and input data. Transistors used for checking, DO~Dn-1 are input data lines, J5'
o-Fi. -1 is an inverted input data line, WO to W. -1 is a write line, and MO-Mm-1 is a verification output line. In FIG. 1, when the information 64 "1 (transistor Q1 is conductive and transistor Q2 is non-conductive)" is stored in the flip-flop, the input data is "0" (the input data line D is at a low potential, If the inverted input data line I5'o is in the state of potential), transistors Q7 and Qll are non-conducting, so no current bus is formed between the verification output line and ground, and therefore the verification output line M. is in an open state,
It is possible to detect that the input data and the information stored in the flip-flop match. On the other hand, if the input data is ゜゜1゛ (the input data line D is at a high potential and the inverted input data line 'DO is at a low potential), the transistors Q7 and Q8 are conductive, so that the verification output line M is turned on. A current bus is formed between M and ground, thus verifying output line M. is grounded, indicating that the input data and the information stored in the flip-flop do not match. can be detected. By the way, the disadvantages of conventional associative memory as shown in Figure 1 are that the circuit configuration is complex and the number of elements is large, which occupies a large area, and that current constantly flows through the flip-flops used to store information. , the power consumption is large.

These drawbacks become very serious obstacles when increasing the capacity of the memory (that is, when increasing the number n of pairs of input data lines and inverted input data lines and the number m of matching output lines). Furthermore, when such a memory is configured and used on the same chip as other logic circuits or random access memory, etc., since the stored information is volatile, the information is written not at the time of product shipment, but after the device is mounted. This method has the disadvantage that it is inconvenient to use. In order to eliminate these drawbacks, the present invention collates stored information and input data using a semiconductor active element (variable resistance element and field effect transistor) whose resistance value changes irreversibly depending on applied voltage or current, or both. The illustrated embodiment will be described in detail below.

FIG. 2 shows one embodiment of the present invention, particularly showing a 1-bit circuit configuration.

In the figure, , Rll, Rl2 are variable resistance elements, Qll
, Ql2 is a field effect transistor, DO is the input data line and the inverted input data line, MO is the ground voltage when writing information, and is separated from the ground voltage when reading information, making it a verification output line. NO is the information node. is a node that is used as a write voltage when writing, and as a ground voltage when read.
Variable resistance elements Rll and Rl2 are those whose resistance value changes irreversibly from an initial high resistance to a low resistance, or from an initial low resistance to a high resistance when a voltage or current or both exceeding a critical value is applied. be.

This Rll, Rl. By using a variable resistance element, the resistance ratio between high resistance and low resistance is very large, and the current flowing in the case of high resistance is negligible compared to the current flowing in the case of low resistance. If it is in a conductive state,
High resistance can be considered a non-conducting state. That is,
Information “゜1゛” or “゜゛0” can be stored depending on whether the variable resistance element Rll or Rl2 has a high resistance or a low resistance. Regarding such variable resistance elements, for example, the General National Conference of the Society of Electronics and Communication Engineers Integrated circuit division, NO.35lC
It is also explained in ゜Polycrystalline silicon PROM゛. In this section, we will first explain the case of a variable resistance element whose resistance value changes from an initial high resistance to a low resistance.

Now, variable resistance element Rll has a low resistance and variable resistance element Rll
When 2 is high resistance, it is defined as information “0゛.Information゜゜0”
When writing ゛, input data line D. to a high voltage, inverting the input data line T). is set to a low voltage, and the variable resistance element Rl
The voltage required to apply a voltage or current, or both, exceeding a critical value at which l changes irreversibly from high resistance to low resistance (
A node (hereinafter abbreviated as "write voltage") that is used as a write voltage when writing information and as a ground voltage when reading information (hereinafter referred to as "write voltage")
(referred to as the write/ground voltage line) is applied to NO. Furthermore, the pigeon is at ground voltage. At this time, since the field effect transistor Qll is conductive, a voltage or current, or both, exceeding a critical value is applied to the variable resistance element Rll, and the variable resistance element Rll irreversibly changes from high resistance to low resistance. . On the other hand, the field effect transistor Ql. is non-conducting, so
No voltage or current or both exceeding the critical value is applied to the variable resistance element Rl2, and Rl2 remains at a high resistance. When reading information, the write/ground voltage line NO is set to ground voltage, and NO is separated from the ground voltage and used as a verification output line.

When the information "0" is written as described above, if the input data is "0" (input data line D. is low voltage, inverted input data line 10. is high voltage), the variable resistance element Rll
and field effect transistor Ql2 are conductive, but variable resistance element Rl2 and field effect transistor Qe are non-conductive, so that verification output line MO and ground voltage line N are connected. No current bus is formed between them, so the verification output line is in an open state, and it can be detected that the input data and the written storage information match. On the other hand, if the input data is "1°" (input data line DO is high voltage, inverted input data line D is low voltage), variable resistance elements R, l and field effect transistor Qll are both conductive, so verification output A current bus is formed between the line pigeon and the ground voltage line N. Therefore, the verification output line MO is grounded, and it is possible to detect a mismatch between the input data and the written memory information.The above is as follows. This is a case where the information "゜0゛" is written, but also when the information "1" is written, the variable resistance element Rl has a high resistance and the variable resistance element Rl2 has a low resistance, so the input data is 1'', variable resistance element Rl2 and field effect transistor Qll are conductive, but variable resistance element Rll and field effect transistor Ql. is non-conductive, so matching of the input data and stored information can be detected with the verification output line MO in an open state.On the other hand, if the input data is "0", both the variable resistance element Rl2 and the field effect transistor Ql2 are conductive. Therefore, the verification output line M.

is grounded, and a mismatch between input data and stored information can be detected. Next, if variable resistance elements Rll and Rl2 irreversibly transition from an initial low resistance to a high resistance, variable resistance element Rll has a low resistance and Rl2 has a high resistance. In order to write, the inverted input data line HO is brought to a high voltage and the input data line D is set to a high voltage.

set to low voltage; line N. This is done by applying the necessary voltage to cause an irreversible change. That is,
Writing is performed using the input data ゜“0゛.Also, when reading information, if the information “0” is written as described above, if the input data is “゜0゛” and 1, the pigeon is If the MO is in an open state and a match can be detected and the input data is "1", the MO is in a grounded state and a match can be detected. Furthermore, when information ゜゜1゛ is written, ``゜0゛ and ゜゜1゛, variable resistance element Rll and variable resistance element Rl2, field effect transistor Qll and field effect transistor Ql2, input data line D and inverted input. The same explanation can be given by replacing the data lines . To make this switch, for example, a field effect transistor is provided between the verification output line and the ground, and this transistor is made conductive during writing and non-conductive during reading. In Fig. 3, the circuit shown in Fig. 2 is configured as a unit element in a matrix of m rows and n columns, and horizontal verification output lines M, (j = 0 to m-1) are commonly connected. , the vertical data input line D and the inverted data input line) I5i (1=0 to n-1) are connected in common, and the write/ground voltage lines N, in the content addressable memory of each unit element are connected in common. (j=0 to k-1) are all k (natural number)
This is a specific example of an associative memo 5 which is divided into groups and the lines within each group are commonly connected to expand the storage capacity as a whole.

In FIG. 3, when writing information, M, is set to the ground voltage, and the write/ground voltage line N, (j=O-k-
By sequentially applying write voltages to only the necessary items in 1) at arbitrary time intervals and at arbitrary times, information can be written to j rows of the matrix k times or less.

In addition, a field effect transistor (hereinafter referred to as "
(abbreviated as "pulled out transistor"), the gates of the pulled out transistors in each unit element are commonly connected in the horizontal direction, or the n drawn out transistors in the horizontal direction are combined and shared as one. Make this transistor conductive by making it usable, and then, as above,
By sequentially applying a write voltage to only the necessary ones of the write/ground voltage lines Nj (j=0 to k-1) at arbitrary time intervals for an arbitrary time, row j is applied k times or less. Information can be written. ), k=
In the case of 1, information is written to all j rows of associative memories at once. At this time, a current is applied to the n content addressable memories in the j row to perform writing, but the current is large and a problem may occur in the commonly connected M, or in the case where a pullout transistor is provided, the pullout transistor and M. When a large current needs to flow, divide the n associative memories into an arbitrary number of k (k≧2) associative memories, and write to the n associative memories in j rows twice or more. By doing so, there is no need to flow a large current through M or the extraction transistor and M at once, and as a result, the area occupied by these can also be reduced. As mentioned above,
A variable resistance element whose resistance value changes irreversibly depending on applied voltage or current, or both, and a field effect transistor are used to collate stored information and input data to create an associative memory that can detect coincidence or mismatch between the two. Therefore, this effect can be used to repair defective bits in random access memory. That is, the address lines Ai and K of the random access memory are connected to the data input line D and the inverted data input line 5, respectively, and the address information of the random access memory is used as input data, and the address information of the random access memory is connected to the associative memory. By writing and storing the address of the defective bit, it is possible to detect whether the address information in the random access memory is the address of the defective bit or the address of the good bit. Now, let us consider the case where the verification output line M, has been precharged and is in a high voltage state. At this time, if the address information of the random access memory is the address of the defective bit, the storage information of the associative memory and the address information of the random access memory match, so the verification output line M is output. -M. ．． Only one of the corresponding wires is open, maintaining a high voltage state.
On the other hand, if the address information of the random access memory is an address with good bits, the storage information of the associative memory and the address information of the random access memory do not match, so all verification output lines M are grounded. Therefore, by adding a circuit that can switch between a spare memory and a defective bit by the output of the verification output line, the defective bit of the random access memory can be relieved. In addition, since the associative memory mentioned above stores the address of the defective bit in the random access memory as non-volatile information, the address of the defective bit can be written at the time of product shipment (before device mounting), and the product can be seen from the outside. It can always provide 100% good bit random access memory. Although field effect transistors are used in the embodiments described above, it is also possible to construct them using various other semiconductor active elements.

As explained above, the associative memory of the present invention includes a variable resistance element and a field effect transistor whose resistance value changes irreversibly from high resistance to low resistance or from low resistance to high resistance depending on applied voltage or current or both. Since information is stored using semiconductor active elements such as , and the stored information is compared with input data, the circuit configuration is simple and the number of elements is small, so the occupied area can be small. Since the current flows only when there is a mismatch, the power consumption can be reduced and the capacity can be increased easily.

Furthermore, when increasing the capacity, the overall occupied area can be reduced by adopting a configuration that allows writing to be performed in parts. Furthermore, when this associative memory is configured and used on the same chip as other logic circuits or random access memory, etc., the information cannot be written at the time of product shipment (before device mounting) because the stored information is non-volatile. As a result, it is convenient to use. In particular, when this associative memory is applied to repair defective bits in random access memory, the address of the defective bit can be written at the time of product shipment, so random access with 100% good bits is always possible when viewed from the outside as a manufactured product. It has the advantage of being able to serve as memory.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional associative memory, Fig. 2 is a circuit diagram of an embodiment of an associative memory of the present invention, and Fig. 3 is a circuit diagram of an associative memory according to an embodiment of the present invention. FIG. 2 is a diagram showing an enlarged example of the associative memory of the present invention. D pin...Input data line, Xun...Inverted input data line, W,...Write line, Mr...Verification output line, Nj... Write/ground voltage line, Q
1 to 10 and QIj...field effect transistor, R,...variable resistance element.

Claims (1)

[Claims] 1. First and second variable resistors whose resistance value irreversibly changes from high resistance to low resistance or from low resistance to high resistance by applying a voltage or current or both of a critical value or more. element, and first and second semiconductor active elements whose conduction and non-conduction are controlled by the voltage applied to the control terminal, and the ground voltage is used when writing information, and the verification output is independent of the ground voltage when reading information. The first variable resistance element and the first semiconductor active element are connected between a first node which is a wire and a second node to which a write voltage is applied when writing information and a ground voltage is applied when reading information. A series circuit is connected to a series circuit consisting of the second variable resistance element and the second semiconductor active element, and an input data line is connected to the control terminal of the first semiconductor active element, and an input data line is connected to the control terminal of the first semiconductor active element. An associative memory characterized in that an inverted input data line is connected to a control terminal of a semiconductor active element. 2. A patent characterized in that the first node is connected to ground via a third semiconductor active element, and the third semiconductor active element is brought into a conductive state when writing information and is brought into a non-conductive state when reading information. An associative memory according to claim 1. 3. A series circuit consisting of the first variable resistance element and the first semiconductor active element, and a series circuit consisting of the second variable resistance element and the second semiconductor active element as unit elements, The unit elements are arranged in a matrix, the horizontal first nodes in each unit element are commonly connected, the vertical input data lines and inverted input lines in each unit element are each commonly connected, and The entire matrix of second nodes in each unit element is divided into an arbitrary number of node groups each consisting of an arbitrary number of nodes, and the nodes within each node group are commonly connected, and when writing information, the Each node group is sequentially set to a write voltage for an arbitrary time at an arbitrary time interval,
3. The content addressable memory according to claim 1 or 2, wherein all node groups are set to ground voltage during reading. 4. The associative memory is configured on the same substrate as the semiconductor substrate on which the random access memory is formed, address information of the random access memory is provided to the first and second semiconductor active elements, and addresses of defective bits of the random access memory are stored. 4. The associative memory according to claim 3, wherein the associative memory is configured to: