JPS6043690B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel selection device such as a television receiver, and more particularly to a frequency synthesizer type channel selection device.

Conventionally, a frequency synthesizer method using a phase locked loop (hereinafter referred to as PLL) has been known as a channel selection device for a television receiver.

FIG. 1 is a diagram showing a schematic configuration thereof, and in the figure, 1 is a frequency synthesizer. This synthesizer 1 divides the local oscillation frequency (FOi) of a local oscillator 2 by N using a frequency divider 3, and then divides the frequency into N by a frequency comparator 5 using the oscillation frequency (F, 8f) of a highly stable reference oscillator 4 such as a crystal oscillator. The phase is compared and the output of the phase comparator 5 is fed back to the local oscillator 2 as a substantially DC voltage via a loop filter 6. In this way, the oscillation frequency FOi that has been phase-synchronized by the synthesizer 1 and the antenna 7 to R
Broadcasting frequencies F and N sent via the F amplifier are mixed by a mixer 8 to create an intermediate frequency FIN, which is sent to the detection stage via the IF amplifier. The frequency division ratio in synthesizer 1 can be determined using channel selection button 9.
This is done in the channel selection number memory 10. In this way, the following equation holds between the local oscillation frequency FOi, the oscillation frequency FrO of the reference oscillator 4, and the frequency division ratio N of the variable frequency divider 2 when used in an electronic channel selection device. Furthermore, FOi and broadcast frequency f! The following equation holds true between N and the medium frequency number f■.

Therefore, by changing N in accordance with the channel number, the local oscillation frequency FOi can be changed, and as a result, each station can be arbitrarily selected.

As shown in the first equation above, an electronic tuning device using a frequency synthesizer has the great feature of being able to extract a highly stable local oscillation frequency synchronized with a highly stable oscillator such as a crystal oscillator.

However, since N in the first equation is a positive integer, various measures have been taken to finely adjust the oscillation frequency of the local oscillator in electronic tuning devices using conventional frequency synthesizers. Ta. That is, since the carrier wave frequency emitted from the broadcasting station is highly stable, there is generally no need for fine adjustment if the receiver side outputs a corresponding local oscillation frequency. However, when rebroadcasting occurs after frequency conversion between broadcasting stations as in CATV, offset frequencies occur between stations, and deviations in the transmission carrier frequency as in video games, which have recently become popular, occur. If the input frequency is shifted, fine adjustment of the frequency must be performed on the receiver side, otherwise tuning may occur, resulting in image deterioration or even making it impossible to select a channel. Therefore, in the case of a conventional frequency synthesizer incorporated in a channel selection device, in order to solve the problem of fine adjustment as described above, for example, the value of N in the first equation can be increased to perform equivalent fine adjustment. Instead of a highly stable reference oscillator using a crystal oscillator, an LC oscillator or the like with a relatively variable range has been used for fine adjustment. However, the first
In a configuration where the value of N in the equation is large, if the fine adjustment steps are made small, the value of N will become very large.
Also, if such an LC oscillator is used as a reference oscillator,
Since its own oscillation is unstable, the stability of the local oscillator synchronized with it is no longer sufficient, and the high stability that is the original feature of using a frequency synthesizer as an electronic tuning device is lost. . Furthermore, the conventional system in which fine tuning is performed using a reference oscillator has the following drawbacks. That is, in the first equation, when the oscillation frequency of the reference oscillator is changed as shown in the following equation, the local oscillation frequency becomes as follows from the first equation.

This formula shows that when the oscillation frequency of the reference oscillator is changed by Δf, the oscillation frequency of the local oscillator changes by N·Δf, but since N generally varies depending on the channel selected, This resulted in the local oscillator fine tuning range and fine tuning step changing depending on the selected channel. The present invention has been made in order to eliminate the drawbacks of the conventional devices as described above, and uses a highly stable oscillator such as a crystal oscillator as a reference oscillator, while allowing a constant fine adjustment step regardless of the selected channel. The present invention aims to provide a tuning device using a frequency synthesizer that can finely adjust the frequency.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the apparatus of the present invention. The device of the present invention can be broadly divided into a synthesizer section 19.
, a synthesizer driving section 44, and a mixing section 48. These will be explained in detail below. First, the synthesizer section 19 will be explained.

12 is a local oscillator, and the output signal of this oscillator 12 (FO
i) is divided by the circuit indicated by 49 and this output (J
O) is applied to the phase comparator 17 and compared in phase with the oscillation frequency FrO of a highly stable reference oscillator 16 such as a crystal oscillator.

The result of the phase comparison is converted to a substantially direct current voltage according to the phase comparison state through the low-pass filter 18, and is fed back to the local oscillator 12. In the frequency synthesizer section 19 of the present invention configured as described above, the output frequency of the first variable frequency divider 14 is determined according to the operation of the circuit indicated by 49 in FIG. FOl decides. Therefore, the operation of the circuit indicated by 49 will be explained next.

This circuit 49 includes a first frequency divider 14 that obtains a frequency division of 1/m, and a second frequency divider 15 that receives the output of the reference signal generator 16 and outputs a Q-generated pulse upon input of a P-generated pulse. an input pulse extracting circuit 13 which thins out the input clock pulse (FOi) to be applied to the first frequency divider 14 in accordance with the rising or falling timing of the output signal of the second frequency divider 15. have First, the second frequency divider 15, which outputs a Q-generated pulse upon input of a P-generated pulse, will be described. FIG. 3 shows an example of the configuration of such a frequency divider, and FIG. 4 is a time chart thereof. The configuration example shown in FIG. 3 outputs 0 to 7 pulses in response to 8 clock pulses. Flip-flops 50, 51, and 52 are connected in cascade to form a synchronous counter. If each flip-flop operates on the rising edge of a clock pulse, the output Q of each flip-flop with respect to the clock pulse (CP) is
a, Qb, and Qc follow the time chart in FIG. Among the thus obtained CP, Qa, Qb, Qc and their inverted outputs, ? , σ, (CP△mutual a
), (CP△Qa△ηb), (CP△Qa.△Qb△mutc) are taken by AND gates 54, 55, and 56, respectively, and as shown in FIG. During input, 4 pulses, 2 pulses, and 1 pulse are output at different times. Further, by selecting these outputs using the input control terminals CO, Cl, and C2 of the AND gates 57, 58, and 59, and calculating the sum using the OR gate 60, the pulse output of 0 to 7 shots can be arbitrarily controlled. I can do it. For example, CO=logic “゜0゛,
In the case of C1 = logic ゛゜1゛ and C2 = logic ゜゜“1゛, the raw output becomes (CP△mutual a) (CP/XQa△0b), and as shown in Fig. 4, it becomes 8 clock pulses. In contrast, it outputs 6 pulses.Since the period is P, the frequency division ratio of the frequency divider that obtains the output pulse of Q from the input clock pulse of P is Q/P. The present invention is characterized by the use of a frequency divider that performs such Q/P frequency division.

Returning to FIG. 2 below, the operation of the circuit 49 will be explained.
The circuit 49 has a first frequency divider 14 that performs 1/m frequency division, and at the same time a second frequency divider 15 that performs Q/P frequency division of the output of the reference oscillator 16. 1
3 reads the rising edge of the output pulse of the second frequency divider 15, and divides the pulse that should be input into the first frequency divider 14 by 1.
A configuration is adopted in which the output is pulled out.

The input pulse extracting circuit 13 performs an operation of reliably extracting only one pulse that should be input to the first frequency divider, depending on the timing of the output of the second frequency divider.

The operation of this frequency dividing circuit 49 will be explained with reference to an embodiment shown in FIG. The circuit indicated by 13 in FIG. 5 is an input pulse extracting circuit, and the flip-flops 61 and 62 operate at the falling edge of the clock pulse, and reset is performed when the reset terminal is at logic 0.0. Further, NAND gates 64 and 65 constitute a zero-reset R-S flip-flop 66. The operation of the circuit of FIG. 5 including the circuit 13 is shown in the time chart of FIG. 6. In this figure, m=8, P=2, Q=1 in Figure 5.
The case is shown below. First, the output of the second frequency divider 15 is a logic
0'', the output 03 of the R-S flip-flop 66 is logic ``r'', and the flip-flops 61 and 62 do not receive the reset clock pulse through the AND gate 67 and maintain their initial state. The output 02 of the flip-flop 62 is logic ゛゜1゛, and the clock pulse is inputted to the first frequency divider 14 by the AND gate 68. Then, when the output of the second frequency divider 15 becomes logic ゛゜r'. , a clock pulse is input from the AND gate 67 to the flip-flop 61, but the flip-flops 61, 62
The R-S flip-flop 66 is set at the time when the outputs Q1 and Q2 of the circuit become logic "1" at the same time, and the flip-flops 61 and 62 are reset. When the output pulse of returns to logic "0", it is reset and returns to the initial state.
At this time, the clock pulse input to the first frequency divider 14 is passed through the AND gate 68 to the output ' of the flip-flop 62.
Since it is given as a product output with Q2, only one shot is extracted according to the time chart of FIG. In other words, in the circuit shown in FIG.
At a certain time, the operation of thinning out one pulse to be input to the first frequency divider 14 is repeated according to the output signal of the second frequency divider 15. The oscillation frequency FOi of the local oscillator 12 and the oscillation frequency F. of the reference oscillator 16 in the frequency synthesizer shown in FIG. The general formula that holds true between ef and ef is derived as follows. The local oscillator 12 with the oscillation frequency FOi outputs a NO pulse per unit time, and the oscillation frequency is FOi. If it is assumed that the reference oscillator 16, which is ef, outputs Nr pulses, the following relational expression holds true during phase synchronization.

When converted to frequency, it becomes.

This seventh equation shows that the oscillation output of the local oscillator 12 is (m+PIQ
) This means that an output equivalent to that passed through the frequency divider that performs frequency division is obtained as the output of the first frequency divider 14. In this seventh equation, P is P=P1 and Q is Q=0.
,1,2,...,P1-1,m as m=m1-1,m1,
When changing m1+1, the oscillation frequency of the local oscillator 12 becomes, for example, f″0i(m1-1)·f″, . and f″0i=
Frequency step Δf(Δ
f=F. J/P) can be used to change it at equal intervals.

This is shown in Table 1 below. Furthermore, as is clear from the above formula 7 and Table 1, this frequency fine adjustment step (Δf) is independent of the frequency division number m corresponding to the selected channel, and is always a constant frequency regardless of the selected channel. It becomes possible to control the local oscillator 12 with fine adjustment steps (Δf).

Next, details of the synthesizer drive section 44 will be explained.

In FIG. 2, up-down counters 28 and 29 are continuously connected as shown in FIG. The values of the up/down counters 28 and 29 are preset when the strobe terminal is logic "0", and the up-count operation is achieved by setting both the down-count input and the strobe terminal to logic "1" and inputting a clock from the up-count input. , the down-count operation is performed by setting both the up-count input and the strobe terminal to logic ``1'' and inputting a clock from the down-count input. In this case, the clock is a synthesizer in the embodiment shown in FIG. The frequency is obtained from the reference oscillator 16 in the section 19 via the frequency divider 30.When a channel number is first set using the channel button 25, the channel number is converted to a predetermined frequency division number using the number memory 26. At the same time, for example, by driving the one-shot monostable multivibrator 27 and obtaining its O output, the strobe terminals of the up/down counters 28 and 29 are set to logic ゜゜0゛.
The frequency division number obtained by 6 is used as an up/down counter 28
The up-down counter 29 is preset to logic "0" at all input terminals as an initial state.The values preset to the up-down counters 28 and 29 are the first and second
The synthesizer 19 is driven to guide the oscillation frequency of the local oscillator 12 to the oscillation frequency corresponding to the channel number. In this way, the local source is decided,
The radio waves of the set channel are received, but the mixer 4
If the video carrier wave of the output of 8 (i.e. the IF output of the tuner) is not completely tuned to 58.75MHz,
A voltage as shown in FIG. 7a is generated at the output of the automatic frequency tuning circuit (hereinafter referred to as AF'T) 31. Returning to FIG. 2, this fine adjustment using the AF'T3l output voltage is performed after the oscillation frequency of the local oscillator 12 is synchronized with the reference oscillator 16.
The one-shot monostable multivibrator 27 returns to its initial state, and the up/down counters 28, 29
This is done when the strobe terminal of the AFT becomes logic "1". At this time, it is detected from the video stage whether the output voltage of the AFT 3l is influenced by the audio carrier wave of the adjacent channel using, for example, a synchronization signal, By feeding this signal back to the AFT inhibition terminal 46, fine adjustment by AFT is started when the layer T inhibition terminal 46 is at logic ゛も゛. The output of the control signal AFT3l of the up-down counters 28 and 29 is set to 0.) A voltage comparison circuit (hereinafter referred to as a window comparator) consisting of level comparators 32 and 33 and an AND gate 35 and a level comparator It is created by combining the two output signals of 34 and 34. (Here, level comparator 32
, 33, and 34 output logic "1" when the potential of the 1 input terminal becomes higher than the potential of the O input terminal, and the potential of the 1 input terminal becomes 8.
It is assumed that the comparator circuit outputs a logic "0" when the potential is lower than the potential of the input terminal.) Figure 7b shows the AFT output signal.The output of this window comparator (the output of the AND gate 35) and the Figure c is level comparator 3
4 shows the characteristics of the output signal of No. 4 to the AF'T circuit 31. If the AFT3l output voltage is now lower than the lower limit level voltage, the video carrier wave is at its reference frequency58,
75r1V4HZ, local oscillator 12
The oscillation frequency is also set higher than the optimum oscillation frequency for the receiving channel. Therefore, the up-down counter 29's up-count input terminal is set to logic ``1'', and the clock pulse obtained by the frequency divider 30 is sent from the down-count input terminal.As a result, the up-down counter 29 counts down, but the count value Borrow (BOR) occurs when changes from O to the next state.
An output pulse is generated from the ROW) terminal.

Since this output pulse is applied to the down count input terminal of the up/down counter 28, the divided wave of the first frequency divider 14 is (if the initial value is (m1)).
m1-1). The oscillation frequency of the local oscillator 12 (FO
i), as shown in Table 1 above, every time it counts down according to the clock, the frequency step Δf (Δf=
Plfref). After counting down by n clocks, the oscillation frequency of the local oscillator and the video carrier frequency FIF at the front stage are (however, f″0i
and f″1F is the frequency in the initial state).

When the down-count continues in this manner and the AFT 3l output voltage falls within the upper and lower limit level voltages of the window comparator, both the up-count input terminal and the down-count input terminal become logic ``1'', stopping the down-counting and maintaining that state. At such a stable point, the equation becomes 1
This holds true regarding the image carrier frequency (FIp) at the F stage.

This formula clearly shows the first wave set to receive the desired wave.
It has nothing to do with the frequency division number of the frequency divider 14. Next AFT3
If the output voltage of l is within the upper and lower limit level voltages, both the up-count input terminal and the down-count input terminal become logic "1" so that the up-down counters 28 and 29 maintain their states.Furthermore, AF'T3l When the output voltage is higher than the upper limit level, the down-count input terminal of the up-down counter 29 becomes logic "゜1゛" so as to increase the oscillation frequency of the local oscillator 12, and the clock pulse from the frequency divider 30 is input as an up-count input. sent to the edge.
As a result, Atupda. The counter 29 performs an up-count operation, and when the count value changes from the maximum value to 0, an output pulse is generated at the carry (CARRY) terminal. Since this output pulse is applied to the up-count input terminal of the up-down counter 28, the 31st frequency divided wave becomes (m1+1) when the initial value is (m1). In this case as well, the eighth equation holds true when up-counting is stopped. Next, if the AFT 3l output voltage is affected by the audio carrier wave of an adjacent channel, or if the video carrier frequency of the desired channel 1 exceeds the control range of the AFT 3l, automatic adjustment must be abandoned.

This is done by setting the AFT inhibit input 46 to logic ``1''. In such a case, by controlling the manual inputs 45 and 47 from the outside, fine adjustment can be made in frequency steps of Δf (Δf=P/Fref) while monitoring the video, for example. As explained in detail above, according to the present invention, even if the desired input frequency arrives at a deviation from the regular frequency, the variable frequency division can uniformly change the value below the decimal point step by step regardless of the selected channel. The circuit automatically fine-tunes the local oscillator using the AFT output, and the highly stable reference oscillator is used as is to take advantage of the features of the synthesizer method, making it possible to obtain stable images. A desired input frequency that exceeds the control range of AF'T can be provided. The output information of layer T alone is not sufficient when the image quality is adjusted to the best point, especially in weak electric field areas, or when it is necessary to suppress the influence of interference waves to a minimum. However, even in such cases, according to the device of the present invention, it is possible to provide a tuning device that allows manual fine tuning while taking advantage of the features of the synthesizer method.

Furthermore, regarding the allocation of the oscillation frequency of the local oscillator, not only in regions where integer values are assigned in megahertz units such as Japan and the United States, but also in regions where values are assigned in decimal places such as Europe, it is simply a decimal point. It is possible to provide a channel selection device that can be easily applied by simply presetting the value of .

Note that the present invention is applicable not only to television receivers but also to AM, .
Needless to say, it can also be applied as a channel selection device for FM radio, transceivers, etc.

Note that the present invention is not limited to the above-described embodiments. For example, the synthesizer section can be expanded to a frequency synthesizer with a prescaler 70 as shown in FIG.
The oscillation frequency of the local oscillator 12 (FO
i) using the reference frequency (Fr..,).

Also, if we extend this method inductively as shown in Figure 9, we get
The oscillation frequency FOi in this case is given by: The circuits shown in FIGS. 8 and 9 can be replaced with the synthesizer section 19 without changing the synthesizer drive section 44 in FIG. 2.

Furthermore, as shown in FIG.
6 and its output as a reference signal F.6. It is also possible to provide a configuration in which the signal is supplied as ef to the phase comparator and the input of the second variable frequency divider 15 is obtained from the reference oscillator 16.
The oscillation frequency of the voltage controlled oscillator 12 in this case is given by.

In this invention, in which the input of the second variable frequency divider 15 is taken from the reference oscillator 16, the VCOl2
The output frequency FOj can be changed by the frequency division ratio 1/k. Further, the pulse extracting circuit is not limited to the circuit shown in FIG. 5 and 13. FIG. 11 shows an example of a configuration using a separate circuit. This circuit is designated as 13 in FIG. 2. The clock pulse input to the first frequency divider is thinned out at the falling timing of the output signal of the second frequency divider 15. This situation is shown in the time chart of FIG. In general, in the pulse extracting circuit, the frequency division ratio of the first frequency divider 14 is (m) at the timing of the output signal of the second frequency divider 15 in FIG.
This is equivalent to converting from to (n+1). Further Q
The frequency divider that performs /P frequency division is not limited to the circuit shown in FIG. It is fine as long as it can be changed in stages. Note that the loop filter in the phase-locked circuit according to the present invention, for example in the embodiment shown in FIG. 2, does not degrade the performance of the local spectrum if the band is limited so as to sufficiently suppress the frequency component (f, Ef/P). It's not even a thing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional channel selection device, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram of an example of a Q/P frequency dividing circuit used in the present invention. Figure 4 is the third
FIG. 5 is an explanatory diagram of a part of the configuration of the present invention; FIG. 6 is an explanatory diagram of the operation of FIG. 5; FIG. 7 is an explanatory diagram of AF'T output; FIGS. 10 and 11 are diagrams showing other examples of a part of the configuration of the present invention, and FIG.
It is an explanatory diagram of the operation of the figure. 12... Local oscillator, 16... Reference oscillator, 17... Phase comparator, 18... Loop filter, 19... Synthesizer section, 4
4...Synthesizer drive section, 49...
・Frequency dividing circuit.

Claims (1)

[Claims] 1. A first variable frequency divider that divides the output frequency of the local oscillator by a division ratio corresponding to the channel to be selected;
A means for comparing the phase of the output of the frequency divider with a reference signal from the reference signal generating means and feeding back the comparison result to the local oscillator to apply phase synchronization, and receiving the local oscillation output that has been phase synchronized by this means. a second variable frequency divider that divides the output from the reference signal generating means so that a pulse input from P outputs a pulse from Q; means for changing the period of the output signal of the first variable frequency divider in response to the timing of the output signal of the second variable frequency divider; and a frequency division ratio of the second variable frequency divider. A channel selection device comprising means for variably controlling the channel according to the reception state. 2. The reference signal generation means includes a reference signal oscillator and a frequency divider that divides the output of this oscillator, supplies the output of the frequency divider as a reference signal to a phase comparator, and outputs the output of the reference signal oscillator to a second 2. The channel selection device according to claim 1, wherein said channel selection device is adapted to supply said signal to a variable frequency frequency divider. 3. The means for variably controlling the frequency division ratio of the second variable frequency frequency divider includes means for detecting a detuned state of the intermediate frequency, and a means for up-counting or increasing the number of clock pulses according to the detected detuned state. 2. The channel selection device according to claim 1, comprising a counter that counts down and means for transmitting the count value of the counter to the second variable frequency divider. 4. The channel selection device according to claim 1, wherein the first variable frequency frequency divider divides the output of the local oscillator after passing it through a prescaler. 5. The first variable frequency divider is composed of a first prescaler, a second prescaler, and a first variable frequency divider circuit connected in cascade, and the second variable frequency divider is configured to
and second and third variable frequency divider circuits that divide the output of the variable frequency divider at different frequency division ratios, respectively, and
The period of the output signal of the first variable frequency divider circuit is changed at the output timing of the variable frequency divider circuit, and the period of the output signal of the second prescaler is changed at the output timing of the third variable frequency divider circuit. The channel selection device according to claim 1, characterized in that the channel selection device is configured to change the channel selection device.