JPS6043521B2 - Programmable feed control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention sequentially reads control data that is stored in a program storage unit and instructs a feed control cycle according to a program counter, and uses the read control data to determine the feed amount and feed rate as machining conditions. Regarding a programmable feed control device that controls the feed of a moving object by selecting a set digital switch, its purpose is to easily change the feed rate and feed rate as processing conditions by changing the settings of the digital switch, and to control the feed of a moving object by selecting a set digital switch. To provide a control device suitable for controlling a grinding machine by making it possible to easily change a feed operation cycle by changing a control zeta stored in a storage section.

In general, the processing conditions for grinding cannot be determined unambiguously based on past experience, and if the shape and dimensions change even slightly, the same processing conditions may become unstable, making it impossible to obtain the required surface accuracy. .

For this reason, it is necessary to program machining conditions based on past experience and try grinding first, and if any problems are found, change the machining conditions as appropriate and grind to find the best machining conditions. In order to programmatically control grinding in this way, it is necessary to be able to easily change the machining conditions, and with conventional paper tape numerical control devices, it is not possible to change the machining and machining conditions without remaking the tape. It is not suitable for program control of the panel. On the other hand, there are program control devices that set various data as machining conditions on digital switches, but in this case, the above-mentioned inconvenience is resolved and machining conditions can be changed freely by changing the settings of the digital switches. be able to.

However, the control circuit that sequentially switches the digital switch according to the feed stage is fixed, and there is almost no flexibility in changing the cycle, and the cycle changes depending on the model, such as a cam grinder or a crank pin grinder. It is difficult to adapt to changes. In view of this, the present invention aims to provide a control device suitable for program control of a grinding machine, which can easily accommodate changes in machining conditions and cycles.

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 1 is a block diagram of a programmable feed control device that controls the feed of a controlled object such as a grinding machine. This is a pulse motor drive circuit that drives the pulse motor 1 in the forward direction by the number of pulses and also drives the pulse motor 1 in the backward direction by the number of pulses received by the backward feed pulse-FP. Note that, if necessary, a pulse motor and a pulse motor drive circuit for not only one axis but also other feed axes may be provided, but a description thereof will be omitted in this specification. 3 is a program storage unit using a diode matrix circuit, and each memory address M
O to M47 respectively indicate the control swivel feed axes Should feed speed F1 to F1, auxiliary functions to select M1 to M7,
It is possible to store control data such as Sl to S7 (S1 is a command to return to the original position of the grindstone, and S4 is a command to correct grindstone wear), program end, etc.

An example of the program is shown in Table 1. In Table 1, the program is for controlling a grinding machine, and memory addresses MO to M7 store the normal feed control cycle program for the grindstone head, and M4l to M42 store the emergency return cycle which is an emergency cycle. The program is memorized and M43
~M44 stores a grindstone wear correction cycle program. For the sake of convenience, the embodiments described below will be described with reference to a case where the present invention is applied to a grinding machine. PBl is an operation start signal EX. for starting a normal feed control cycle.
4 is a manual external command switch that turns on STARTl, and 4 is an external command switch that turns on operation start signal EX.
When STARTl is input, the feed control cycle signal START is applied until timing pulse CL2, which will be described later, is input.
This is a signal level conversion circuit that continues to output l signals. P.B.
2 is a grindstone wear correction start signal EX.2 for starting the grindstone wear correction cycle. A manual external command switch 5 turns on START2, and external command switch PB2 outputs the grindstone wear correction start signal EX. This is a signal level conversion circuit that continues to output the grindstone wear correction cycle signal START2 when START2 is input until the timing pulse CL2 is input. PB3 sends an emergency return start signal EX. to start the emergency return cycle. Manual external command switch to turn on EMB, 6 is external command switch PB
3, emergency return start signal EX. This is a signal level conversion circuit that outputs an emergency return cycle signal when EMB is turned on.

Although the signal level conversion circuit for controlling the auxiliary function operation is not shown, the instruction decoder 18 described later
When the auxiliary function signals M1 to M7 are outputted from the auxiliary function signals M1 to M47, an auxiliary function device operation start signal EX. Ml
~EX. M2 is output to each auxiliary function device, and the auxiliary function device specified by the auxiliary function signals M1 to M7 operates and its operation confirmation signal EX. When MF'IN is output, M. FI
Outputs N signal.

For example, the auxiliary function signal M1 is a signal that commands the hydraulic feed advance of a rest (not shown), and when the rest reaches the hydraulic feed advance end, the hydraulic feed advance completion signal EX. rvlF'1N is output.

The auxiliary function signal M2 is a signal that commands the hydraulic feed and retreat of the rest, and the hydraulic feed and retreat start confirmation signal M2 causes the rest to start hydraulic feed and retreat. FIN is now output. Reference numeral 7 denotes a timing pulse generation circuit that outputs timing pulses CLl to CL5 during the control data read cycle and stops outputting the timing pulses CLl to CL5 when performing a feed operation.

8 is a run flag circuit that outputs a RUN signal during a normal feed control cycle and a grindstone wear correction cycle, and 9 is an EMB. SDW signal, EMB. CLK
Signal, EMB. ST signal and EMB. An emergency return run flag circuit outputs a CYCLE signal, and 10 is a busy flag circuit that outputs a BUSY signal during execution of the feed operation.

Specific examples of these circuits 7 to 10 are shown in FIG.

The timing pulse generation circuit 7 always generates a clock pulse C.
A clock pulse generator 71 that outputs L, a shift register that outputs timing pulses CL1 to CL5 for one cycle by the shifting action of a clock pulse CL that is input to a shift terminal when an input is input to a serial terminal, and a shift register 72. The output terminal is connected to the OR gate 73 which outputs a 0P signal while the timing pulses CL1 to CL5 are being output, the RUN signal output terminal of the inverter 7 run flag circuit 8 to which the OR gate 73 is connected, and the EMB. of the emergency return run flag circuit 9. OR gate 75 to which the CYCLE output terminal is connected, BUSY of the busy flag circuit 10
An inverter 76 to which the signal output terminal is connected, an OR gate 75, an AND gate 77 to which the output terminals of the inverters 74 and 76 are connected and connected to the serial terminal of the shift register 72, and an inverter to which the output terminal of the clock pulse oscillator 71 is connected. It is composed of 78. Therefore, this timing pulse generation circuit 7 receives the RUN signal or the E
M.B. CYCLE signal is output and timing pulse CL
If the output of the BUSY signal is stopped when l~CL5 is not output, one cycle of timing pulse CLl~
Start outputting CL5. The emergency return run flag circuit 9 is
The inverter 91 is connected to the EMB signal output terminal of the signal level conversion circuit 6, and the inverter 91 is connected to the T terminal, and the output terminal of an OR gate 98, which will be described later, is connected to the reset terminal R. When set, EMB. SDW
A J-K flip-flop 92 that outputs a signal (J-K flip-flop is configured such that at the moment the T terminal input changes from a high level potential to a low level potential, the J terminal input is at a high level potential and the K terminal input is at a low level. If the potential is at a low level, it is set; conversely, if the J terminal input is at a low level potential and the K terminal input is at a high level potential, it is reset, and when the input to the reset terminal R becomes a low level potential, the other input terminals J, T, ), the AND gate 93 is connected to the Q terminal of the J-K flip-flop 92 and the output terminal of the inverter 74 of the timing pulse generation circuit 7, and the AND gate 93 is connected to the J terminal. The inverter 78 of the timing pulse generation circuit 7 is connected to the T terminal, and the inverter 99 (described later) is connected to the reset terminal R.
is connected and set, EMB. A J-K flip-flop 94 that outputs the CLK signal, an AND gate 95 to which the Q terminal of the J-K flip-flop 94 and the CL2 pulse output terminal of the shift register 72 of the timing pulse generation circuit 7 are connected, and an END of the instruction decoder 18 to be described later. An AND gate 96 is connected to the signal output terminal and the CL5 pulse output terminal of the shift register 72, an AND gate 95 is connected to the J terminal, an inverter 78 of the timing pulse generation circuit 7 is connected to the T terminal, and an ungate 96 is connected to the K terminal. When connected and set, EMB. J-K that outputs ST signal
Flip-flop 97, J-K flip-flop 94,
The Q terminal of EMB.97 is connected. CLK signal and E
M.B. OR gate 98 to pass as CYCLE signal
, an inverter 99 connected to the Q terminal of a JK flip-flop 97. Therefore, when the EMB signal is output, the emergency return run flag circuit 9 performs an EMB. SDW signal, EMB. CLK signal, EMB. S
T signals are sequentially output, and the EMB. CLK signal and EMB
．． EMB at the same time as ST signal. Outputs the CYCLE signal.

The run flag circuit 8 includes an OR gate 81 to which the output terminals of the signal level conversion circuits 4 and 5 are connected, an AND gate 82 to which the END signal output terminal of the instruction decoder 18 and the CL5 pulse output terminal of the shift register 72 are connected, and a J- An inverter 83 is connected to the Q terminal of the K flip-flop 92, and an OR gate 81 is connected to the J terminal.
is connected, the inverter 78 of the timing pulse generation circuit 7 is connected to the T terminal, the AND gate 82 is connected to the K terminal, and the inverter 83 is connected to the reset terminal R. When set, the J outputs the RUN signal to the Q terminal. -K
It is composed of a flip-flop 84.

Therefore, when the START1 signal or START2 signal is output, the run flag circuit 8 outputs the END signal or EMB. The R[-JN signal is output until the SDW signal is output. The busy flag circuit 10 is connected to the D. SIG signal output terminal, T. S.I.
G signal output terminal and S1 signal output terminal and M1~
OR gate ICl, J to which each M7 signal output terminal is connected
- OR gate 102 to which the Q terminals of K flip-flops 84 and 97 are connected; OR gates 101 and 102;
is connected to the AND gate 103, the Q output terminal of the JK flip-flop 92, and the feed control counter 54, which will be described later.
and the M.DEN signal output terminal of the signal level conversion circuit. An inverter 105 is connected to an OR gate 104 connected to the FIN signal output terminal, an AND gate 103 is connected to the J terminal, a CL5 pulse output terminal of the shift register 72 is connected to the T terminal, and an inverter 105 is connected to the reset terminal R. The JK flip-flop 106 outputs a BUSY signal to the Q terminal when connected and set.

Therefore, this busy flag circuit 10 is used for EMB. When the ST signal or RUN signal is output, the D. S.I.G.
,T. If either SIG or SL is output, the BUSY signal is output from the time when the output of the timing pulse CL5 is completed, and the END signal or EMB. When the SDW signal is output, the output of the BUSY signal is stopped.

In FIG. 1, reference numeral 11 denotes a program counter that designates a memory address in the program storage section 4 to be read.

12 is the start address of the emergency return cycle program (M
4l) is the emergency return cycle start address setting circuit.

13 is a grindstone wear correction cycle start address setting circuit in which the start address (M43) of the grindstone wear correction cycle program is set; 14 is a circuit through which the output of the emergency return cycle start address setting circuit 12 is normally passed, and the signal level conversion circuit 5 This is an address gate circuit that allows the output of the grindstone wear correction cycle start address setting circuit 13 to pass through when the START2 signal is output from.

15 resets the contents of the program counter 11 to MO when the timing pulse CLl is inputted when the STARTl signal is inputted, and passes through the address gate circuit 14 when the timing pulse CLl is inputted when the START2 signal is inputted. The setting position (M4l) of the start address setting circuit 12 to be set is set by the program counter 11.
The EMB. When the CLK signal is input, the setting value (M43) of the start address setting circuit 13 passing through the address gate circuit 14 is loaded into the program counter 11 when the timing pulse CLl is input, and the STARTl signal, START2 signal, EMB,. This is a program control circuit that increments the contents of the program counter 11 by 1 when the timing pulse CLl is input when none of the CLK signals are input.

Reference numeral 16 denotes an address decoder which decodes the contents of the program counter 11 and validates the memory address of the program storage section 3 specified by the contents.

17 is an instruction register for reading out and temporarily storing the control data stored in the enabled memory address of the program storage unit 3 in response to input of the timing pulse CL2; 18 is an instruction for decoding the control data stored in the register 17; It is a decoder.

This decoder 18 receives the control data X, Y, +, -,
In addition to decoding M1 to M7, Sl to S7, END, etc., if the control data specifies D1 to D7, D. If the SIG signal is output and T1 to T7 are specified, T. It is designed to output a SIG signal. 21 to 27 are feed amount setting digital switches for setting feed amounts D1 to D7, respectively;
A selector 20 decodes the contents of the register 17 and enables only the outputs of the digital switches 21-27 corresponding to the feed amounts D1-D7 specified by the control data.

31 to 37 are time setting digital switches that respectively set times T1 to T7, and 30 is a circuit that decodes the contents of the register 17 and outputs only the outputs of the digital switches 31 to 37 corresponding to the times T1 to T7 specified by the control data. This is a selector to enable.

41 to 47 are feed rate setting digital switches for setting feed rates F1 to F7, respectively; 40 is the register 17;
Control by deciphering the contents. This is a selector that enables only the outputs of the digital switches 41 to 47 corresponding to the feed speeds F1 to F7 specified by the control data.

Reference numeral 50 indicates that the set values of the enabled feed speed setting digital switches 41 to 47 are loaded by inputting the timing pulse CL4 through the data bus BUS, and a feed pulse F.50 of a frequency corresponding to the loaded set value is loaded. O
SC starts to be output by inputting the BUSY signal, and BU
As soon as the SY signal is stopped, the sending pulse F. A sending pulse generating circuit 51 for stopping the output of the OSC is used when the + signal is output from the decoder 18, when the S1 signal is output from the decoder 18, and when the COUNT- signal is output from the return control counter 56, which will be described later. If it is output, the feed pulse F. When the OSC is passed as a forward feed pulse +FP and one signal is output from the decoder 18, and the decoder 18 outputs S1
If the COUNT+ signal is being output from the return control counter 56, which will be described later, then the feed pulse F. This is a pulse distribution gate circuit that passes the OSC as a backward feed pulse-FP.

52 is the T. When the SIG signal is being output, a time counting pulse TP of a predetermined constant frequency starts to be outputted by inputting the BUSY signal, and B
This is a time counting pulse generation circuit that immediately stops outputting the time counting pulse when the USY signal is stopped.

53 receives the S1 signal from the decoder 18 or the D. S.I.
When the G signal is output, the sending pulse generating circuit 50
The feed pulse output from F. This is a feed control counter input gate circuit that passes through the OSC.

Reference numeral 54 indicates setting values D1 to D7 of the enabled feed amount setting digital switches 21 to 27 or setting values T1 to T7 of the enabled time setting digital switches 31 to 37.
passes through the data bus BUS, and the timing pulse C
It is preset by the input of L4, and when the return control counter output gate circuit 57, which will be described later, is opened, the numerical value passing through this gate circuit 57 is preset by the input of the timing pulse CL4 through the data bus BUS.
These preset values are applied to the sending pulse F. which passed through the gate circuit 53. This is a feed control counter that is subtracted by the time count pulse TP output from the OSC or the time count pulse generation circuit 52, and outputs a DEN signal when the content becomes O.

55 is normally open and the pulse distribution gate circuit 5
This is a return control counter input gate recirculation gate that allows the sending pulses +FP and -FP that have passed through 1 to pass through, and is closed when the S4 signal is output from the decoder 18 to prevent the passing of the sending pulses +FP and -FP.

56 is the forward feed pulse +FP that has passed through the gate circuit 55
is added, and the backward feed pulse-FP that has passed through the gate circuit 55 is subtracted, and when the cumulative value is positive, COUNT+
A return control counter 57 outputs a COUNT signal when the accumulated value is negative, and a return control counter 57 is opened only when the S1 signal is output from the decoder and allows the counted value of the return control counter 56 to pass through. Control counter gate.

FIG. 3 shows a time chart of the aforementioned control signals.

Next, the operation of the apparatus of the above embodiment will be explained according to the program shown in Table 1 and the timing chart shown in FIG.

In the case of a normal feed control cycle, the operator turns on the outer knob command switch PBl.

As a result, from the signal level conversion circuit 4, A STARTl signal is output.

This STARTl signal causes the run flag circuit 8 to
Flip-flop 84 is set and a RUN signal is output. ) In the initial state, the J-K flip-flop 106 of the busy flag circuit 10 is reset and the BUSY signal is not output, so as soon as the RUN signal is output, a timing pulse for one cycle is generated from the shift register 72 of the timing pulse generation circuit 7. 7CL1 to CL5 are output. One control data is read out while the timing pulses CL1 to CL5 are being output. That is, S
Since the TARTl signal is being output, the program counter 11 is reset to MO by the timing pulse CLl, and the output of the STARTl signal is stopped by the timing pulse CL2, and the storage content X+D3F7 of the storage address MO of the program storage unit 3 is stored in the register 17. Read out.

As a result, the output of the feed amount setting digital switch 23 and the output of the feed rate setting digital switch 47 are enabled, and the decoder 18 outputs an X signal, a ten signal, a D.
An STG signal is output. The set value D3 of the feed amount digital switch 23 is preset in the feed control counter 54 by the timing pulse CL4, and the set value F7 (rapid feed rate) of the feed rate setting digital switch 47 is loaded into the feed pulse generation circuit 50. When the output of the timing pulses CL1 to CL5 is stopped, a feeding operation is performed next. That is, the RUN signal is output as described above, and the D. Since the STG signal is being output, the busy flag circuit 10 is activated when the output of the timing pulse CL5 is completed.
Flip-flop 106 is set and a BUSY signal is output, whereby the feed pulse generation circuit 50 generates a feed pulse F. of the frequency corresponding to the load value F7. OSC is output. Since the 10 signal is output, the feed pulse F
．． The OSC passes through the pulse distribution gate circuit 51 as a forward feed pulse +FP. This forward feed pulse +FP is input to the pulse motor drive circuit 2 to drive the pulse motor 1 forward, thereby moving the grindstone head forward at a rapid feed speed F7.
Since the S4 signal is not output, the return control counter input gate circuit 55 is open, and the forward feed pulse +
FP is also input to the return control counter 56 and added.
Ru. Also D. Since the STG signal is being output, the feed control counter input gate circuit 53 is open, and the feed pulse F. The OSC is input to the feed control counter 54 and the preset value D3 of the counter 54 is input! Subtract.

In other words, when the content of this counter 54 becomes O, the feed pulse F output from the feed pulse generation circuit 50. O.S.C.
When the number of D3 reaches D3, a DEN signal is output from the counter 54, and this DEN signal immediately resets the flip-flop 10 of the busy flag circuit 10.
Output of the SY signal is stopped. As a result, the sending pulse generation circuit 50 immediately generates the sending pulse F. Stops OSC output. The grindstone head is thus advanced by a distance D3 at a rapid feed rate F7. When the BUSY signal is no longer output, since the RUN signal has been output, the shift register 72 of the timing pulse generation circuit 7 outputs one cycle of timing pulses CL1 to CL5 again.
The control data at memory address m1 is read out and executed, and the grindstone head is advanced by distance D2 at rough grinding feed rate F1.

Similarly, when the control data M1 at memory address M2 is read out, the rest is hydraulically fed forward, and when the hydraulic forwarding is completed, the M. The FIN signal is output and the output of the BUSY signal is stopped. Note that the grindstone head is not fed during this time. When the control data at memory address M3 is read, the grindstone head moves to distance D5 at fine grinding feed speed F2.
I am forced to move forward. Control data T1 at memory address M4
When is read out, the set value T1 of the time setting circuit 31 is preset to the feed control counter 54, and the time count pulse is output from the time count pulse generation/generation circuit 52, and the preset value T1 of the feed control counter 54 is set to this time. Subtracted by counting pulse TP.

During this time, the feed control pulse F. Since the OSC is not output, the grindstone head is stopped. Thus, during the time T1, the grindstone head is stopped and spark-out grinding is performed. When the control data at the memory address M5 is read out, the rest is hydraulically moved back, and when the control data at the memory address M6 is read out, the grindstone head is moved back by a distance D4 at a rapid feed rate F7 and returns to its original position.

When the control data END at memory address M7 is read out, the flip-flop 84 of the run flag circuit 8 is reset. In this way, the execution of the normal feed control cycle program is completed.

In the case of the grindstone wear correction cycle, the operator turns on the external command switch PB2, for example, after dressing the grindstone when the normal feed control cycle is not being executed.

As a result, from the signal level conversion circuit 5, A START2 signal is output.

The START2 signal sets the flip-flop 84 of the run flag circuit 8 and outputs the RUN signal.
As a result, one cycle of timing pulses CL1 to C are output from the shift register 72 of the timing pulse generation circuit 7.
L5 is output. Further, the START2 signal causes the address gate circuit 14 to pass the output value M43 of the grindstone wear correction cycle start address setting circuit 13. Then, M43 passing through the address gate circuit 14 is loaded into the program counter 11 by the timing pulse CLl. As a result, the set value D1 of the feed amount setting digital switch 21 is set in the same manner as in the normal feed control cycle.
(D1 is preset to the amount of reduction in the grindstone caused by dressing) is preset in the feed control counter 54, and the set value F2 of the feed speed setting digital switch 42
is loaded into the feed pulse generating circuit 50, and the grindstone head is advanced by a distance D1 at a speed F2.

Note that in this case, since the S4 signal is output from the decoder 18, the gate circuit 55 is closed and the sending pulse +
FP is not input to the return control counter 56. Therefore, the return control counter 56 always stores the current position of the grindstone head, which has been corrected for wear of the grindstone. The emergency return cycle is executed by stopping any other cycles in progress.

For example, when an abnormality occurs during execution of a normal feed control cycle, an operator turns on the external command switch PB3. As a result, the signal level conversion circuit 6 outputs the ErvlB signal.

When the EMB signal is output, the flip-flop 92 of the emergency return run flag circuit 9 is set and the EMB. An SDW signal is output. EMB. The run flag circuit 8 is activated by the SDW signal. The flop 84 is reset and the RU
If the output of the M signal is stopped and an external operation is being executed and the flip-flop 106 of the flag circuit 10 is set, this EMB. The EMB.SDW signal immediately resets the output of the BUSY signal and stops the execution of external operations. The SDW signal causes the normal feed control cycle that was being executed up to that point to be aborted. On the other hand, EMB. When the SDW signal is output, the shift register 72 of the timing pulse generation circuit 7 outputs the timing pulses CLl to CL5 immediately when the timing pulses CLl to CL5 are not outputted, or when the output of the timing pulses CLl to CL5 is completed when the timing pulses CLl to CL5 are outputted. The flip-flop 94 of the emergency return run flag circuit 9 is set to EMB. CLK is output.

As a result, the flip-flop 92 is reset and the EM
B. The output of the SDW signal is stopped, and the EMB. CYC
LE signal is output. B from busy flag circuit 10
Since the output of the USY signal is stopped immediately, the EMB.
In response to the CYCLE signal, one cycle of timing pulses CL1 to CL5 is output from the shift register 72 of the timing pulse generation circuit 7. Timing pulse CLl
As a result, the output value M4l of the emergency return cycle start address setting circuit 12, which has passed through the address gate 14, is loaded into the program counter 11, and the timing pulse C
Control data X7Sl at memory address M4l is read by L2.

Furthermore, the flip-flop 97 of the emergency return run flag circuit 9 is set by the timing pulse C2, and the EMB. ST
The flip-flop 94 is reset by outputting the EMB. Output of the CLK signal is stopped. Decoder 1
Since the S1 signal is output from 8, the return control counter output gate circuit 57 is opened, and the count value of the return control counter 56, that is, the current position of the grindstone head, is preset in the feed control counter 54 by the timing pulse CL4.

Further, the setting value F7 (rapid feed rate) of the feed rate setting digital switch 41 is loaded by the timing pulse CL4. EMB. The ST signal is output and the decoder 18
Since the S1 signal is being output from CL5, the flip-flop 106 of the busy flag circuit 10 is set upon completion of outputting the timing pulse CL5.

As a result, the feed pulse generation circuit 50 outputs a feed pulse F. of the frequency corresponding to F7. OSC is output. Since the S1 signal is output from the decoder 18, when the content of the return counter 56 is positive (indicating that the grindstone head is in a position advanced relative to the origin), the pulse distribution gate circuit 51 outputs the feed pulse F. The pulse distribution gate circuit 51 outputs the forward pulse F. OS
Output C as forward pulse +FP. The pulse motor 1 is driven by the feed pulse +FP or -FP, and since the S1 signal is output from the decoder 18, the gate circuit 53 is opened and the preset value of the feed control counter 54 is set to the feed pulse F. Subtracted by OSC. When the content of the feed control counter 54 becomes O, the DEN signal is output, the flip-flop 106 of the busy flag circuit 10 is reset, the output of the BUSY signal is stopped, and the feed pulse F.
The output of the OSC is stopped. In this way, the grindstone head returns to its origin at the rapid feed rate F7. When the output of the BUSY signal is stopped, the timing pulses CL1 to CL5 are output again.

At this time, EMB. The output of the CLK signal has already been stopped, and the EMB. Since the ST signal is being output, the program counter 11 is incremented by 1 by the timing pulse CLl and becomes M42. Therefore, the control data END at the memory address M42 is read out by the timing pulse CL2, and the flip-flop 97 of the emergency return run flag circuit 9 is reset. In this way, the execution of the emergency return cycle program is completed.

As is clear from the above explanation, in the present invention, the feed rate and feed rate as machining conditions can be freely changed by changing the settings of the digital switch, and can be easily changed by changing the control data stored in the program storage unit as a diode matrix. You can change the cycle to

Therefore, it is extremely practical in program control of grinding processing, and it is also easily applicable to different types of grinding machines with different cycles, so it is versatile and has the advantage of being extremely flexible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
An electric circuit diagram showing specific examples of blocks 7 to 10 in the figure, and FIG. 3 is a time chart of control signals. DESCRIPTION OF SYMBOLS 1... Pulse motor, 2... Pulse motor drive circuit, 3... Program storage section, 4-6... Signal level conversion circuit, 7... Timing pulse generation circuit, 8...
・Run flag circuit, 9...Non-return run flag circuit, 1
0...Busy flag circuit, 11...Program counter, 12...Emergency return cycle start address setting circuit, 21-27...Feed amount setting digital switch, 4
1 to 47...Feed rate setting digital switch, 50.
... Feed pulse generation circuit, 51... Pulse distribution gate circuit, 54... Feed control counter, 56... Return control counter, PBl to PB3... External command switch.

Claims (1)

[Claims] 1. A plurality of feed rate setting digital switches for setting the incremental feed amount for each feed stage of the moving body, and a plurality of feed rate setting digital switches for setting the moving speed of the moving body;
A selector circuit for selecting and activating one of the feed amount setting digital switch and the feed rate setting digital switch, and control data to be applied to this selector circuit are programmably stored in each memory address that can be switched for each feed stage. a program storage section consisting of a diode matrix circuit; a program counter that specifies the storage address of the control data stored in the program storage section and sequentially reads out the control data corresponding to each feeding stage; A feed pulse generation circuit that receives the setting value of the feed speed setting digital switch and outputs a feed pulse with a frequency corresponding to the input setting value, and a pulse that drives a pulse motor for controlling a moving object using this feed pulse. The setting value of the motor drive circuit and the feed rate setting digital switch selected by the control data is preset, and this preset value is subtracted by the feed pulse output from the feed pulse generation circuit, and when the content becomes 0, a feed stop signal is issued. A programmable feed control device comprising: a feed control counter that outputs an output; and a control circuit that stops the feed pulse output from the feed pulse generation circuit in response to the feed stop signal and increments the program counter. .