JPS604321A - Variable gain amplifier - Google Patents

Variable gain amplifier

Info

Publication number
JPS604321A
JPS604321A JP11321383A JP11321383A JPS604321A JP S604321 A JPS604321 A JP S604321A JP 11321383 A JP11321383 A JP 11321383A JP 11321383 A JP11321383 A JP 11321383A JP S604321 A JPS604321 A JP S604321A
Authority
JP
Japan
Prior art keywords
circuit
variable gain
gain amplifier
terminal
input level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11321383A
Other languages
Japanese (ja)
Inventor
Isao Nakazawa
中沢 勇夫
Hideki Kiyono
清野 秀木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11321383A priority Critical patent/JPS604321A/en
Publication of JPS604321A publication Critical patent/JPS604321A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3036Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Filters And Equalizers (AREA)

Abstract

PURPOSE:To obtain a broad band variable gain amplifier applicable to a high- quality radio equipment by providing an amplitude changing circuit in the preceding stage of a variable gain amplifying circuit. CONSTITUTION:The gain of a variable gain amplifying circuit V-AMP is controlled by an automatic gain control circuit AGC-CON so that the output level of a terminal 5 is constant approximately even if the input level applied to a terminal 3 is changed by, for example, about 50dB, and the input level applied to the terminal 3 is monitored by an input level detecting circuit DET. Outputs of the automatic gain amplifying circuit AGC-CON and the input level detecting circuit DET are inputted to a driving circuit DRV, and the driving circuit is so operated that the frequency characteristic of a variable gain amplifying circuit V-AMP is compensated by the amplitude characteristic of an amplitude equalizing circuit AE and is made flat as the whole, and this frequency characteristic is applied to the amplitude equalizing circuit AE to improve the frequency characteristic as the whole.

Description

【発明の詳細な説明】 (81発明の技術分野 本発明は可変利(q増幅器に係り、特に高品質を要求さ
れる無線装置に使用される可変利得増幅器に関するもの
で−ある。
DETAILED DESCRIPTION OF THE INVENTION (81) Technical Field of the Invention The present invention relates to a variable gain (q) amplifier, and particularly to a variable gain amplifier used in radio equipment requiring high quality.

(bl 従来技術と問題点 音声1画像及びその他の情報をアナログ量のまま送るア
ナログ無線方式と、ディジタル化してディジタル無線方
式の両方が用いられているが、年年送るべき情11Jf
が多くなっている。これに伴い無線機に要求される規格
はより厳しくなっている。
(bl Conventional technology and problems) Both analog wireless systems that send images and other information in analog quantities, and digital wireless systems that digitize information, are used.
are increasing. Along with this, the standards required for radio equipment are becoming more stringent.

例えば、可変利得の中間周波増幅器に対しては入カレヘ
ルが50〜60db変’t)Jシても70±15MII
z又は140±25M1lzの範囲で周波数特性は平坦
でなければならない、と云うことが要求される場合があ
る。
For example, for a variable gain intermediate frequency amplifier, the input voltage may vary by 50 to 60 db.
In some cases, it may be required that the frequency characteristic must be flat in the range z or 140±25M1lz.

第1図は従来の可変利得増幅回路の動作を説明するため
の図である。
FIG. 1 is a diagram for explaining the operation of a conventional variable gain amplifier circuit.

同図に於いて、端子1に加えられた中間周波信号は増幅
器耐IP−1で増幅された後ダイオードD1及びD2が
直列接続された回路を通過し、再び増幅器AMP−2で
増幅された後、端子2から外部に取り出される。ここで
ダイオードD1及びD2の抵抗分は、駆動電圧v1が太
き(なる程大きなダイオード電流が流れるので、各ダイ
オードの抵抗分が少なくなり、逆に駆動電圧v1が小さ
くなる程ダイオードの抵抗分が大きくなる。そして増幅
器AMP −1から増幅器へMP −2へ加えられる電
流iは略v/ rdl ” rdlで与えられる。ここ
でVは増幅X::AMP −1の出力電圧で−+ + 
rd2はぞれぞれダイオードD1及びD2の抵抗骨であ
る。この式から分かるようにダイオードの抵抗骨を変え
る事に依り、増幅器へMP −2に加えられる電流の大
きざが変わる。そこで、増幅器/IMP −1及びAM
P−2自身の利得は帰還抵抗R1+R2の値に依って決
められているが、駆動電圧v1を変化さ・Uることによ
り増幅器AMP −2への入力電流を変えることが出来
るのでAMP −1及びAMll −2で構成された増
幅器の利得を制御することが出来る。
In the figure, the intermediate frequency signal applied to terminal 1 is amplified by amplifier IP-1, passes through a circuit in which diodes D1 and D2 are connected in series, and is amplified again by amplifier AMP-2. , taken out from terminal 2. Here, the resistance of the diodes D1 and D2 is determined by the fact that the drive voltage v1 is large (as a large diode current flows, so the resistance of each diode decreases, and conversely, the smaller the drive voltage v1 is, the greater the resistance of the diode becomes. The current i applied from amplifier AMP-1 to amplifier MP-2 is approximately given by v/rdl''rdl, where V is the output voltage of amplifier X::AMP-1.
rd2 are resistance bones of diodes D1 and D2, respectively. As can be seen from this equation, by changing the resistance of the diode, the magnitude of the current applied to MP-2 to the amplifier changes. Therefore, amplifier/IMP-1 and AM
The gain of P-2 itself is determined by the value of the feedback resistor R1 + R2, but by changing the drive voltage v1, the input current to the amplifier AMP-2 can be changed. The gain of the amplifier configured with AMll-2 can be controlled.

第2図は第1図で説明したjiL来の可変利得増幅回路
の周波数対出力特性を示す。
FIG. 2 shows the frequency versus output characteristics of the variable gain amplifier circuit introduced in jiL as explained in FIG.

図中■は可変利得増幅回路への入力レベルが高い場合で
可変利得増幅回路の利得は小さくなっている。■は標準
入力レベルの場合、■ば入力レベルが低い場合で可変利
得増幅回路の利得は大きくなっている。
In the figure, ■ indicates a case where the input level to the variable gain amplifier circuit is high, and the gain of the variable gain amplifier circuit is small. (2) is when the input level is standard, and (2) is when the input level is low, and the gain of the variable gain amplifier circuit is large.

この図から判るように、可変利得増幅回路の利得が大き
(なる程周波数特性の高い方の成分が低下し、逆に低い
方の成分が上昇してイル。
As you can see from this figure, the gain of the variable gain amplifier circuit is large (as you can see, the higher frequency response components decrease, while the lower frequency components increase).

これは可変利得増幅回路の利得を大きくする為に増幅器
を構成するトランジスタの周波数特性がそのまま現れた
ため、又はダイオード’DI、D2の抵抗骨を変えるこ
とに依り浮遊容量の影響が顕著となるためである。これ
を補償するための回路も考案されているが必ずしも充分
な効果が得られず、又パリオロソザーを用いた可変利得
増幅回路は回路規模が大きくなり小型化出来ない欠点が
ある等の問題があった。
This is because the frequency characteristics of the transistors that make up the amplifier appear as they are in order to increase the gain of the variable gain amplifier circuit, or because the influence of stray capacitance becomes noticeable by changing the resistance bones of diodes 'DI and D2. be. Circuits have been devised to compensate for this, but they are not always sufficiently effective, and variable gain amplification circuits using pariorososers have problems such as the circuit scale becoming large and not being able to be miniaturized. .

(C1発明の目的 本発明は前記従来技術の問題に鑑みなされたものであっ
て、高品質な無線装置に用いるための広帯域な可変利得
増幅器を提供することを目的としている。
(C1 Object of the Invention The present invention has been made in view of the problems of the prior art described above, and an object of the present invention is to provide a wideband variable gain amplifier for use in high-quality radio equipment.

(dl 発明の構成 前記発明の目的は中間周波信号を増幅する可変利得増幅
回路、該可変利得増幅回路の出力信号を用いて該可変利
得増幅回路の利得を制御する自動利得制御回路iび該可
変利得増幅回路に加えられる入力信号レベルを検出する
入力レベル検出回路から構成される可変利得増幅部に於
いて、該可変利得増幅回路の前段に該自動利1u制御回
路及び該入力レベル検出回路の出力信号を合成する駆動
回路によって制御される振幅等化回路を設けたことを特
徴とする可変利得増幅器を提供することに依り達成され
る。
(dl Structure of the Invention The object of the invention is to provide a variable gain amplifier circuit for amplifying an intermediate frequency signal, an automatic gain control circuit for controlling the gain of the variable gain amplifier circuit using an output signal of the variable gain amplifier circuit, and a variable gain amplifier circuit for controlling the gain of the variable gain amplifier circuit using an output signal of the variable gain amplifier circuit. In a variable gain amplification section consisting of an input level detection circuit that detects the level of an input signal applied to a gain amplification circuit, the automatic gain 1u control circuit and the output of the input level detection circuit are connected at a stage before the variable gain amplification circuit. This is achieved by providing a variable gain amplifier characterized in that it is provided with an amplitude equalization circuit that is controlled by a drive circuit that combines signals.

tel 発明の実施例 第3図は本発明の一実施例のブロック図である。tel Embodiments of the invention FIG. 3 is a block diagram of one embodiment of the present invention.

図中、AEは振幅等化回路、V−AMPは可変利得増幅
器回路、 AGC−CONは自動利1M制御回路、 I
IETは入力レベル検出回路、 DRVは駆動回路、3
〜7はそれぞれ、l、1.11子を示す。
In the figure, AE is an amplitude equalization circuit, V-AMP is a variable gain amplifier circuit, AGC-CON is an automatic gain 1M control circuit, and I
IET is input level detection circuit, DRV is drive circuit, 3
~7 indicate l, 1.11 children, respectively.

これらの各ブロックは次のように接続されている。Each of these blocks is connected as follows.

振幅等化回路AIEの(1)の入力端子は!111子3
と。
The (1) input terminal of the amplitude equalization circuit AIE is! 111 children 3
and.

出力端子は可変利得増幅回路V−A肝を介して端子5に
それぞれ接続される。又自動利得制御回路AGC−CO
Nの入力端子は端子5と、(1)の出力端子ぼ可変利得
増幅回路V−AMPの(2)の入力端子に、(2)の出
力端子は駆動回路DIIVの端子6に、入力レベル検出
回路DETの入力端子は可変利得増幅回路V −AMP
の(2)の出力端子と、出力端子は駆動回路DRVの端
子7と、駆動回路DRVの(1)及び(2)の出力端子
は振幅等化回路AIEの(2)及び(3)の入力端子に
それぞれ接続される。
The output terminals are respectively connected to the terminal 5 via the variable gain amplifier circuit V-A. Also automatic gain control circuit AGC-CO
The input terminal of N is connected to terminal 5, the output terminal of (1) is connected to input terminal (2) of variable gain amplifier circuit V-AMP, and the output terminal of (2) is connected to terminal 6 of drive circuit DIIV. The input terminal of the circuit DET is the variable gain amplifier circuit V-AMP.
The output terminal (2) of the output terminal is the terminal 7 of the drive circuit DRV, and the output terminals (1) and (2) of the drive circuit DRV are the input terminals (2) and (3) of the amplitude equalization circuit AIE. connected to the respective terminals.

尚、本発明の部分は点線で囲った部分である。Note that the portion of the present invention is surrounded by a dotted line.

このように接続された各ブロックの動作は次のようであ
る。
The operation of each block connected in this way is as follows.

端子3に加えられた中間周波信号は振幅等化回路AIE
及び可変利得増幅回路V−八Ml+を経由して端子5か
ら外部に暇り出される。この時端子3に加えられる入力
■/ヘルが、例えば50dh位変化しても端子5には略
一定の出力レベルになるように自動利得制御回路AGC
−CONで可変利得増幅回路V −AMPの利j[)を
制御すると共に、入力レベル検出回路DIETで端子3
に加えられた入力レベルを監視する。
The intermediate frequency signal applied to terminal 3 is passed through the amplitude equalization circuit AIE.
And it is outputted to the outside from terminal 5 via variable gain amplifier circuit V-8Ml+. At this time, even if the input ■/her applied to terminal 3 changes by, for example, 50 dh, the automatic gain control circuit AGC is configured to maintain a substantially constant output level at terminal 5.
-CON controls the gain j[) of variable gain amplifier circuit V -AMP, and input level detection circuit DIET controls terminal 3.
monitor the input level applied to the

この場合、可変利j11増幅回路V −AMpの利得に
対する周波数特性は前記のように利得が高くなる程高い
周波数成分が低下するので、これを補償して平坦な特性
にするのが点線で囲った部分で、自動利得増幅回路AG
C−CON及び入力レベル検出回路DIETの出力を駆
動回路DRVに入れて振幅等化回路AEの振幅特性が前
記可変利得増幅回路シーへ肝の周波数特性を補償して全
体として平坦になるような駆動回路出力を作り、これを
振幅等化回路AIEに加える。
In this case, the frequency characteristics of the variable gain j11 amplifier circuit V-AMp with respect to the gain are such that the higher the gain, the lower the high frequency components are, as described above, so the way to compensate for this and make the characteristics flat is as shown in the dotted line. In part, automatic gain amplification circuit AG
The outputs of C-CON and the input level detection circuit DIET are input to the drive circuit DRV, and the amplitude characteristics of the amplitude equalization circuit AE are driven to the variable gain amplifier circuit C so that the amplitude characteristics of the amplitude equalization circuit AE are flattened as a whole by compensating for the main frequency characteristics. Create a circuit output and apply it to the amplitude equalization circuit AIE.

第4図は第3図に示したブ1−17り図の点線で囲った
部分のより具体的な動作説明図である。
FIG. 4 is a more detailed diagram illustrating the operation of the portion surrounded by dotted lines in the block diagram 1-17 shown in FIG.

同図に於て、八Eは振幅等化回路、 DREは駆動回路
を、3,4,6.7はそれぞれ端子を示し第3図と同一
の記号を用いている。
In the figure, 8E indicates an amplitude equalization circuit, DRE indicates a drive circuit, and 3, 4, and 6.7 indicate terminals, using the same symbols as in FIG. 3.

これらの各部分は次のように接続されている。These parts are connected as follows.

振幅等化回路AEはビン・ダイオードD2とバラクタダ
イオードD3の並列接続されたものが端子3と端子4の
間に挿入され、ビン・ダイオードD2は増幅器へMP 
−3及びAMP−4で、バラクタダイオ−1”D。
In the amplitude equalization circuit AE, a parallel connection of a bin diode D2 and a varactor diode D3 is inserted between terminals 3 and 4, and the bin diode D2 is connected to the amplifier MP.
-3 and AMP-4, varactor diode-1"D.

は増幅器AMP ’−5及#AMp −6でそれぞれ駆
動される。
are driven by amplifiers AMP'-5 and #AMp-6, respectively.

そして増幅器へMP −3とAMI’−5は共に端子6
及び7から自動利得制御電圧八GC−CON及び入力レ
ベル検出回路DETの出力信号が加えられる。
Then, both MP-3 and AMI'-5 are connected to terminal 6 to the amplifier.
and 7 to the automatic gain control voltage 8GC-CON and the output signal of the input level detection circuit DET.

この回路の機能は、前記のように振幅等化回路Anの周
波数特性で可変利得増幅回路V −A肝の周波数特性を
補償する為のもので、この振幅等化回路AEを駆動する
駆動部DRVの動作点の設定は次のような手順でこれを
行っている。
The function of this circuit is to compensate the frequency characteristics of the variable gain amplifier circuit V-A with the frequency characteristics of the amplitude equalization circuit An, as described above, and the drive unit DRV that drives this amplitude equalization circuit AE. The operating point of is set using the following steps.

1、可変利得増幅回路V −AMPの周波数特性を測定
して補償すべき量を決定する(第2図参照)。
1. Measure the frequency characteristics of the variable gain amplifier circuit V-AMP to determine the amount to be compensated (see Figure 2).

2、?iti償ずべき周波数特性を実現する為ビン・ダ
イオードD2を抵抗に、バラクタダイオードD3を容量
に置き換え、これらの並列回路の周波数特性が第1項の
補償すべき周波数特性と略一致するようなそれぞれの値
を決定するく第5図(al参照)。
2.? In order to realize the frequency characteristics to be compensated for, the bin diode D2 is replaced with a resistor, and the varactor diode D3 is replaced by a capacitor, and the frequency characteristics of these parallel circuits are set so that they approximately match the frequency characteristics to be compensated for in the first term. Figure 5 (see al) to determine the value of.

3、ビン・ダイオードD2及びバラクタダイオードDP
抵抗分及び容量分が、第2項で定められた値になるよう
な駆動電圧及び駆動電流をそれぞれの素子の特性曲線か
らめる(第5図(bl参照)。
3. Vin diode D2 and varactor diode DP
The drive voltage and drive current are determined from the characteristic curve of each element so that the resistance and capacitance become the values determined in the second term (see FIG. 5 (bl)).

4、第3項に示した駆動電圧及び駆動電流になるように
、第5図fc)に示ず入カレヘル検出電圧及び自動利得
制御電圧の曲線を組み合わせる(第5図tel参照)。
4. Combine the curves of the input voltage detection voltage and the automatic gain control voltage (see tel in FIG. 5), not shown in FIG.

5、第4項の制御曲線に一致するように第4図に示した
可変抵抗器Rシー1〜Rv −(iの値を設定するが、
最終的には可変利得増幅回路V −AMPの周波数特性
を直視しながら前記可変Il(抗器Rシー1〜Rシー6
の値を?!i、MI!II整する。
5. Set the values of the variable resistors Rc1 to Rv-(i) shown in FIG. 4 to match the control curve in Section 4.
Finally, while directly observing the frequency characteristics of the variable gain amplifier circuit V-AMP,
the value of? ! i, MI! II Adjust.

以上のような調整に依り、可変利得増幅回路VA、MI
+の利i!lに関係なく必要な全周波数帯域に渡り平坦
な特性が得られる。
Through the above adjustments, the variable gain amplifier circuits VA, MI
+ profit i! Flat characteristics can be obtained over the entire necessary frequency band regardless of l.

第6図は本発明の別の一実施例でビン・ダイオ−1’D
2及びバラクタダイオ−1−D3の接続を第6図fat
の場合は直列接続に、第〔1図(t))は第6図(al
と同しく直列接続であるがバラクタダイオードr13の
0を低下させ、より広帯域化を図るために抵抗I?5が
バラクタダイオ−1・D3に並列接続されている。
FIG. 6 shows another embodiment of the present invention.
2 and varactor diode-1-D3 connection in Figure 6 fat
In the case of series connection, Figure 1 (t) is connected in series, Figure 1 (t) is connected in series, Figure 6 (al
The resistor I? is also connected in series, but in order to lower the 0 value of the varactor diode r13 and achieve a wider band, the resistor I? 5 are connected in parallel to the varactor diodes 1 and D3.

この伯にも可変抵抗素子及び可変容量素子を直列及び並
列に構出することに依り任意の周波数特性を持つ回路を
構成することが出来る。
Also in this case, by arranging variable resistance elements and variable capacitance elements in series and in parallel, a circuit having arbitrary frequency characteristics can be constructed.

第7図は本発明の別の一実hi!i例で駆動回路DVI
?の構成が第4図と異なっている。
Figure 7 shows another example of the present invention! In example i, drive circuit DVI
? The configuration is different from that in FIG.

第7(a)の場合は可変抵抗器が端子7と増幅器AMP
〜7及びAMP−9との間に、増幅器AMP −7と八
MP −8及びAMP −9とAMP−10との間にそ
れぞれ挿入されている。
In the case of No. 7 (a), the variable resistor is connected to the terminal 7 and the amplifier AMP.
-7 and AMP-9, amplifiers AMP-7 and 8 are inserted between MP-8, and amplifiers AMP-9 and AMP-10, respectively.

第7図(blの場合は可変抵抗器が端子6と増幅器へM
P−11及び八MP−13との間に、増幅器へMP −
11の出力側と入力端子(1)及びAMP−13の出力
側と入力醋1了(1)との間にそれぞれ挿入され′(い
る。
Figure 7 (In the case of bl, the variable resistor is connected to terminal 6 and the amplifier M
Between P-11 and eight MP-13, MP- to amplifier
They are inserted between the output side of AMP-11 and the input terminal (1), and between the output side of AMP-13 and the input terminal (1), respectively.

しかし、機能的には第4図と同じである。However, it is functionally the same as in FIG.

(fl 発明の詳細 な説明したように、本発明によればビン・ダイオード及
びバラクタダイオードを用いて振幅等化回路を構成し、
自動利得制御回路及び入力レベル検出回路の出力電圧を
適当に合成して得られた駆動電圧で、前記振幅等化回路
を駆動することに依り可変利得増幅回路の周波数特性を
補償することが出来る。そこで従来の可変利得増幅回路
に本発明の回路を付加することに依り高品質の無線装置
に使用することが出来る。
(fl As described in detail, according to the present invention, an amplitude equalization circuit is constructed using a bin diode and a varactor diode,
The frequency characteristics of the variable gain amplifier circuit can be compensated by driving the amplitude equalization circuit with a drive voltage obtained by suitably combining the output voltages of the automatic gain control circuit and the input level detection circuit. Therefore, by adding the circuit of the present invention to the conventional variable gain amplifier circuit, it can be used in high quality radio equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の可変利得増幅回路の動作を説明する為の
図、第2図は第1図に示した回路の周波数対出力特性を
示す図、第3図は本発明の一実施例を示すブロック図、
第4図は本発明の一実施例のより具体的な回路図、第5
図(a)、 (bl、 (C1は本発明の一実施例に含
まれる駆動回路の動作点設定を説明するための図、第6
図本発明の別の一実施例第7図は本発明の別の一実施例
をそれぞれ示す。 図中、八[ば振゛幅等化回路、■−へMPは可変利得増
幅回路AGC−CONは自動利得制御回路、 DIIV
は駆動回路を、叶Tは入カレヘル検出回路、D、はビン
・ダイオード、D=はバラクタダイオード、へMP−3
〜八MP−14は増幅器、I?、〜R5は抵抗、1〜7
は端子をそれぞれ示す。 煕I阻 一咋1に4( 賓3吋 #4−閉 へ万しヘル1大 人力レヘ+し→〆
Fig. 1 is a diagram for explaining the operation of a conventional variable gain amplifier circuit, Fig. 2 is a diagram showing the frequency vs. output characteristic of the circuit shown in Fig. 1, and Fig. 3 is a diagram for explaining an embodiment of the present invention. Block diagram shown,
FIG. 4 is a more specific circuit diagram of one embodiment of the present invention, and FIG.
Figures (a), (bl, (C1 is a diagram for explaining the operating point setting of the drive circuit included in one embodiment of the present invention, the sixth figure is
Figures Another Embodiment of the Invention FIG. 7 shows another embodiment of the invention. In the figure, 8 [amplitude equalization circuit] - MP is a variable gain amplifier circuit AGC-CON is an automatic gain control circuit, DIIV
is the drive circuit, T is the input voltage detection circuit, D is the bin diode, D= is the varactor diode, to MP-3
~8 MP-14 is an amplifier, I? , ~R5 is the resistance, 1 to 7
indicate the respective terminals.煕I block 1 to 4 (guest 3 后#4-to close, 1 adult power rehe+shi→〆

Claims (1)

【特許請求の範囲】[Claims] 中間周波信号を増幅する可変利得増幅回路、該可変利得
増幅回路の出力信号を用いて該可変利得増幅回路の利得
を制御する自動利得制御回路及び該可変利得増幅回路に
加えられる入力信号レベルを検出する入力レベル検出回
路から構成される可変利得増幅部に於いて、該可変利得
増幅回路の前段に該自動利得制御回路及び該入カレヘ1
1・検出回路の出力信号を合成する駆動回路によって制
御される振幅等化回路を設けたことを特徴とする可変利
得増幅器。
A variable gain amplifier circuit that amplifies an intermediate frequency signal, an automatic gain control circuit that controls the gain of the variable gain amplifier circuit using an output signal of the variable gain amplifier circuit, and detects the level of an input signal applied to the variable gain amplifier circuit. In a variable gain amplification section consisting of an input level detection circuit, the automatic gain control circuit and the input port 1 are provided before the variable gain amplification circuit.
1. A variable gain amplifier characterized by being provided with an amplitude equalization circuit controlled by a drive circuit that synthesizes the output signals of the detection circuit.
JP11321383A 1983-06-23 1983-06-23 Variable gain amplifier Pending JPS604321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11321383A JPS604321A (en) 1983-06-23 1983-06-23 Variable gain amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11321383A JPS604321A (en) 1983-06-23 1983-06-23 Variable gain amplifier

Publications (1)

Publication Number Publication Date
JPS604321A true JPS604321A (en) 1985-01-10

Family

ID=14606428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11321383A Pending JPS604321A (en) 1983-06-23 1983-06-23 Variable gain amplifier

Country Status (1)

Country Link
JP (1) JPS604321A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02172309A (en) * 1988-12-26 1990-07-03 Mitsubishi Electric Corp Power amplifier
JPH04128456A (en) * 1990-09-19 1992-04-28 Misawa Homes Co Ltd Formation of roof panel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02172309A (en) * 1988-12-26 1990-07-03 Mitsubishi Electric Corp Power amplifier
JPH04128456A (en) * 1990-09-19 1992-04-28 Misawa Homes Co Ltd Formation of roof panel

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