JPS6043034B2 - Manufacturing method of switching element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a switching element such as a power transistor, thyristor, or gate turn-off thyristor (hereinafter referred to as GTO).

Generally power transistor, thyristor or GTO
Switching elements such as
Reduction of heat loss is required.

In particular, switching elements for electric power such as Δ41, Φclaw-f, 111--0, , , are required to have high current and high withstand voltage in addition to the above-mentioned performance in order to miniaturize the device and increase capacity. is required. These performances are often determined by the internal configuration of the element, and there is a trade-off relationship between these performances. For example, to increase the withstand voltage, it is necessary to widen the width of the intermediate layer that serves as the base layer, but widening the width increases the on-state voltage, which increases heat loss, and further increases the volume of the intermediate layer, which causes the switch to turn off. There is a trade-off relationship between the performances, such that it takes time for excess carriers to disappear and the switching operation becomes slow. In practice, therefore, when obtaining a switching element with a low power consumption, the trade-off point between each characteristic is optimized depending on the application.
There are some parameters of the current control device that are not in a trade-off relationship; for example, the higher the minority carrier lifetime in the semiconductor layer containing the control electrode, the higher the current increase rate of the transistor based on this layer. The switching performance is improved, the on-voltage is lowered, and the leakage current is also reduced, so that the device performance is almost improved.

Therefore, in a switching element, it is generally desirable to make the carrier lifetime of a semiconductor substrate as high as possible before diffusing lifetime killer atoms, such as gold (Au) atoms. However, in the actual manufacturing process, in order to introduce impurities into the semiconductor substrate, 100σC
When the above-mentioned high-temperature heat treatment is performed, carrier trap levels are created due to heavy metals mixed in from the container during the heat treatment and thermal strain generated in the semiconductor substrate due to the heat treatment, reducing the carrier lifetime. .

This phenomenon, unlike intentional lifetime control such as the diffusion of lifetime killer atoms, has been a major cause of deterioration of device performance and reproducibility of device manufacturing. The Ringetter method is well known as one of the solutions to this problem.

This is because when a phosphorus compound is formed (deposited) on a semiconductor substrate and the phosphorus of the phosphorus compound is diffused into the semiconductor substrate, Fe, . This method takes advantage of the effect that heavy metals such as Cu are diffused by heat and adsorbed to the phosphorus compound layer on the semiconductor substrate, resulting in a decrease in the amount of heavy metals in the semiconductor substrate and an increase in lifetime.
A method using this Ringetter effect will be specifically explained with reference to FIGS. 1a to 1d. What is shown in FIGS. 1A to 1D is an example of the manufacturing process of a thyristor, which is one of the switching elements. First, a p-type layer 12 that will become an anode layer by diffusing, for example, Ga from both sides of an n-type Si substrate 11 and a p-type layer 13 that will later become a p-base layer on which a gate electrode will be formed are formed.
A Si substrate having a -np structure is obtained (FIG. 1a). Then p
A phosphorus glass layer 14 is formed (deposited) on the p-type layer 13 which becomes the base layer (FIG. 1b). When this phosphorus glass layer 14 is formed, heavy metals contained in the Sj substrate and heavy metals present outside are adsorbed to the phosphorus glass layer 14. Thereafter, the phosphorus glass layer 14 is removed, and the phosphorus contained near the surface of the S1 substrate 11 is diffused to form an n-type layer 15 that will become a cathode layer (first
Figure c). Note that the reason why phosphorus is diffused after removing the phosphorus glass layer 14 in this step is to control the surface concentration and depth of the n-type layer that will become the cathode layer. Thereafter, lifetime killer atoms (indicated by dots in the figure) are diffused from the side of the p-type layer 12, which will become the anode layer (FIG. 1d). Finally, although not shown, an anode electrode is formed on the p-type layer 12 that becomes the anode layer, a gate electrode is formed on the p-type layer 13 that becomes the p-base layer, and a cathode electrode is formed on the n-type layer 15 that becomes the cathode layer to form a thyristor element. is obtained. Since the thyristor element thus obtained utilizes the Ringetter effect, the amount of heavy metals in the Si substrate is reduced and the lifetime is improved.

However, the improvement in lifetime is only slight, and as a result, it is almost the same as a thyristor using a method that does not utilize the Ringetter effect. A possible reason for this is that because the phosphorus glass layer 14 is not formed when phosphorus is diffused, the heavy metals that have been sucked into the vicinity of the surface of the Si substrate 11 are re-diffused during the phosphorus diffusion, and the It's for invading. As described above, there was a fatal flaw in the manufacturing process in that while the lifetime was once increased during the formation (deposition) of the phosphorus glass layer, the carrier lifetime was lowered during the diffusion of phosphorus. The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a method for manufacturing a switching element that increases carrier lifetime and improves switching characteristics.

That is, the present invention diffuses phosphorus (n-type impurity) into a semiconductor substrate to form an n-type layer (emitter layer), and then forms a layer containing phosphorus on the semiconductor substrate again to reduce the n-type layer formation temperature. In this method, ring etching is performed at a temperature of 700° C. to 1100° C., which is lower and higher than the Au diffusion temperature, thereby improving the lifetime of the semiconductor substrate again.

An embodiment of the present invention will be described below with reference to the drawings.

2A to 2E are cross-sectional views showing the manufacturing process of a thyristor according to an embodiment of the present invention, corresponding to FIG.
The process from a to c in FIG. 2 is the same as a to c in FIG. is formed to form a p-type layer 13 which becomes a p-base layer.
[S] Structure of the substrate is obtained (Fig. 2a). Next, a phosphorus glass layer 14 is formed (deposited) on the p-type layer 13 which will become the p-base layer (FIG. 2b). At this time, the p-type layer 12 side, which normally becomes an anode layer, is covered with a SiO2 film or the like, although not shown. When forming the phosphor glass layer 14, the heavy metals contained in the Sl substrate and the heavy metals present on the outside are removed from the phosphor glass layer 14.
Adsorb to 4. Therefore, in this step, the lifetime of the Si substrate, especially the p-type layer which becomes the p-base layer, is improved several tens of times as will be explained later. After that, the phosphor glass layer 14 is removed and the Si
Phosphorus contained in the substrate ↓± is diffused at a temperature of about 1200° C. for about 5 hours to form an n-type layer 15 that will become a cathode layer (FIG. 2c). In this step of diffusing phosphorus, the heavy metals that have been attracted near the surface of the Si substrate as described in the conventional example are re-diffused into the Si substrate, and the Si substrate, especially the p-type layer 1 which becomes the p base layer.
The lifetime of 3 decreases and returns to its original value, as will be explained later (FIG. 3). The process up to this point is the same as the conventional method, that is, the method shown in FIG. The following step is an important step of the present invention. That is, after phosphorus is diffused into the p-type layer 13 of the Si substrate, which becomes the so-called p-base layer, a phosphorus glass layer 26 is again formed (deposited) on the surface thereof (FIG. 2d). When the phosphorus glass layer 26 is formed again in this manner, the lifetime, which had been lowered during the phosphorus diffusion process, is improved again, and as will be explained later (FIG. 3), the lifetime is improved by several tens of times after immediately after the phosphorus diffusion.
After that, similar to the process shown in FIG. 1d, Au atoms (
(shown as dots in the figure). This Au atom diffusion step is carried out at a temperature of 850° C., but since the temperature is lower and the time is shorter than that of phosphorus diffusion, there is little re-diffusion of heavy metals.
Furthermore, it is not necessarily necessary to remove the phosphor glass layer 26 during this Au atom diffusion step. The reason for this is that, as explained above, the diffusion of Au atoms is lower and for a shorter time than the temperature during phosphorus diffusion, so phosphorus re-diffusion does not occur, and the initial impurity (phosphorus) concentration is maintained at a deep level. This is because there is almost no change. Finally, although not shown, as in the conventional example, an anode electrode is formed on the p-type layer 12 that becomes the anode layer, a gate electrode is formed on the p-type layer 13 that becomes the p-base layer, and a cathode electrode is formed on the n-type layer 15 that becomes the cathode layer. A thyristor element is obtained. The thyristor element obtained in this way has a longer lifetime of the Si substrate, especially the p-type layer serving as the p-base layer, and has better switching performance than the conventional thyristor element obtained as shown in FIGS. 1a to 1d. It comes to have characteristics.

Next, the Si of the thyristor element obtained as in the above example is
The lifetime of the p-type layer 13, which becomes the substrate, that is, the p-base layer, is more specific than the lifetime of the p-type layer 13, which becomes the p-base layer of the conventional thyristor element, that is, obtained as shown in FIGS. The degree to which this is good will be explained with reference to FIG.

This FIG. 3 shows the n base layer of the thyristor element for a'' to d'' and a'' to e'''' corresponding to conventional FIG. 1 a to d and FIG. 2 a to e of an embodiment of the present invention. This is a curve diagram showing the lifetime (μSec.) of the n-type layer 11, where the dotted line is for the conventional case and the solid line is for the embodiment of the present invention. As is clear from FIG. 3, in the conventional case, the lifetime of the n-type layer, which is the n-base layer of the Si substrate, is 0.6 to 1.1μ.
Sec. On the other hand, in the case of one embodiment of the present invention, the lifetime of the n-type layer is 1.1 to 1.3 psec. It was at that rank.
That is, in the conventional case, the target value of 1.2μSec. There were many things that I had never seen before, and there was wide variation. On the other hand, in the case of one embodiment of the present invention, the target value was almost achieved and there was little variation. The reason why the lifetime almost reached the target value and had little variation (good reproducibility) is that the phosphorus glass layer 26 was formed (deposited) again after the phosphorus was diffused as mentioned above. It is for the sake of being there. That is, after diffusing phosphorus, the phosphorus glass layer 2
6, the heavy metals re-diffused into the Si substrate and the external heavy metals are returned to the phosphor glass layer 2.
This is because the amount of heavy metals in the Si substrate immediately after phosphorus is diffused decreases even if gold is adsorbed to Si substrate 6 and then subjected to gold diffusion at a temperature of about 850° C. immediately after phosphorus is diffused. Note that the lifetime measurement in FIG. 3 was carried out by the diode voltage drop method, and what is shown in FIG. 3 is the change in lifetime when a heat treatment process is performed at 700° C. or higher. In this way, the lifetime of the n-type layer that becomes the n-base layer is almost the target value, but unfortunately there is currently no means to directly measure the lifetime of the p-type layer 13 that becomes the p-base layer.
This can be fully understood by calculating the lifetime of the mold layer or by analogy with the device characteristics. The lifetime, τN8, which is a function of depth in a commonly used calculation formula, is n
The lifetime of the type layer 11, CNB represents the impurity concentration of the n-type layer 11, and CPB(X) represents the impurity concentration as a function of the depth of the p-type layer 13, respectively. The average value of the p-type layer can be estimated. Here, C= is the average impurity concentration of the p-type layer. The sample used in the experiment shown in Figure 3 is CNB = 4 x 1013
Since 礪-3, kaku = ni4×1α7d-3, 7 words = γN
Since it is B/100, if the lifetime of the n-type layer shown in FIG. 3 is set to 11100, the lifetime of the p-type layer can be obtained.

However, the above relational expression cannot be used for the lifetime in the gold diffusion process, and the lifetime of the n-type layer in which gold is selectively diffused is lower than that in the previous process, but the p-type layer, which is hardly affected by gold diffusion, is As for the lifetime of the mold layer, most of the values from the previous process are maintained. Therefore, according to FIG. 3, the lifetime of the p-type layer according to the present invention is about 40 times longer than that of the conventional example.

As an example of device characteristics that prove this, POCl was used to form the phosphorus glass layer. 900 with spread sources such as
Deposition above ℃ is effective. Formation of phosphorus glass by CVD is usually carried out at a temperature of about 500°C, but it does not contain copper (Cu) and iron (F), which are the main contaminating heavy metals in semiconductors.
e) The diffusion constant of gold (Au) is the same as that of Cu, . F
e is 6 x 10-0 cIt/Sec, whereas 10-0 cTi/SeclAu at 900°C is 10-1 at 500°C.
10-7d/S at 9000C for 1c1t/Sec
ec, the values at 900°C are two to four orders of magnitude larger. This is important in the Ringetter process which is a part of the present invention; the higher the temperature, the more the diffusion of heavy metals will be promoted, and the heavy metals in the semiconductor will be adsorbed into the phosphorus glass layer. but,
If the temperature is too high, phosphorus will diffuse into the semiconductor and change the impurity concentration distribution, so the temperature for forming the phosphorus glass layer in the present invention is preferably in the range of 700 to 1100°C. It can be seen from the experimental results shown in FIG. 4 that the formation temperature of this phosphor glass layer, that is, the ringer temperature, is preferably 700 DEG C. to 1100 DEG C. This figure 4 shows the change in lifetime (vertical axis) with respect to Ringeter temperature (horizontal axis). From this figure, it can be seen that at Ringeter temperature between 700°C and 1100°C, the lifetime is high and there is little variation. It can also be seen that the lifetime of the ringer does not necessarily improve as the temperature rises. Furthermore, when the above-mentioned phosphorus glass layer forming temperature is applied to the Si substrate, crystal defects in the Si substrate are reduced due to the ring getter effect and the annealing effect. For example, by heating at 1000° C. for about 1 hour, crystal defects are reduced to one to two orders of magnitude compared to before heating, and the lifetime increases accordingly. In addition, when forming phosphorus glass by CVD, the heating temperature is at most 600°C or less,
There is almost no annealing effect mentioned above. FIG. 5 shows a comparison of the forward blocking characteristics of the thyristor between conventional a and an embodiment b of the present invention, and FIG. 6 similarly shows the forward conduction characteristics of the thyristor between conventional a and an embodiment of the present invention. Compare and show. The fifth of these
From the figure, it can be seen that the forward blocking voltage increases by about twice as much in the method according to the embodiment of the present invention as compared to the conventional method (FIG. 1).
It can be seen from FIG. 6 that the on-voltage at an anode current of 100 QA is reduced to about 112. As explained above, according to the present invention, the switching characteristics (temporal) are slightly improved (when multiple units are connected in parallel, the effects described above are achieved), and it is possible to increase the withstand voltage and reduce heat loss. ,
Furthermore, reproducibility and control range in the manufacturing process are improved. In the above embodiment, it was applied to a thyristor, but
It goes without saying that the method of the present invention can be applied to switching elements such as power transistors, G'IOs, and optical thyristors.

For example, in the case of GTO, after forming an n-type layer 15 which becomes a cathode layer, this n-type layer 15 is divided into a plurality of parts by mesa etching etc., and a phosphorus glass layer 26 is formed on the divided surfaces as in FIG. 2b. That's why. In addition, in the case of this G'10, the gold diffusion conditions after forming the phosphor glass layer 26 are 800
℃, 2 to 4 hours. GT obtained in this way
The characteristics of O are that when the gate turn-off current is 60V and the anode current is 60V, the on-voltage is 2.2V (conventional GTO is 3.3V).
V), surge current withstand capacity is 5000A (conventional GTO is approximately 3000A), off voltage is 3000V (conventional GT
O was approximately 1500V). Further, in the above embodiments, only typical heat treatment steps before gold diffusion were considered, but in the method of the present invention, between the step of forming a layer containing phosphorus, such as a phosphorus glass layer, and the lifetime killer diffusion step, Even if some heat treatment process such as a thermal oxidation process, p-type diffusion process, or CVD process is involved, the effects of the present invention are not impaired.

[Brief explanation of the drawing]

1A to 1D are process sectional views for explaining a conventional method for manufacturing a switching element, FIGS. 2A to 2E are process sectional views for explaining an embodiment of the present invention, and FIG. A curve diagram showing a comparison between the change in lifetime corresponding to the manufacturing process shown in Figure 1 and the change in lifetime corresponding to the manufacturing process shown in Figure 2. Figure 4 is a curve for explaining the effects of the present invention. 5 is a diagram comparing the forward blocking characteristic b of an embodiment of the present invention (FIG. 2) with the forward blocking characteristic a of the conventional method (FIG. 1), and FIG. 2 is a diagram showing a comparison between the forward conduction characteristics of the embodiment (FIG. 2) and the conventional conduction characteristics (FIG. 1). FIG. 11... n-type Sj substrate, dan... Si substrate,
12...p-type layer serving as an anode layer, 13...
... p-type layer, 14 and 26, which becomes p base layer...
Phosphorous glass layer, 15... N-type layer that becomes a cathode layer.

Claims (1)

[Claims] 1 A step of forming a layer containing an n-type impurity on at least one surface of a semiconductor substrate whose at least one surface is a p-type semiconductor layer, and after the step, heat treatment is performed to diffuse the n-type impurity to form an n-type layer. a step of forming, and n obtained by the step.
A method for manufacturing a switching element comprising the step of diffusing lifetime killer atoms from the mold layer side or the other surface of the semiconductor substrate, the step of diffusing the n-type impurity to form an n-type layer; During the step of diffusing lifetime killer atoms, a layer containing phosphorus is formed on at least one surface of the semiconductor substrate, and the temperature is lower than the n-type layer formation temperature and higher than the diffusion temperature of the lifetime killer atoms. A method for manufacturing a switching element, characterized in that ring etching is performed at a temperature of 700°C to 1100°C.