JPS6042793A - Plasma display panel driving system - Google Patents

Plasma display panel driving system

Info

Publication number
JPS6042793A
JPS6042793A JP58150802A JP15080283A JPS6042793A JP S6042793 A JPS6042793 A JP S6042793A JP 58150802 A JP58150802 A JP 58150802A JP 15080283 A JP15080283 A JP 15080283A JP S6042793 A JPS6042793 A JP S6042793A
Authority
JP
Japan
Prior art keywords
circuit
control signal
control
transistor
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58150802A
Other languages
Japanese (ja)
Inventor
神津 三久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP58150802A priority Critical patent/JPS6042793A/en
Publication of JPS6042793A publication Critical patent/JPS6042793A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はプラズマ、ディスプレイ、パネルの駆動システ
ムに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a plasma, display, and panel drive system.

従来システムでの被駆動回路の一実施例を第1図に、従
来システムのブロック図を第2図(a)、タイミング図
を第2図(b)にて説明する。
An example of a driven circuit in a conventional system will be explained with reference to FIG. 1, a block diagram of the conventional system in FIG. 2(a), and a timing diagram in FIG. 2(b).

第1図において、出力信号波形104を得る場合、起動
信号波形102は、第2図(b)のタイミング図1、電
源信号波形101のt、に同期させる。
In FIG. 1, when obtaining the output signal waveform 104, the activation signal waveform 102 is synchronized with t of the power signal waveform 101 in the timing diagram 1 of FIG. 2(b).

同様に、制御信号波形103も、電源信号波形101の
t2に同期させる。
Similarly, the control signal waveform 103 is also synchronized with t2 of the power signal waveform 101.

第2図(b)タイミングt、の間、トランジスタ02け
、蓄積時間1mKよ多動作状態にあり、起動電流は、抵
抗05、ダイオード03を経て、トランジスタ01と、
トランジスタ02に分流する。
During the timing t in FIG. 2(b), the transistor 02 is in a multi-operation state for an accumulation time of 1 mK, and the starting current passes through the resistor 05 and the diode 03 to the transistor 01.
The current is shunted to transistor 02.

ダイオード03の逆回復時間trr (1)は、1叫電
流に依存する墨より、この場合、起動電流に依存する。
In this case, the reverse recovery time trr (1) of the diode 03 depends on the starting current rather than on the single current.

トランジスタ02が完全に動作停止状態の場合、起動電
流は、トランジスタ01のベース電RtD ミであるが
、タイミングt、の間トランジスタo2け動作状態にあ
り、トランジスタ01のベース電流よシもはるかに大き
い電流がトランジスタo2に流れる。
When transistor 02 is completely inactive, the starting current is equal to the base voltage RtD of transistor 01, but only transistor o2 is in operation during timing t, and the base current of transistor 01 is also much larger. Current flows through transistor o2.

(起動市、圧102)−(順’ekifEVp03)−
(xミ、、電圧VBEo1)起動電流言□ (抵抗05) この状態で、タイミングt、を終了すると、市、源電圧
波形101力j高電圧より低電圧に変化した場合、出力
端子104より入力される電流は、ダイオード04、ト
ランジスタ01のペース・コレクタ・ダイオードより1
@〕源端子101に流九るものと、ダイオード03の逆
回復時間br(1)により起動端子102に流れるもの
として分流される。電源端子]02に流gる電流が少な
いと、トランジスタO1のベース・コレクタ・ダイオー
ドの蓄積電荷が少なく、逆回復時間trr(21が短か
くなる。
(Startup city, pressure 102) - (order'ekifEVp03) -
(x, voltage VBEo1) starting current (resistance 05) In this state, when timing t ends, the source voltage waveform 101 changes from high voltage to low voltage, input from output terminal 104. The current flowing through diode 04 is 1 from the pace collector diode of transistor 01.
@] The current flows to the source terminal 101 and the current flows to the start terminal 102 due to the reverse recovery time br(1) of the diode 03. When the current flowing through the power supply terminal]02 is small, the charge accumulated in the base-collector diode of the transistor O1 is small, and the reverse recovery time trr (21) is shortened.

逆回得時間trr(21を終了後、電源端子電圧101
が低電圧より高短、圧に変化しても、トランジスタ01
は自動的に動作状態にならず、異常動作状態”St (
’alが発生する。
After completing reverse retrieval time trr (21, power supply terminal voltage 101
Even if the voltage changes to higher or shorter than the low voltage, the transistor 01
does not automatically enter the operating state and enters the abnormal operating state "St (
'al occurs.

逆回復時間trr(21内で、電の端子電圧波形101
を低電圧より高電圧に変化させる墨は、タイミングt2
内の周波数を上げることになシ駆動条件が、かなり限定
される欠点があっfc、さらにタイミングt〆トランジ
スタ02より接地端子、105に流れる電流は、無駄1
ビ、流であり、抵抗05.ダイオード03.トランジス
タ02のパワー損失の増加に力る欠点があった。
Reverse recovery time trr (within 21, electric terminal voltage waveform 101
The black mark that changes the voltage from a low voltage to a high voltage is at timing t2.
Increasing the frequency within fc has the disadvantage that the driving conditions are quite limited, and furthermore, the current flowing from the timing t〆 transistor 02 to the ground terminal 105 is wasted 1
Bi, flow, resistance 05. Diode 03. There was a drawback that the power loss of the transistor 02 increased.

本発明の目的は、このような欠点を解消することにある
An object of the present invention is to eliminate such drawbacks.

本発明によれば起動(入力)部、出力部、制御部で構成
される〃プラズマ・ディスプレイ・パネル駆動回路〃の
駆動システムで、制御信号発生装置、制御信号バッファ
回路の間に、当該する制御入力信号の終了(反転)タイ
ミングに対して、被駆動回路の動作特性改善に必要な時
間だけ早く、制御入力信号を終了(反転)する制御信号
変更回路を設けたことを特徴とする駆動システムが得ら
れる。
According to the present invention, in a drive system for a plasma display panel drive circuit, which is composed of a starting (input) section, an output section, and a control section, the relevant control A drive system is provided with a control signal changing circuit that terminates (inverts) a control input signal earlier than the input signal termination (inversion) timing by a time necessary to improve the operating characteristics of a driven circuit. can get.

すなわち第2図の従来の制御信号波形103より第3図
の制御信号波形116に変更する事により実現している
。以下、第3図(a) (b)で、この発明による一実
施例をブロック図と、タイミング図により説明する。
That is, this is realized by changing the conventional control signal waveform 103 in FIG. 2 to the control signal waveform 116 in FIG. 3. Hereinafter, one embodiment of the present invention will be explained using a block diagram and a timing diagram with reference to FIGS. 3(a) and 3(b).

制御信号バッファ回路113の前段に、制御信号変更回
路114を設置し、トランジスタ02の蓄積時間t・(
=タイミング図s)に相当する時間タイミング17で、
制−@1信号116を1−0“レベルにし、タイミング
t、の間は、トランジスタ02を完全に動作停止状態に
する。ダイオード03TfC’R,fLる電流を、トラ
ンジスタ01のベース電流IBのみにすることにより、
タイオード03の逆回復時間trr(1)を短縮(ts
よりtll) ’L、駆動条件の緩和を行った駆動方式
を得ることができる。
A control signal changing circuit 114 is installed before the control signal buffer circuit 113, and the storage time t・(
= At time timing 17 corresponding to timing diagram s),
The control@1 signal 116 is set to 1-0" level, and the transistor 02 is completely stopped during timing t. The current flowing through the diode 03TfC'R, fL is made to flow only to the base current IB of the transistor 01. By doing so,
Shorten the reverse recovery time trr(1) of diode 03 (ts
tll) 'L, it is possible to obtain a driving method in which the driving conditions are relaxed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明および従来システムでの被駆動回路
の一実施例である。第2図(a)、 (b)は、従来シ
ステムの一矢、施例であり、第3図(a)、 (b)は
、この発明の一実施例である。第2図、第3図の(a)
はブロック図、(b)はタイミング図であシ各々′φ−
圧波形で稍1いている。図中01〜07は、被駆動回路
内の集子で、トランジスタ01,02ダイオード03.
04、抵抗05〜07で示している。図中、同一符号は
同一またh1相当部分を示す。 101・・・・・・電源端子および信号、102・・・
・・・起動(入力)端子および信号、lo3・・・・・
・制御端子および信号、104・・・・・・出力端子お
よび信号、105・・・・・・接地端子、106・・・
・・・被駆動回路、107・・・・・・制御信号発生装
置、1o8・・・・・・電源制御信号、109・・・・
・・電源回路、11o・・・・・・起動(入力)制御信
号、111・・・・・・起動信号発生回路、112・・
・−・・制御入力信号、113・・・・・・制御信号バ
ッファ回路、114・・−・・・制御信号変更回路、1
15・・・・・・変更制御入力信号、116・・・・・
・変更制御信号を示す。 第3図 ((1) (b)
FIG. 1 shows an embodiment of a driven circuit in the present invention and a conventional system. FIGS. 2(a) and 2(b) show an example of a conventional system, and FIGS. 3(a) and 3(b) show an example of the present invention. (a) in Figures 2 and 3
is a block diagram, and (b) is a timing diagram.
There is a slight difference in the pressure waveform. In the figure, 01 to 07 are collectors in the driven circuit, including transistors 01, 02, diodes 03, .
04, resistances 05 to 07. In the figure, the same reference numerals indicate the same parts or parts corresponding to h1. 101...Power terminal and signal, 102...
...Start (input) terminal and signal, lo3...
- Control terminal and signal, 104... Output terminal and signal, 105... Ground terminal, 106...
... Driven circuit, 107 ... Control signal generator, 1o8 ... Power supply control signal, 109 ...
...Power supply circuit, 11o...Start-up (input) control signal, 111...Start-up signal generation circuit, 112...
--- Control input signal, 113 --- Control signal buffer circuit, 114 --- Control signal changing circuit, 1
15... Change control input signal, 116...
- Indicates a change control signal. Figure 3 ((1) (b)

Claims (1)

【特許請求の範囲】[Claims] 起動(入力)部、出力部、制御部で構成される”プラズ
マ、ナイスプレイ、パネル駆動回路”の躯勤−システム
で、制御信号発生装置、制御信号バッファ回路の間に、
当該する制御入力信号の終了(反転)タイミングに対し
て、被駆動回路の動作特性改善に必要な時間たけ早く、
制御入力信号を終了(反転)する。制御信号変更回路を
設けたことを特徴とする駆動システム。
This system consists of a "plasma, nice play, and panel drive circuit" consisting of a startup (input) section, an output section, and a control section. Between the control signal generator and the control signal buffer circuit,
With respect to the termination (inversion) timing of the relevant control input signal, as early as necessary to improve the operating characteristics of the driven circuit,
Terminate (invert) the control input signal. A drive system characterized by being provided with a control signal changing circuit.
JP58150802A 1983-08-18 1983-08-18 Plasma display panel driving system Pending JPS6042793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58150802A JPS6042793A (en) 1983-08-18 1983-08-18 Plasma display panel driving system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58150802A JPS6042793A (en) 1983-08-18 1983-08-18 Plasma display panel driving system

Publications (1)

Publication Number Publication Date
JPS6042793A true JPS6042793A (en) 1985-03-07

Family

ID=15504743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58150802A Pending JPS6042793A (en) 1983-08-18 1983-08-18 Plasma display panel driving system

Country Status (1)

Country Link
JP (1) JPS6042793A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358949A (en) * 1986-03-05 1994-10-25 Otsuka Pharmaceutical Co., Ltd. Carbostyril derivatives and salts thereof and anti-arrhythmic agents containing the carbostyril derivatives

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358949A (en) * 1986-03-05 1994-10-25 Otsuka Pharmaceutical Co., Ltd. Carbostyril derivatives and salts thereof and anti-arrhythmic agents containing the carbostyril derivatives

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