JPS6042743U - integrated circuit package structure - Google Patents

integrated circuit package structure

Info

Publication number
JPS6042743U
JPS6042743U JP13412583U JP13412583U JPS6042743U JP S6042743 U JPS6042743 U JP S6042743U JP 13412583 U JP13412583 U JP 13412583U JP 13412583 U JP13412583 U JP 13412583U JP S6042743 U JPS6042743 U JP S6042743U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
package structure
pin
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13412583U
Other languages
Japanese (ja)
Inventor
新宮 宏
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP13412583U priority Critical patent/JPS6042743U/en
Publication of JPS6042743U publication Critical patent/JPS6042743U/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の集積回路パッケージ構造の一実施例を示す
斜視図である。 図において、1・・・・・・DIP、2・・・・・・プ
リント基板、1G、  11.20.21・・・・・・
配列、12・・・・・・挿入極性指示部、A、 B、〜
H,I、〜P・・・・・・ピン、a、b、〜h、  i
、〜pφφ・Φ・・スルーホール。
The figure is a perspective view showing an embodiment of the integrated circuit package structure of the present invention. In the figure, 1...DIP, 2...Printed circuit board, 1G, 11.20.21...
Arrangement, 12... Insertion polarity instruction section, A, B, ~
H, I, ~P...Pin, a, b, ~h, i
,~pφφ・Φ・・Through hole.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デュアルインライン形集積回路パッケージにおいて、少
なくとも1つのピンを他のピンの列からずれた位置に配
置してなることを特徴とする集積回路パッケージ構造。
What is claimed is: 1. An integrated circuit package structure, characterized in that, in a dual in-line integrated circuit package, at least one pin is arranged at a position offset from the other pin rows.
JP13412583U 1983-08-30 1983-08-30 integrated circuit package structure Pending JPS6042743U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13412583U JPS6042743U (en) 1983-08-30 1983-08-30 integrated circuit package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13412583U JPS6042743U (en) 1983-08-30 1983-08-30 integrated circuit package structure

Publications (1)

Publication Number Publication Date
JPS6042743U true JPS6042743U (en) 1985-03-26

Family

ID=30302315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13412583U Pending JPS6042743U (en) 1983-08-30 1983-08-30 integrated circuit package structure

Country Status (1)

Country Link
JP (1) JPS6042743U (en)

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