JPS6041892B2 - variable frequency divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable frequency divider circuit that can be highly integrated and has a high operating speed.

Conventionally, a variable frequency divider circuit has been proposed in which a predetermined frequency division ratio is obtained by changing each frequency division period of frequency division into P frequency division and P+ frequency division.

This type of frequency divider circuit has the advantage that the frequency division ratio can be changed in fine steps without increasing the frequency of the clock pulse too much. This frequency dividing circuit usually includes a controlled prescaler circuit, a variable frequency divider, an auxiliary variable frequency divider, and a latch circuit.

The controlled prescaler circuit has its frequency division number changed to P or Pfr by a control signal applied from the outside, and provides its frequency division output to the variable frequency divider and the auxiliary variable frequency divider. The variable frequency divider divides the frequency divided output into the given data M'
Divide the frequency by On the other hand, the auxiliary variable frequency divider converts the divided output from the controlled prescaler circuit into the given data q.
Divide the frequency by The latch circuit is then set by the output of the variable frequency divider and reset by the output of the auxiliary variable frequency divider. When set, the latch circuit sends out a control signal to cause the controlled prescaler circuit to frequency divide to P+, and also resets the auxiliary variable frequency divider.
With such a configuration, the controlled prescaler circuit divides the input signal to P+ only during the period when the auxiliary variable frequency divider counts q, and divides the input signal into P+ during the period when the variable frequency divider counts M' - q. The prescaler circuit divides the input signal into P frequency.

Therefore, if = 1, the total frequency division number of the frequency divider circuit is
(P+1)qfP(M'-q) -A l ■.

Here, when the data M'' is increased by one, the total frequency division number is , which differs from the above case by P.

Therefore, by setting q=P, all frequency division numbers between variable frequency divider data M'' and M''+1 can be obtained by changing q. By the way, in a frequency dividing circuit configured as described above, in order to generally increase the total variable frequency division number, the variable frequency division number M'' is often set larger than the variable frequency division number q.

On the other hand, the variable frequency divider that changes the frequency division number according to the variable frequency division numbers M'' and q is different from the single feedback type 2n frequency divider, and is different from the feedback type of the flip flop circuit connected in multiple stages. Since the loop is switched to obtain a predetermined frequency division ratio, as the frequency division number becomes larger, the feedback path becomes longer and the operation time becomes extremely slow. Therefore, it is preferable to use a frequency division ratio of M'' In order to lighten the burden on the variable frequency divider that determines the frequency, it is possible to increase the frequency division number of the auxiliary variable frequency divider that determines the frequency division number of q, but in this case, the above formula As is clear from the above, since the range of q is determined by the frequency division number P of the controlled prescaler circuit, P has to be increased in the end.

However, increasing P causes the following problems. In other words, since the controlled prescaler circuit that determines P is inserted at the forefront of this frequency dividing circuit, it must be constructed of high-speed elements that can respond to clock pulses, such as Schottky'ITL and ECL. is desirable.

However, these high-speed devices require a large mounting area, making it difficult to achieve high integration. Therefore, this becomes a factor that prevents higher integration of the entire frequency dividing circuit. As described above, in the conventional variable frequency dividing circuit of this type, it has been difficult to obtain a variable frequency dividing circuit capable of high speed and high integration. The present invention was made based on the above circumstances, and an object of the present invention is to provide a variable frequency divider circuit that is capable of high speed and high integration.

The present invention is characterized in that, in the variable frequency divider circuit described above, an auxiliary frequency divider is inserted before the variable frequency divider.

That is, now, the frequency division number of the controlled prescaler circuit is divided by P or P+1, the frequency division number of the auxiliary frequency divider is N1, the frequency division number of the variable frequency divider is M, and the frequency division number of the auxiliary variable frequency divider is If q,
The total frequency dividing number of the variable frequency dividing circuit according to the present invention is as follows.

In this case, if M is increased by one, then the variable range of q can be expanded to PN without changing P.

This means that the variable range of M can be reduced accordingly. The frequency divider that determines N does not impair the speeding up of the circuit in any way. Therefore, according to the present invention, the load on the variable frequency divider can be reduced without particularly increasing the frequency division number of the controlled prescaler, so that the variable frequency divider can operate at high speed without any loss in high integration. A frequency divider circuit can be obtained.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram, and numeral 1 indicates a controlled prescaler circuit composed of high-speed logic gates such as ECL.

This prescaler circuit 1 divides the frequency of an input signal Fin by P or (P±1) based on a control signal to be described later. The frequency-divided output signal frequency-divided by this prescaler circuit 1 is frequency-divided by N via an auxiliary frequency divider 2, and then inputted to a variable frequency divider 3 where it is frequency-divided by M. The frequency division number M by the variable frequency divider 3 is input as a preset from the outside, for example. Further, the frequency-divided output of the prescaler circuit 1 is inputted to an auxiliary variable frequency divider 4, where the frequency is divided by q. This frequency division number q is also preset input from the outside like the frequency division number M. These circuits, that is, the auxiliary frequency divider 2 and the variable frequency divider 3, are composed of I2L logic gate circuits, and the auxiliary variable frequency divider 4 is composed of high-speed logic gates such as ECL, and is the same as the prescaler circuit 1. They are simultaneously integrated and formed on a semiconductor substrate. Further, a latch circuit 5 composed of a high-speed logic gate such as an ECL integrated simultaneously with the above-mentioned circuits is set by the output signal of the variable frequency divider 3, and is set by the output signal of the auxiliary variable frequency divider 4. It has been reset. This latch circuit 5 outputs a reset signal to the auxiliary variable frequency divider 4 and also issues the aforementioned control signal to the controlled prescaler circuit 1. Therefore, the prescaler circuit 1 normally receives the input signal Fin.
The input signal Fin is divided into (P±1
) Divide the frequency. According to the circuit configured in this way, the input signal Fin is divided by (P±1) for a q frequency division period determined by the auxiliary variable frequency divider 4, that is, after it is divided by q times. , P frequency division operation is determined by frequency dividers 2, 3, and 4 (
This will be repeated MN-q) times.

Therefore, the total frequency division number of the input signal Fin is as follows.

This total frequency division number can be variably set by data input values M and q. Now, here is the main frequency division value P of this counting circuit.
Assume that NM is determined by data M(7) times PN, and the shift frequency division number is given by q (q<NP).

Such a frequency division number can also be provided by, for example, a conventional swirl counter type frequency division circuit. For example 1~
When setting the dividing value of 1Cf' variably, 101, 103
If the digits are given by the frequency division data M and the 1σ, 101, 1Cf' digits are given by the data q, NP is effectively reduced to 1.
03, 103・M+Q, however, M=0~99,q
=0 to 999. However, if this is done, the operating speed of the entire circuit is limited, and if the value of NP is set to a value other than a multiple of 10, the specification of data M, etc. becomes extremely complicated. Therefore, in the circuit of the present invention,
By configuring the frequency division operation of the numerical value corresponding to q with high-speed operation logic gates, the frequency division operation of the numerical value corresponding to M can be operated at an operating speed of 1/NP with respect to the frequency of the input signal Fin. I have to. Therefore, the low-speed operation section can be highly integrated using a circuit such as I2L, and even when the value of NP is other than a multiple of 10, the external data M can be easily specified. That is, according to the circuit configuration shown in FIG. 1, the limit on the operating speed for the input signal Fin depends only on the operating speed of the prescaler circuit 1, and the auxiliary frequency divider 2 and the variable frequency divider 3 limit the operation speed of the input signal Fin. 1/P of frequency
It is sufficient to have an operating speed of approximately ±1. In addition, since the variable frequency division value is actually specified for the signal further divided through the auxiliary frequency divider 2, when the deviation frequency division value q is set to be large, the value given to the prescaler circuit 1 is The burden can be reduced. Therefore, the frequency division number is P
When performing frequency division and (P-1) frequency division by switching, the value determined by P and N is determined as (NPxM-q). In addition, the prescaler circuit 1 performs P frequency division and (P+
1) When performing frequency division operation, the frequency division number of the circuit is (NPX
M+q). Therefore, since q can be varied within the range of NP, if the value of N is appropriately set as necessary, the variable range of q can be increased without increasing P, and the M can be reduced by that amount, and as a result, the operating speed of the variable frequency divider 3 can be increased, and as a result, the entire circuit can be operated at high speed. Conversely, by adopting such a circuit configuration, the variable frequency divider 3, the auxiliary variable frequency divider 4, etc. can be configured using low-speed operation elements, such as I2L logic gates, and the overall The packaging density can be increased without reducing the operating speed of the device.

FIG. 2 is a schematic diagram of a PPL (phase locked loop) circuit for controlling the local oscillation frequency in a television tuner constructed using the circuit of the present invention.

This PPL circuit controls the oscillation output signal (frequency: F..x,) of the voltage controlled oscillator (VCO) 11. This control sets the frequency division number in this circuit to (NPxM-q)
, and the reference frequency is Fr.

The frequency band of television signals is approximately 150MHz to 85MHz.
0 MI (about 1 MHz), and in order to receive each channel with good discrimination, channel steps at approximately 1 MHz intervals are required.Furthermore, in order to improve the tuning accuracy for the selected frequency, the frequency F. It is necessary to further fine-tune cO, that is, fine-tuning.In order to perform this fine-tuning,
It is necessary to perform a frequency shift of approximately several 10 K pressure units.
To explain the circuit shown in FIG. 2, the signal output from the VCOll is supplied to a television tuner (not shown) as a local oscillation output signal, and the prescaler circuit 12
For example, it is inputted into 1 and is repeated once.

This one-rounded signal is input to the control type prescaler circuit 13 according to the circuit of the present invention and is one-rounded or one-rounded. This switching between 1-rolling and 1-rolling is performed based on the control signal described above. And prescaler circuit 1
The frequency-divided output signal of 3 is frequency-divided by 2 via the auxiliary frequency divider 14 on the one hand, and then input to the variable frequency divider 15 where it is frequency-divided by M. On the other hand, the auxiliary variable frequency divider 16
is input and frequency-divided by q. These variable frequency dividers 1
The frequency division values M and q of 5 and 16 are given via latch circuits 17 and 18, respectively, which input external data M and q. Here, the frequency division value q is, for example, 0 to 32.
, and the frequency division value M is set to be 150 to 180, for example. In addition, the latch circuit 19 is a variable frequency divider 15.
It is set by the output signal of the auxiliary variable frequency divider 16 and reset by the output signal of the auxiliary variable frequency divider 16 to output a control signal to the control type prescaler circuit 13 and a reset signal to the auxiliary variable frequency divider 16. Thus, the oscillation output signal of VCOll is frequency-divided by these frequency dividers.

This frequency-divided output signal is supplied to a phase comparator 20 where it is phase-compared with a reference frequency signal F, and the comparison detection signal is supplied via a low-pass filter 21 as a control signal for the VCOll. There is. However, P configured in this way
According to the LL circuit, the frequency of Fr is 1.953125K
When set to 5Ωυ′）■ ＼A▼
The oscillation frequency FvcO can be controlled as the AALU.

That is, after specifying the reception frequency M using the frequency division value M, fine tuning in 31.25 KHz steps becomes possible using the frequency division value q. Now, P like this
In the LL circuit, the prescaler circuits 12 and 13 are set to ECL.
If the ECL section is configured with high-speed logic gates and other circuit parts are configured with I2L logic gates and integrated simultaneously, the ECL section can be configured with approximately 9 flip-flop circuits with an operating speed of approximately 850 MHz or more. Further, I2L can construct a flip-flop circuit with an operating speed of 4M cells or more using approximately 4C@.
As is clear from the number of these flip-flop circuits, the present PPL circuit can be integrated on a single chip semiconductor substrate with sufficient margin. Note that the present invention is not limited to the above embodiments.

For example, Schottky TTL is F as a high-speed logic gate.
It is also possible to configure with EL, or a combination of these may be configured. Further, the setting of the frequency division number of the prescaler circuit and the frequency division value given to the variable frequency divider may be determined as appropriate based on the specifications. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing one embodiment of the circuit of the present invention, and FIG.
The figure is a configuration diagram of a PLL circuit for local oscillation control of a television to which the same embodiment circuit is applied. 1, 13...Controlled prescaler circuit, 2, 14
...Auxiliary frequency divider, 3,15...Variable frequency divider, 4,16...Auxiliary variable frequency divider, 5,19.
... Latch circuit, 11 ... Voltage controlled oscillator (VCO), 12 ... Prescaler circuit, 17,
18... Latch circuit, 20... Phase comparator, 21... Low pass filter.

Claims (1)

[Claims] 1. A controlled prescaler circuit that divides an input signal by P or (P±1), an auxiliary frequency divider that divides the frequency-divided output signal of this prescaler circuit by N, and this auxiliary frequency divider. a variable frequency divider which divides the frequency divided output signal of 1 by M based on external data M; and a variable frequency divider which is operated by the frequency divided output signal of this variable frequency divider to give a control signal to the prescaler circuit (P± 1) An auxiliary frequency divider that performs frequency division operation and returns the prescaler circuit to P frequency division operation after dividing the frequency of this (P±1) frequency division output signal by q based on external data q. A variable frequency divider circuit featuring: 2. The high-speed operation section including the controlled prescaler circuit is composed of bipolar high-speed logic gates, and the remaining low-speed operation section is composed of I^2L logic gates, and these logic gates are simultaneously integrated on the same substrate. The variable frequency dividing circuit according to claim 1. 3. The variable frequency divider circuit according to claim 2, wherein the bibolar type high-speed logic gate is a Schottky TTL or ECL logic circuit.