JPS6041396B2 - Address detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address detection device that automatically detects a portion where an address is written from among the address, sender's address, correspondence, figure, etc. written on a letter or the like.

Currently, automatic postal code sorting machines are widely used as devices for recognizing postal codes.

According to the sorting machine, for postal codes written within the red frame indicating the position of the postal code on letters, etc., and postal codes written in printed letters outside the red frame, the position of the postal code is determined by the machine in advance. By setting almost 1
It can be read close to 00%.

However, postal codes written in printed letters in positions other than the red frame cannot be read at all unless the position of the postal code is set in advance. This is a major cause of significant restrictions on the range of letters, etc. that can be processed.

FIG. 1 shows a typical example of the address writing surface of a letter written in printed type. Generally, the front side of a letter has a part 104 in which the sender's address is written in addition to a part 102 in which the addressee is written.
It is generally composed of 100 characters or figures such as , confidential, etc. The following method is known as a means for detecting the position where an addressee is written in a letter such as the one shown in FIG. 1. That is,
100, 102, 104 characters, figures, etc. on the address writing side 2
Dimensionally, a blank area 10 with a certain distance or more around it
1, 103, 105, the group of characters, figures, etc. is divided into blocks (hereinafter referred to as character blocks), and then the regularity of the position or mutual positional relationship described for each character block is determined. By paying attention, a cluster of characters, figures, etc. in which the addressee is written is identified from among the character blocks. However, if you look at letters written in printed type that are currently in circulation, the address is blank.

There is no significant regularity in the writing position of the block or in the positional relationship between the character blocks, and it is extremely difficult to correctly detect the position of the address block using the above method.
The inventors of the present invention have noted that the above-mentioned features of letters, etc. in which the addressee is written in printed letters, which occupy a large proportion of the letters, etc., include the addressee, sender's address, correspondence, figures, etc. discovered that address blocks can be detected from character blocks.

A large number of address blocks are written in print using address cards or EDP printing devices such as line printers.

These descriptions include the postal code, address, addressee's name, code number, etc., all printed in characters of a certain size and written in several lines of characters. On the other hand, in the character block such as the sender's address, the characters are printed on the letter etc. in advance, so the font size of the sender's address and the sender's name are not constant, and the company name mark etc. What is there is normal.

In other words, compared to other blocks, the address block is characterized by having the same font size and by having several lines. The purpose of the present invention is to detect an address block by searching for a character string consisting of several lines with a fixed printed character size from character blocks such as an addressee, sender's address, correspondence, etc. written on a letter, etc. The objective is to provide a device that

In order to achieve the above object, an address detection device according to the present invention includes a circuit that inputs a block-by-block pattern of characters written on a letter, etc., and a circuit that detects the height of the characters in the block pattern from the input information. A circuit, a counting circuit that counts the number of lines of character strings of substantially the same height in the block pattern, and a comparison to determine whether the value obtained from the counting circuit is within a predetermined value as the number of lines of the address. By doing so, it is configured to detect whether or not the block pattern is a portion in which an addressee is written.

According to the above configuration, the destination block can be detected and the object of the present invention can be achieved.

Furthermore, the detection allows reading of the postal code without any manual operation. Hereinafter, the addressee detection device according to the present invention will be explained in more detail with reference to the drawings.

FIG. 2 is a block diagram of an apparatus for detecting address blocks according to the present invention.

In the following explanation, the longitudinal direction of the envelope in Figure 1 is horizontal (row).
Let the lateral direction be the scanning direction. In FIG. 2, an input circuit 1 outputs a pattern signal S2 for an arbitrary character block among character blocks to a pattern horizontal compression circuit 2. This signal S2 is a signal corresponding to a large number of scanning lines converted to (0, 1) in the scanning direction. It may be a signal obtained by digitizing the output of a flying spot scanner, or it may be a signal read out from a memo stored as flock information.
The pattern data horizontal compression circuit 2 receives the pattern signal S
2 in the direction of the rows of the pattern, the two-dimensional pattern information of the character block is compressed into one-dimensional information. Signal 1 on corresponding pixels on multiple scan lines
Even when there are many, it is shown as one point (lbit),
It is compressed into one-dimensional information in the scanning line direction. This compressed information S
3 is input to the block height detection circuit 3. The block height detection circuit 3 sequentially counts the number of bits (hereinafter referred to as block height) of consecutive portions of 1 signals in the one-dimensionally compressed information (compressed information S3), and calculates the block height. A memo is stored in the detection circuit 2. This block height can correspond to the height of a character. At the same time, the minimum value of the block height (hereinafter referred to as minimum block height) is stored in a register, and the block height and the minimum block height are output to the character line number determination circuit 4 as block height information S4. The character line number determination circuit 4 counts the number of blocks included in the compressed information S3 based on the minimum block height, and compares the result with a prescribed line value to determine that the character block is an address block. When it is determined, destination block detection information S5 is output.
In the character block, address block detection information S5
If the address block is not obtained, the above operation is repeated for the next character block, thereby making it possible to detect the address block.

FIG. 3 is a block diagram showing the above-mentioned address detection apparatus of the present invention in more detail. When the configuration of FIG. 3 corresponds to FIG. 1, the input circuit 1 corresponds to the input circuit 11, the pattern data horizontal compression circuit 2 corresponds to the compression control circuit 21, the compression circuit 2
Corresponds to 2. The flock height detection circuit 3 includes a height detection control circuit 31, a force counter 32, a register 33, and a selector 34.
, a comparator 35, and a memory 36, the character line number determination circuit 4 includes an adder 41, registers 42, 46, and a comparator 43.
, 47, a row number detection control circuit 44, and a counter 45.

Next, referring to FIG. 3, the operation of detecting a destination block in the destination detection device of the present invention will be explained in detail.

A binary pattern signal S9 obtained by digitizing one character block from among the character blocks to be detected is input from the input circuit 11 to the compression circuit 22.

The compression circuit 22 logically ORs the pattern signal S9 in the row direction using the control signal S8 of the compression control circuit 21, thereby obtaining compressed information SII in which the two-dimensional pattern signal is compressed into a one-dimensional signal. The compressed information SII is input to the height detection control circuit 31. The compressed information SII is information in which the height of each block corresponds to the height of one line in a character block, or the height of multiple lines if the lines are very close to each other. By counting the block heights of blocks, height information of characters, etc. perpendicular to the direction of the character rows can be obtained.

The height detection control circuit 31 checks the value of the compression information SII one bit at a time, and every time the value changes from 0 to 1 and continues to be 1, the height detection control circuit 31 starts the counter 32 at the clock SI2. Count up the value of
When the value changes from 1 to 0, the output SI6 of the counter 32 is set in the register 33 with the clock S29, and the value of the counter 32 is cleared with the clock SI4. The above checking operation is further repeated, and when the value of the compression information SII changes from 1 to 0, the signal SI9 (hereinafter referred to as the minimum block height signal) indicating the block height of the previous block is compared with the output SI6 of the counter 32. When the output SI5 of the comparator 35 indicates that the output S16 of the counter 32 is greater than or equal to the minimum height signal SI9, a control signal SI7 is output to the selector 34 and the counter The output SI6 of the memory 32 is output as the data input signal SI3 of the memory 36, and the memory 3 is output with the memory control signal S18.
6, the counter 32 is cleared by the clock S14, and the above checking operation can be repeated. On the other hand, if the minimum height signal SI9 is larger than the output S16 of the counter 32, the minimum height signal SI9 is written in the memory 36, the output SI6 of the counter 32 is set in the register 33 at clock 29, and the output SI6 of the counter 32 is set at clock S14. is cleared and the above checking operation is repeated.

By repeating the above checking operation for the entire compressed information SII, up to 4 block heights SI are stored in the register 33.
9 and memory 36 store block height information of other blocks.

Next, the clock S22 clears the register 42 and sets the minimum block height SI9 to the output S23 of the register 42 to the adder 4.
1 and output S21 to register 4 with clock S30.
2, the block height information stored in the memory 36 is outputted as an output signal S20 in response to the memory control signal S18, and is compared with the output S23 of the register 42 in the comparator 43.

When the output S21 of the comparator 43 indicates that the output signal S20 and the output S23 of the register 42 are equal, the row number detection control circuit 44 outputs the clock S25, counts up the counter 45, and outputs the clock S22. The register 42 is cleared at clock S30, and the adder 4 is cleared at clock S30.
1 output S21 is set in the register 42, and the height information of the next block is output signal S201 using the memory control signal SI8.
This is output and the comparison operation is repeated. On the other hand, memory output S
If 20 is greater than the output S23 of the register 42, then
The counter 45 is counted up with the clock S25, and the output S21 of the adder 41 is sent to the register 42 with the clock S30.
, and the comparison operation is repeated until the memory output signal S20 and the output S23 of the register 42 become equal.

Furthermore, if the memory output S20 is smaller than the output S23 of the register 42, this indicates that the block being output by the memory output S20 is not composed of an integral multiple of the minimum block, so the counter 45 is started at the clock S25. Counts up by the same value as the value S26 of the register 46,
The comparison operation ends.

In the block height comparison operation, there is a variation in type;
Although it is possible that the block heights do not match completely due to dirt on the paper surface, etc., this can be easily resolved by adding a correction signal to the adder 41.

By performing the comparison operation for all blocks, the number of blocks included in the compressed information S11 based on the block with the minimum block height is output to the counter 45.

This value S27 indicates the number of lines of characters constituting the character block, and the comparator 47 uses the output S27 of the counter 45 and the value S26 of the line number setting register 46 in which the specified number of lines is set in advance. compare. The specified number of lines is
For example, it is set to 2 to 6 lines, and a block detection result S25 is output by comparing it with S27. If it is determined by the comparison that the block is not an address block, the above-described operation is sequentially performed for the next character block, thereby making it possible to detect the address block from among the character blocks.

As explained above, according to the address detection device according to the present invention, it is possible to detect an address block from character blocks such as an addressee, a sender's address, a correspondence, etc. written on a letter or the like.

As a result, it is possible to recognize the address block of a letter, etc. in which the address is written in printed letters without having to mechanically set the address position in advance, and it is possible to read the postal code based on this determination. be able to.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram for explaining the surface condition of the envelope;
FIG. 3 is a block diagram showing the configuration of an address detection apparatus according to the present invention, and FIG. 3 is a detailed block diagram showing an embodiment of the address detection apparatus according to the invention. 1... Input circuit, 2... Pattern data lateral compression circuit, (21... Compression control circuit, 22... Compression circuit),
3... Flock height detection circuit, (31... Height detection control circuit, 32... Counter, 33... Register,
34...Selector, 35...Comparator, 36...Memory), 4...Character line number determination circuit, (41...Adder, 42, 46...Register, 43, 47 ... comparator, 44 ... row number detection control circuit, 55 ... counter). Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 A circuit for inputting a pattern for each block of characters, etc. written on a letter, etc., a circuit for detecting the height of characters in the block pattern from the input information, and a circuit for detecting the height of the characters in the block pattern from the input information, By comparing a counting circuit that counts the number of lines of a character string and whether the value obtained from the counting circuit is within a predetermined value as the number of lines of the address,
An address detection device characterized in that it is configured to detect whether or not the block pattern is a portion in which an address is written.