JPS6040263A - Integrated circuit for driving double power source printing element - Google Patents

Integrated circuit for driving double power source printing element

Info

Publication number
JPS6040263A
JPS6040263A JP58149028A JP14902883A JPS6040263A JP S6040263 A JPS6040263 A JP S6040263A JP 58149028 A JP58149028 A JP 58149028A JP 14902883 A JP14902883 A JP 14902883A JP S6040263 A JPS6040263 A JP S6040263A
Authority
JP
Japan
Prior art keywords
circuit
low voltage
voltage
power supply
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58149028A
Other languages
Japanese (ja)
Other versions
JPH0373477B2 (en
Inventor
Masaharu Ozaki
尾崎 正晴
Haruhiko Nishio
春彦 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP58149028A priority Critical patent/JPS6040263A/en
Publication of JPS6040263A publication Critical patent/JPS6040263A/en
Publication of JPH0373477B2 publication Critical patent/JPH0373477B2/ja
Granted legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/35Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To check a heat generating element from operating under the non-control condition by operating a gate circuit under normal state by another low voltage being lowered from a high voltage during the lowering of a low voltage to prevent malfunctioning of an output transistor. CONSTITUTION:When the lowering of a low voltage from a terminal 2 is detected, a switch of a power source circuit 7 is changed over with a voltage detection circuit 9 for a low voltage power source and a low voltage is supplied to a gate circuit 3 from a voltage lowering circuit 8 for lowering the high voltage from a terminal 20. Consequently, the circuit 3 operates normally to generate a low level output without the supply of the power to a logic circuit 1 and an output transistor 5 is turned OFF through a level shifter and a buffer circuit 4 to prevent malfunctioning. Thus, a heat generating element 6 is checked from operating under the non-control state thereby eliminating breakdown of the element 6 due to overcurrent.

Description

【発明の詳細な説明】 本発明は二策源形印字素子駆動集積回路に関し、特に、
サーマルヘッド発熱体のごとき印字素子を二車源で駆動
する場合供給さiする低電圧の電圧が低下すると出力ト
ランジスタがオノトナリ、サーマルヘッドへの誤信号が
供給されないようにするための新規な改良に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual-source printing element driving integrated circuit, and more particularly, to
This invention relates to a new improvement for preventing output transistors from turning on their own when the low voltage supplied when driving a printing element such as a thermal head heating element with a two-wheel power source prevents an erroneous signal from being supplied to the thermal head. It is something.

従来、用いられていたサーマルヘッド駆動回路において
は、レベルシフトおよびバッファを制御するためのロジ
ック回路に供給されている低電圧の電圧が低下すると、
高電圧1M、源に接続さ1また出カトランジスタがオン
状態のままであるため、出力トランジスタに接続された
発熱素子が無制御状態で作動することとなり、印字ミス
および過電流による破壊となることがあ“す、重大な欠
陥となっていた。
In conventional thermal head drive circuits, when the low voltage supplied to the logic circuit for level shift and buffer control decreases,
Since the output transistor is connected to a high voltage 1M source and remains in the on state, the heating element connected to the output transistor will operate in an uncontrolled state, resulting in printing errors and destruction due to overcurrent. However, it turned out to be a serious flaw.

本発明は、以上のような欠点をすみやかに除去するため
の極めて効果的な手段を提供することを目的とするもの
で、特に、低電圧系のロジック回路に接続Δれたゲート
回路と、このゲート回路の出力に接続さ7′1.タレベ
ルシフト回路と、このレベルシフト回路の出力に接続さ
itだ出力トランジスタと、前記ゲート回路に接続され
た電源切換回路と、この電源切換回路に接続された降圧
回路と、前記低電圧系ロジック回路と前記電源切換回路
に供給される低電圧を入力する低’r1c圧入力端子と
、前記降圧回路に供給される高電圧を入力する縮重圧入
力端子とを備え、前記低電圧入力端子よυ供給される低
電圧の電圧が低下しf?−、S合、低電圧電源用重圧t
ω出回路がこのことを検出して信号を出力し、この信号
により前記電源切換回路が切換わシ、前記ゲート回路に
前記降圧回路からの低電圧が供給されると共に、前記ゲ
ート回路の出力がLレベルとなり前記出力トランジスタ
をオフ状態にするようにした構成である。
The present invention aims to provide extremely effective means for quickly eliminating the above-mentioned drawbacks, and in particular, it is an object of the present invention to provide extremely effective means for quickly eliminating the above-mentioned drawbacks. Connected to the output of the gate circuit 7'1. a level shift circuit, an output transistor connected to the output of the level shift circuit, a power supply switching circuit connected to the gate circuit, a step-down circuit connected to the power supply switching circuit, and the low voltage logic a low voltage input terminal for inputting the low voltage supplied to the circuit and the power supply switching circuit, and a degenerate voltage input terminal for inputting the high voltage supplied to the step-down circuit, and υ from the low voltage input terminal. The voltage of the supplied low voltage decreases and f? -, S combination, heavy pressure t for low voltage power supply
The ω output circuit detects this and outputs a signal, and this signal causes the power supply switching circuit to switch, supplying the gate circuit with the low voltage from the step-down circuit, and causing the output of the gate circuit to change. This configuration is such that the output transistor becomes L level and turns off the output transistor.

以下、図面と共に本発明による二電源形印字素子駆動用
集積回路の好適な実施例について詳細に説明する。
Hereinafter, preferred embodiments of the dual power supply type printing element driving integrated circuit according to the present invention will be described in detail with reference to the drawings.

図面において、符号1で示されるものは低電圧入力端子
2より供給される低電圧で駆動される低電圧系(+57
)のロジック回路であり、このロジック回路1の各出力
はNANDゲート回路6の各入力が端子5a、5bに入
力されている。
In the drawings, the reference numeral 1 indicates a low voltage system (+57
), and each output of this logic circuit 1 is inputted to each input of a NAND gate circuit 6 to terminals 5a and 5b.

このゲート回路5の出力はレベルシフトおよびバンファ
回路4に接続され、このレベルシフトおよびバンファ回
路4の出力はN形MO8)ランジスタからなる出力トラ
ンジスタ5のゲートに接続されている。この出力トラン
ジスタ5のソースは接地されているとともに、そのドレ
インはサーマルヘフド(図示せず)を構成する発熱素子
6に接続され、この発熱索子6の他端6aには発熱体躯
動電源が接続されている。
The output of this gate circuit 5 is connected to a level shift and bumper circuit 4, and the output of this level shift and bumper circuit 4 is connected to the gate of an output transistor 5 consisting of an N-type MO transistor. The source of this output transistor 5 is grounded, and its drain is connected to a heating element 6 constituting a thermal head (not shown), and the other end 6a of this heating cord 6 is connected to a power source for driving the heating element. ing.

ゲート回路5には、ゲート電源ライン7dとして電源切
換回路7の出力端子7aが接続されており、との電源切
換回路7の第1端子7bには、高電圧入力端子20に接
続された降圧回路8が接続されている。
The output terminal 7a of the power supply switching circuit 7 is connected to the gate circuit 5 as a gate power supply line 7d, and the step-down circuit connected to the high voltage input terminal 20 is connected to the first terminal 7b of the power supply switching circuit 7. 8 are connected.

電源切換回路7は、図面には示されていないが、公知の
電子切換回路より構成されており、その作動を制御する
ために、高電圧電源入力端子20に接続された低電圧電
源用電圧検出回路9が接続されていると共に、この低電
圧電源用電圧検出回路9には低電圧入力端子2より低電
圧が供給されている。
Although not shown in the drawing, the power supply switching circuit 7 is composed of a known electronic switching circuit, and in order to control its operation, a low voltage power supply voltage detection circuit connected to the high voltage power supply input terminal 20 is used. A circuit 9 is connected to the low voltage power supply voltage detection circuit 9, and a low voltage is supplied from the low voltage input terminal 2.

さらに、低電圧入力端子2より電源ライン10を経て低
電圧系のロジック回路1に低電圧が供給畑九でいると共
に、ロジック回路1の他方の出力すなわち、ゲート回路
5の他方の入力端子6bには抵抗RLが接地されている
。又、レベルシフトおよびバンファ回路4には、高電圧
が高電圧入力端子20より供給されている。
Further, a low voltage is supplied from the low voltage input terminal 2 to the low voltage logic circuit 1 via the power line 10, and the other output of the logic circuit 1, that is, the other input terminal 6b of the gate circuit 5 is supplied with a low voltage. The resistor RL is grounded. Further, a high voltage is supplied to the level shift and bumper circuit 4 from a high voltage input terminal 20.

以上のような構成において、本発明による二電源形印字
素子駆動用集積回路を作動させる場合について述べると
、低電圧入力端子2より低電圧および高電圧電源入力端
子20よυ高電圧を供給することによυ、低電圧電源用
電圧検出回路9が作動して電源切換回路7の出力端子7
aが第2端子7cと接続しているため、低電圧(+5V
)がケート回路5およびロジック回路1に供給され、ロ
ジック回路1からは、各々正常な信号が出ているためゲ
ート回路6が作動し、レベルシフトおよびバンファ回路
4を介しで出力トランジスタ5がオン又はオフと表り、
ロジック回路1の信号出力に応じて発熱索子60オン、
オフが正常に行なわれている。
In the above configuration, when operating the dual power supply type printing element driving integrated circuit according to the present invention, a low voltage is supplied from the low voltage input terminal 2 and a high voltage υ is supplied from the high voltage power supply input terminal 20. , the voltage detection circuit 9 for low voltage power supply is activated and the output terminal 7 of the power supply switching circuit 7 is activated.
Since a is connected to the second terminal 7c, a low voltage (+5V
) is supplied to the gate circuit 5 and the logic circuit 1, and since each normal signal is output from the logic circuit 1, the gate circuit 6 is activated, and the output transistor 5 is turned on or off via the level shift and bumper circuit 4. It says off,
The heating cord 60 is turned on according to the signal output of the logic circuit 1,
Turning off is performed normally.

しかしながら、低電圧入力端子2よυ供給される低電圧
の電圧力低下した場合には、ロジック回路1には電源が
供給されなくなり、低電圧電源用電圧検出回路9が作動
しないため、電源切換回路7の出力端子7aが第1端子
7′bと接続するように切換えられ、高電圧を降圧回路
8で降圧して得られた低11i、川がゲートTiL 6
1ライン7dを経てロジック回路5に供給g、f+て、
ロジック回路5のみは作動を継続することができる。
However, when the voltage of the low voltage supplied to the low voltage input terminal 2 drops, power is no longer supplied to the logic circuit 1 and the low voltage power supply voltage detection circuit 9 does not operate, so the power supply switching circuit The output terminal 7a of 7 is switched to be connected to the first terminal 7'b, and the low voltage 11i obtained by stepping down the high voltage by the step-down circuit 8 is connected to the gate TiL 6.
G, f+ are supplied to the logic circuit 5 via one line 7d,
Only logic circuit 5 can continue to operate.

この場合、ロジック回路5の他方の入力端子5bに接続
6J1−だ抵抗器RLの端子電圧が、低電圧14’i、
 帥2のオフと連動してLレベルになるため、ロジック
回路5の出力はbレベルとなり、出力トランジスタ5が
オフとなることによって、発熱素子6 V、J、通電さ
れず、破壊されることはなくなるものである。
In this case, the terminal voltage of the resistor RL connected to the other input terminal 5b of the logic circuit 5 is the low voltage 14'i,
Since the output of the logic circuit 5 goes to the B level in conjunction with the turning off of the transistor 2, the output transistor 5 turns off, so that the heating element 6 is not energized (V, J) and will not be destroyed. It is something that will disappear.

本発明による二、電源形印字駆動用集積回路は、以上の
ような構成と作用とを備えているため、たとえ低毛用入
力端子2より供給される低電圧の電圧が低下してロジッ
ク回路が作動しなくなった場合でも、別の高圧を降圧し
た低電圧により、ゲート回路のみは正常に作動すること
ができ、そhによって、出力トランジスタの誤動作を防
止することができるので、印字ミスおよび発熱素子の破
壊は極めて個実に防止されるものである。
2. The power supply type printing drive integrated circuit according to the present invention has the above-described configuration and operation, so even if the low voltage supplied from the low voltage input terminal 2 decreases and the logic circuit is Even if it stops working, the gate circuit can still operate normally using the low voltage that is obtained by stepping down another high voltage, which prevents the output transistor from malfunctioning, thereby preventing printing errors and heating elements. destruction is something that can be prevented in a very specific way.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は、本発明による一、7H源形サーマルヘッド駆動
集積回路を示すための同略図である。 1はロジック回路、 2は低重圧入力端子、5はゲート
回路、 58.5btd入力端そ、4はレベルシフトお
よびバッファ回路、5は出力トランジスタ、6 I;l
:発熱素子。 7は電源切換回路、8は降圧回路、 9は低電圧1′A源用電圧検出回路、 10は電源ライン、20は高屈、圧入力婬子、である。 以 上 出願人 株式会社・第二精工舎 代理人 弁理士 最 上 務
The drawing is a schematic diagram showing a 1.7H type thermal head driving integrated circuit according to the present invention. 1 is a logic circuit, 2 is a low voltage input terminal, 5 is a gate circuit, 58.5btd input terminal, 4 is a level shift and buffer circuit, 5 is an output transistor, 6 I;
:Heating element. 7 is a power supply switching circuit, 8 is a step-down circuit, 9 is a voltage detection circuit for a low voltage 1'A source, 10 is a power supply line, and 20 is a high-voltage, press-in connector. Applicant: Daini Seikosha Co., Ltd. Agent: Patent Attorney Mogami

Claims (1)

【特許請求の範囲】[Claims] 低電圧系のロジック回路と、このロジック回路の出力に
接続されたゲート回路と、このゲート回路の一方の入力
端子に設けらiまた接地抵抗と、前額ルゲート回路の出
力に接続されたレベルシフトおよびバッファ回路と、こ
のレベルシフトおよびバノノア回路の出力に接続された
出力トランジスタと、前記ゲート回路に接Heされた゛
電源切換回路と、前記市詠切喚回路と前記ロジック回路
と低屯圧電源用11L圧検出回路に供給される低11y
圧を入力する低電用入力端子と、前記レベルシフトおよ
びバッファ回路と降圧1す1路に供給さノするMiJ記
低電圧よυも向い′電圧を有する高電圧を入力する高電
圧入力端子と、前記電源切換回路に接続された前記低電
圧電源用電圧検出回路とを備え、前記低電圧入力端子よ
り供給される前記低′tに圧の′t11、圧の電圧が低
下し牟場合、前記低電圧電源用電圧検出回路により検出
して前記電源切換回路が切遺り、前記ゲート回路に前記
降圧回路からの低電圧が供給さノすると共に、前記ゲー
ト回路の出力がLレベルとなり前記出力トランジスタを
オフ状態にするように構
A low voltage logic circuit, a gate circuit connected to the output of this logic circuit, a grounding resistor provided at one input terminal of this gate circuit, and a level shift connected to the output of the front gate circuit. and a buffer circuit, an output transistor connected to the output of the level shift and Vanonoa circuit, a power supply switching circuit connected to the gate circuit, the city switching circuit, the logic circuit, and a low voltage power supply. Low 11y supplied to 11L pressure detection circuit
a low current input terminal for inputting voltage, and a high voltage input terminal for inputting a high voltage having a voltage opposite to the low voltage MiJ supplied to the level shift and buffer circuit and the step-down circuit. , the voltage detection circuit for the low voltage power supply connected to the power supply switching circuit; Detected by the voltage detection circuit for low voltage power supply, the power supply switching circuit is turned off, and the low voltage from the step-down circuit is supplied to the gate circuit, and the output of the gate circuit becomes L level and the output transistor is configured to turn off.
JP58149028A 1983-08-15 1983-08-15 Integrated circuit for driving double power source printing element Granted JPS6040263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58149028A JPS6040263A (en) 1983-08-15 1983-08-15 Integrated circuit for driving double power source printing element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58149028A JPS6040263A (en) 1983-08-15 1983-08-15 Integrated circuit for driving double power source printing element

Publications (2)

Publication Number Publication Date
JPS6040263A true JPS6040263A (en) 1985-03-02
JPH0373477B2 JPH0373477B2 (en) 1991-11-21

Family

ID=15466087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58149028A Granted JPS6040263A (en) 1983-08-15 1983-08-15 Integrated circuit for driving double power source printing element

Country Status (1)

Country Link
JP (1) JPS6040263A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5985078U (en) * 1974-06-04 1984-06-08 コルモ−ゲン・コ−ポレイシヨン DC motor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848449U (en) * 1981-09-29 1983-04-01 富士通株式会社 Thermal printing head protection circuit in thermal recording equipment
JPS5964374A (en) * 1982-10-05 1984-04-12 Sanyo Electric Co Ltd Apparatus for driving thermal head

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848449B2 (en) * 1980-04-21 1983-10-28 日本鋼管株式会社 silo

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848449U (en) * 1981-09-29 1983-04-01 富士通株式会社 Thermal printing head protection circuit in thermal recording equipment
JPS5964374A (en) * 1982-10-05 1984-04-12 Sanyo Electric Co Ltd Apparatus for driving thermal head

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5985078U (en) * 1974-06-04 1984-06-08 コルモ−ゲン・コ−ポレイシヨン DC motor

Also Published As

Publication number Publication date
JPH0373477B2 (en) 1991-11-21

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