JPS6039851A - Device with solder bump - Google Patents
Device with solder bumpInfo
- Publication number
- JPS6039851A JPS6039851A JP14808983A JP14808983A JPS6039851A JP S6039851 A JPS6039851 A JP S6039851A JP 14808983 A JP14808983 A JP 14808983A JP 14808983 A JP14808983 A JP 14808983A JP S6039851 A JPS6039851 A JP S6039851A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor device
- solder bumps
- wiring board
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
イ発明は、配線基板へ接続するためのはんだバンプを有
する装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a device having solder bumps for connection to a wiring board.
以下、はんだバンプを有する装置として半導体装置を例
に挙げて説明する。しかし、本発明はこれに限定される
ことなくはんだバンプを有するすべての装置に適用でき
る。Hereinafter, a semiconductor device will be described as an example of a device having solder bumps. However, the present invention is not limited thereto and can be applied to any device having solder bumps.
半導体装置を配線基板に接続する方法に、はんだリフロ
ー法がある。この方法は、第１図に示すように、半導体
装置２の接続用端子（図示ぜず）にはんだバンプ４をあ
らかじめ接続形成しておき、配線基板６の面上に形成さ
れた接続端子８とこのはんだバンプ４との位置を合わせ
た後、はんだバンプ４のはんだを加熱溶融させ、該はん
だバング４と接続端子８とが金属的に接合することによ
り、半導体装置２を配線基板６に接続するものである。A solder reflow method is a method for connecting a semiconductor device to a wiring board. In this method, as shown in FIG. 1, solder bumps 4 are connected in advance to connection terminals (not shown) of a semiconductor device 2, and then solder bumps 4 are connected to connection terminals 8 formed on the surface of a wiring board 6. After aligning with the solder bumps 4, the solder of the solder bumps 4 is heated and melted, and the solder bumps 4 and the connection terminals 8 are metallically joined, thereby connecting the semiconductor device 2 to the wiring board 6. It is something.
この接続法に用いられる半導体装置２のはんだバンプ４
は、半導体装置２の表面に形成された接続端子すなわち
接続パターン上に真空蒸着法、めっき法、あるいは厚膜
ペースト印刷法によってはんだを供給し、その後でとの
はんだを加熱溶融させて該はんだが前記接続パターンに
金属接合することにょ多形成される。このため、加熱溶
融後のはんだバンプ４は先端部が自然球体形状になり、
この形状のまま凝固する。つまり、従来のはんだバング
４の先端部の形状は、第１図に示すようビ、球体形状の
一部を有した形状になっている。このことから、従来技
術においては次のような欠点があった。Solder bumps 4 of the semiconductor device 2 used in this connection method
In this method, solder is supplied onto the connection terminals or connection patterns formed on the surface of the semiconductor device 2 by vacuum evaporation, plating, or thick film paste printing, and then the solder is heated and melted. A plurality of layers are formed by metal bonding to the connection pattern. Therefore, the tip of the solder bump 4 after heating and melting has a natural spherical shape,
It solidifies in this shape. In other words, the tip of the conventional solder bang 4 has a partially spherical shape as shown in FIG. For this reason, the conventional technology has the following drawbacks.
すなわち、配線基板６と半導体装置２とを位置合わせす
る場合、両者の接続部となるはんだバンプ４と接続端子
８はいずれも非常に微小であるから、両者に照明光を当
ててＴＶカメラで撮像し、その像を拡大して、その相対
位置を認識する方法がとられている。ところが、前述の
ように、従来のはんだバンプ４の先端は球体形状をして
いるので、はんだバンプ４の表面に投射した照明光は一
方向に反射せず、反射光が広がってしまうため、ＴＶ
カメラに入る光が弱くなシ、はんだバンプ４の位置認識
が困難であった。That is, when aligning the wiring board 6 and the semiconductor device 2, since the solder bumps 4 and the connection terminals 8, which are the connection parts between the two, are both very small, illumination light is applied to them and the images are taken with a TV camera. However, a method is used to enlarge the image and recognize its relative position. However, as mentioned above, since the tip of the conventional solder bump 4 has a spherical shape, the illumination light projected onto the surface of the solder bump 4 is not reflected in one direction, but the reflected light spreads out.
Since the light entering the camera was weak, it was difficult to recognize the position of the solder bump 4.
さらに、はんだバンプ４を介して半導体装置２を配線基
板６にはんだ接続する際は、あらかじめ配線基板６の接
続端子８上にはんだを置くいわゆる迎えはんだを行なう
が、この迎えはんだを行なった接続端子８の上面は、第
１図に示すように中央がふくらんだ球面状になシ非常に
滑らかな状態になることから、この球面状の接続端子８
上に先端の丸いはんだバンプを載置すると、はんだバン
プ４と接続端子８間に滑シを生じて両者の位置ずれが起
きて、正確な位置合わせができなかった。したがって、
このことに基因してはんだバンプを有する装置と配線基
板との接続不良が生ずる不都合があった。Furthermore, when the semiconductor device 2 is soldered to the wiring board 6 via the solder bumps 4, so-called pick-up soldering is performed in which solder is placed on the connection terminals 8 of the wiring board 6 in advance. As shown in Fig. 1, the top surface of the connection terminal 8 has a spherical shape with a bulge in the center and is very smooth.
When a solder bump with a round tip was placed on top, slippage occurred between the solder bump 4 and the connection terminal 8, causing a misalignment between the two, making accurate positioning impossible. therefore,
Due to this, there is an inconvenience that a connection failure occurs between a device having solder bumps and a wiring board.
本発明の目的は、上記の欠点をなくシ、微小なはんだバ
ンプの位置を光学的に鮮明に認識することができると共
に、迎えはんだを行なった接続端子上にはんだバンプを
置いても位置のずれを防止することができ、配線基板上
に正確に位置を合わせてはんだ接続ができるはんだバン
プを有する装置を提供するにある。It is an object of the present invention to eliminate the above-mentioned drawbacks, to make it possible to optically clearly recognize the position of minute solder bumps, and to prevent misalignment of solder bumps even if they are placed on connection terminals that have been soldered. It is an object of the present invention to provide a device having solder bumps that can be accurately positioned and solder connected on a wiring board.
要するに、本発明は、はんだバングの先端を平坦にする
ことにより、この平坦部が光学系における照明光を一方
向に反射させて反射光が広がるのを防ぎ、さらに配線基
板の接続端子上への載置に際しては、はんだバンプの滑
りを防止するようにしたものである。In short, by making the tip of the solder bang flat, this flat part reflects the illumination light in the optical system in one direction, preventing the reflected light from spreading, and further prevents the reflected light from spreading onto the connection terminal of the wiring board. When placed, the solder bumps are prevented from slipping.
以下、図面を用いて本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図は本発明のはんだバンプを有する装置を示す概略
図である。この図に示すように、本実施例においては、
はんだバンプを有する装置の一例としての半導体装置１
０の表面に複数のはんだバンプ１２が形成されており、
該はんだバンプ１２の先端には平坦部１４が設けられて
いる。FIG. 2 is a schematic diagram illustrating an apparatus with solder bumps according to the present invention. As shown in this figure, in this example,
Semiconductor device 1 as an example of a device having solder bumps
A plurality of solder bumps 12 are formed on the surface of 0,
A flat portion 14 is provided at the tip of the solder bump 12 .
第３図は第２図に示した本発明のはんだバンプを有する
装置を配線基板上に位置合わせして載置する装置の一例
を示す説明図である。この図において、第２図に示した
はんだバンプを有する装置すなわち半導体装置１０が矢
印入方向に移動可能な吸引ノズル１６によって吸引保持
されている。半導体装置１０を接続すべき配線基板６０
表面には接続端子８が形成されておシ、半導体装置１０
の下方に位置してテーブル２２の上に載置されている。FIG. 3 is an explanatory diagram showing an example of an apparatus for aligning and mounting the apparatus having solder bumps of the present invention shown in FIG. 2 on a wiring board. In this figure, the device having the solder bumps shown in FIG. 2, ie, the semiconductor device 10, is suction-held by a suction nozzle 16 movable in the direction of the arrow. Wiring board 60 to which semiconductor device 10 is to be connected
Connection terminals 8 are formed on the surface of the semiconductor device 10.
It is placed on the table 22 below.
この半導体装置１０と配線基板６との間には、反射面２
４と２６を有する反射鏡２８が設置されており、この反
射鏡は矢印Ｂ方向に移動可能である。照明ランプ６０か
ら出た照明光３２６４は、ハーフミラ−３６を通過して
反射面２４で反射され、半導体装置１ｏの下面を照明す
る。また、照明ランプ３８から出た照明光４０ 、４２
は、ハーフミラ−４４を通過して反射面２６で反射され
、配線基板６の上面を照明する。ＴＶ右カメラ６は、反
射面２４およびハーフミラ−３６で反射されてきた半導
体装置１００表面の像を撮像し、図、示しないＴＶモニ
タにその像を映し出す。同様に、ＴＶカメラ４８は、反
射面２６およびハーフミラ−４４で反射されてきた配線
基板６０表面の像を撮像し、前記ＴＶモニタにその像を
前記半導体装置１ｏの像と重ね合わせて映し出す。A reflective surface 2 is provided between the semiconductor device 10 and the wiring board 6.
A reflector 28 having numbers 4 and 26 is installed and is movable in the direction of arrow B. Illumination light 3264 emitted from the illumination lamp 60 passes through the half mirror 36 and is reflected by the reflective surface 24, illuminating the lower surface of the semiconductor device 1o. In addition, illumination lights 40 and 42 emitted from the illumination lamp 38
passes through the half mirror 44 and is reflected by the reflective surface 26, illuminating the upper surface of the wiring board 6. The TV right camera 6 captures an image of the surface of the semiconductor device 100 reflected by the reflective surface 24 and the half mirror 36, and displays the image on a TV monitor (not shown). Similarly, the TV camera 48 captures an image of the surface of the wiring board 60 that has been reflected by the reflective surface 26 and the half mirror 44, and displays the image on the TV monitor in a superimposed manner with the image of the semiconductor device 1o.
このような構成の装置において、作業者はＴＶモニタ上
に写し出された半導体装置１ｏと配線基板６の像を目視
しながら、ＴＶモニタ上で、半導体装置１０のはんだバ
ンプ１２と配線基板乙の接続端子８が重なるように、テ
ーブル２２を移動あるいは回転させる。ＴＶモニタ上で
はんだバンプ１２と接続端子８が重なれば、テーブル２
２の移動を停止させて位置合わせを完了する。その後、
反射光２８を矢印Ｂ方向に移動させ、次に吸引ノズル１
６を矢印Ａ方向に押し下げて、半導体装置１０を配線基
板６上に載置し、吸引ノズル１６の吸引を解除すること
によシ、半導体装置１０は配線基板６の位置合わせした
箇所に設置さる。前記位置合わせにおいて、照明ランプ
３０からの照明光３２ 、３４は、はんだバンプ１２を
真下から照明するが、。In an apparatus having such a configuration, an operator visually observes the images of the semiconductor device 1o and the wiring board 6 projected on the TV monitor, and connects the solder bumps 12 of the semiconductor device 10 and the wiring board B on the TV monitor. The table 22 is moved or rotated so that the terminals 8 overlap. If the solder bump 12 and the connection terminal 8 overlap on the TV monitor, the table 2
The movement of step 2 is stopped to complete the alignment. after that,
The reflected light 28 is moved in the direction of arrow B, and then the suction nozzle 1
6 in the direction of arrow A, place the semiconductor device 10 on the wiring board 6, and release the suction of the suction nozzle 16, so that the semiconductor device 10 is installed at the aligned position on the wiring board 6. . During the alignment, the illumination lights 32 and 34 from the illumination lamp 30 illuminate the solder bumps 12 from directly below.
本発明においてははんだバンプ１２の先端が平坦にされ
ているので、照明光３２ 、５４はこの平坦部１４にて
完全に真下に反射されてくる。このことによシ、はんだ
バンプ１２の像を鮮明にＴＶ右カメラ６に送ることがで
き、ＴＶモニタに鮮明な像を映し出すことができる。In the present invention, since the tips of the solder bumps 12 are flattened, the illumination lights 32 and 54 are completely reflected directly downward at the flat portions 14. As a result, a clear image of the solder bump 12 can be sent to the TV right camera 6, and a clear image can be displayed on the TV monitor.
第４図および第５図は本発明による別の効果を説明する
ための図である。第４図は従来のはんだバンプ形状を有
する装置の配線基板への載置状態を示す図で、前にも述
べたが、半導体装置２０表面には先端が自然球体形状を
したはんだバンプ４が形成されている。また、配線基板
６０表面には接続端子８が形成されておシ、前述のよう
にその上面には迎えはんだ付によって付着したはんだ膜
９がある。このような構成において、はんだバンプ４の
丸い先端とはんだ膜９が接触する状態で半導体装置２を
載置すると、はんだ膜９の上面は中央がふくらんだ球状
になっておシ、かつ滑シ易い面であるので、図中の破線
で示したように半導体装置２は矢印Ｃ方向に滑ってしま
い正確な位置合わせができない。FIGS. 4 and 5 are diagrams for explaining another effect of the present invention. FIG. 4 is a diagram showing a state in which a device having a conventional solder bump shape is mounted on a wiring board. As mentioned earlier, solder bumps 4 with natural spherical tips are formed on the surface of the semiconductor device 20. has been done. Further, connection terminals 8 are formed on the surface of the wiring board 60, and as described above, there is a solder film 9 attached to the upper surface by pick-up soldering. In such a configuration, if the semiconductor device 2 is placed in a state where the round tips of the solder bumps 4 and the solder film 9 are in contact with each other, the upper surface of the solder film 9 becomes spherical with a bulge in the center and easily slips. Since the semiconductor device 2 is a flat surface, the semiconductor device 2 slides in the direction of arrow C, as shown by the broken line in the figure, and accurate positioning cannot be achieved.
これに対し、本発明によるはんだバンプを有する装置に
おいては、第５図に示すように、はんだバンプ１２の先
端に平坦部１４が形成しであるので、半導体装１＃（，
１０が滑って位置ずれを起こすのを防止でき、正確に位
置合わせして載置することが可能である。On the other hand, in the device having solder bumps according to the present invention, as shown in FIG.
10 can be prevented from slipping and becoming misaligned, and can be accurately positioned and placed.
なお、本発明になるはんだバンプの先端に平坦部を形成
するには、はんだを再溶融させた状態で、はんだバンプ
上面に平らな板を押し付けることによシ容易に形成する
ことができる。Note that a flat portion can be easily formed at the tip of the solder bump according to the present invention by pressing a flat plate onto the top surface of the solder bump while the solder is remelted.
〔発明の効果）
以上説明したように、本発明によれば、はんだバンプの
先端に平坦部を設けたので、当該半導体装置を配線回路
に接続する際、照明光が一方向に反射して反射光が広が
らないので、はんだバンプの位置認識を非常に鮮明に行
なえるため、誤認識による接続不良を皆無にすることが
可能である。また、従来ははんだ・（ンプ像の認識が鮮
明に行なえないため、はんだ）くンプを有する装置を位
置合わせして載置することの自動化は不可能とされてい
たが、本発明により容易に自動化ができるようになった
。さらに、従来載置時にはんだバングを有する装置が滑
って位置ずれを起こし、接続不良を発生していたが、本
発明により位置ずれの完全防止が達成され、接続不良を
無くすことができた。このように本発明の効果は顕著で
ある。[Effects of the Invention] As explained above, according to the present invention, since a flat portion is provided at the tip of a solder bump, when connecting the semiconductor device to a wiring circuit, illumination light is reflected in one direction and reflected. Since the light does not spread, the position of the solder bump can be recognized very clearly, and connection failures due to erroneous recognition can be completely eliminated. In addition, in the past, it was considered impossible to automate the alignment and placement of a device with solder bumps because the solder bump image could not be clearly recognized. Automation is now possible. Further, conventionally, when placed, a device having solder bangs slipped and misaligned, resulting in poor connections, but with the present invention, misalignment can be completely prevented, and poor connections can be eliminated. As described above, the effects of the present invention are remarkable.
第１図は従来のはんだバンプを有する装置を配線基板に
接続する際の両者の位置関係を示す断面図、第２図は本
発明のけんだノ（ンプを有する装置の断面図、第３図は
本発明のけんだ）（ンプを有する装置を配線基板へ位置
を合わせて載置する装置の説明図、第４図および第５図
ははんだバンプを有する装置を配線基板上に載置した状
態を示す断面図である。
２．１０・・・半導体装置、４．１２・はんだ）（ンプ
、６・・・配線基板、 ８ 接続端子、
９ はんだ膜、 １４・・平坦部、
２８ 反射鏡、 ６０．ろ８ 照明ランプ、５６ 、４
４・・・ハーフミラ−１４６、４８・ Ｅ’Ｖカメラ、
第 ／ 層
鳩 ２ 図
７θ
第 ３２FIG. 1 is a sectional view showing the positional relationship between a conventional device having solder bumps and a wiring board, FIG. 2 is a sectional view of a device having solder bumps according to the present invention, and FIG. Figures 4 and 5 are explanatory diagrams of a device for aligning and placing a device having solder bumps on a wiring board, and Figures 4 and 5 show a state in which a device having solder bumps is placed on a wiring board. 2.10... Semiconductor device, 4.12. Solder) (amplifier, 6... Wiring board, 8 Connection terminal, 9 Solder film, 14... Flat part, 28 Reflector, 60.ro8 lighting lamp, 56, 4
4...half mirror 146, 48・E'V camera,
32nd / Layer Pigeon 2 Figure 7θ 32nd
Claims (1)
において、前記はんだバンプの先端に平坦部を設けたこ
とを特徴とするはんだバンプを有する装置、。1. A device having a solder bump connected to a terminal of a wiring board, characterized in that a flat portion is provided at the tip of the solder bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14808983A JPS6039851A (en) | 1983-08-15 | 1983-08-15 | Device with solder bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14808983A JPS6039851A (en) | 1983-08-15 | 1983-08-15 | Device with solder bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6039851A true JPS6039851A (en) | 1985-03-01 |
Family
ID=15444985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14808983A Pending JPS6039851A (en) | 1983-08-15 | 1983-08-15 | Device with solder bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6039851A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102457660A (en) * | 2010-10-25 | 2012-05-16 | 致伸科技股份有限公司 | Assembling method of camera module |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5099269A (en) * | 1973-12-28 | 1975-08-06 |
-
1983
- 1983-08-15 JP JP14808983A patent/JPS6039851A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5099269A (en) * | 1973-12-28 | 1975-08-06 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102457660A (en) * | 2010-10-25 | 2012-05-16 | 致伸科技股份有限公司 | Assembling method of camera module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6062460A (en) | Apparatus for producing an electronic circuit | |
| KR20080040789A (en) | Automated optical inspection system | |
| US5741410A (en) | Apparatus for forming spherical electrodes | |
| JPS6039851A (en) | Device with solder bump | |
| KR100321327B1 (en) | Apparatus for attaching flexible print circuit and method thereof | |
| JPH0626227B2 (en) | How to attach a semiconductor chip | |
| KR101050842B1 (en) | Device for inspection of poor welding position and determination method for determining bad welding position thereof | |
| JPH0870013A (en) | Method and apparatus for bonding | |
| JP2635755B2 (en) | Electronic component positioning device | |
| JP2004014698A (en) | Simple mounter | |
| JP3254956B2 (en) | Bonding method | |
| JPH04340240A (en) | Structure for connecting ic chip | |
| JPS6339118B2 (en) | ||
| JP2885404B2 (en) | Crimping method and device | |
| JP3370419B2 (en) | Positioning method for mounting electronic components on circuit boards | |
| JPH04370945A (en) | Method and apparatus for face down bonding | |
| CN101490591A (en) | Mounting an electro-optical component in alignment with an optical element | |
| JP2002076602A (en) | Method for mounting chip of display board | |
| JPH10320054A (en) | Chip component mounting device and positioning method for chip component and circuit board by chip component mounting device | |
| JP2004022881A (en) | Method and apparatus for positioning component | |
| JP2755726B2 (en) | Position recognition device and mounting device | |
| JPH03263338A (en) | Inner lead bonder | |
| JPH11145193A (en) | Method for forming soldered bump | |
| KR19990018439A (en) | Component Inspection Device | |
| JPH08227162A (en) | Production of printed wiring board |