JPS6039263A - System for informing and processing fault detailed information - Google Patents

System for informing and processing fault detailed information

Info

Publication number
JPS6039263A
JPS6039263A JP58147413A JP14741383A JPS6039263A JP S6039263 A JPS6039263 A JP S6039263A JP 58147413 A JP58147413 A JP 58147413A JP 14741383 A JP14741383 A JP 14741383A JP S6039263 A JPS6039263 A JP S6039263A
Authority
JP
Japan
Prior art keywords
channel
detailed information
central processing
processing unit
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58147413A
Other languages
Japanese (ja)
Inventor
Kazutaka Sasaki
和孝 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58147413A priority Critical patent/JPS6039263A/en
Publication of JPS6039263A publication Critical patent/JPS6039263A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To relieve the load of a central controller by allowing a channel to store fault detailed information on the channel to an address location on a main storage device to allow the channel to give a command sensing the fault detailed information to the central controller. CONSTITUTION:The system consists of the central processing unit, a storage device 2, a channel 3 and an input/output device 4 and the channel 3 controls the data transfer between the storage device 2 and the device 4. The channel 3 interrupts the unit check to the unit 1 in case of generation of an fault at the device 4. Fault detailed information corresponding to generation of fault is stored in a buffer 6 on the channel 3. The channel 3 stores the fault detailed information to the address location on the storage device 2 and after the storage is performed, the sensing of the fault detailed information of the storage device 2 is commanded to the unit 1 to apply unit check interruption thereby relieving the load of the unit 1.

Description

【発明の詳細な説明】 囚　発明の技術分野 本発明は、障害詳細情報通知処理方式、特に入出力装置
側における障害発生に対応する障害詳細情報通知に轟っ
て、チャネルが当該詳細情報を主記憶装置上にストアし
ておいて、二二ツ）−チェック割込みを発するよう構成
し、従来のセンス指令を省略できるようにした障害詳細
情報通知処理方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a failure detailed information notification processing method, in particular, a failure detailed information notification corresponding to the occurrence of a failure on the input/output device side, and a channel mainly transmits the detailed information. The present invention relates to a failure detailed information notification processing method that is configured to store on a storage device and issue a check interrupt, thereby omitting the conventional sense command.

（Ｂｌ　技術の背景と問題点 従来から、データ処理システムにおいては、中央処理装
置と主記憶装置とチャネルとが存在しており、中央処理
装置がチャネルに対してスタートＩ１０指令を発した状
態の後に入出力装置側において障害が発生すると９次の
如く処理されていた。(Bl Technological Background and Problems Conventionally, a data processing system has a central processing unit, a main memory, and a channel. After the central processing unit issues a start I10 command to the channel, When a failure occurs on the input/output device side, it is handled as follows.

即ち、入出力装置側からユニット・チェックが発せられ
ると、チャネルは中央処理装置に対してユニット・チェ
ック割込みを発する。これに対応して、中央処理装置は
チャネルに対してセンス指令を発し、チャネルはこれに
対応して障害詳細情報を中央処理装置に通知するように
していた。That is, when a unit check is issued from the input/output device side, the channel issues a unit check interrupt to the central processing unit. In response to this, the central processing unit issues a sense command to the channel, and the channel responds to this by notifying the central processing unit of detailed failure information.

このため、従来方式の場合には、中央処理装置やチャネ
ルに対する負荷が大となり、また中央処理装置に対する
割込み発生回数が大となっていた。For this reason, in the case of the conventional system, the load on the central processing unit and the channel becomes large, and the number of occurrences of interrupts to the central processing unit becomes large.

（Ｃ１発明の目的と構成 本発明は上記の問題点を解決することを目的としており
２本発明の障害詳細情報通知処理方式は。(C1 Object and Structure of the Invention The present invention aims to solve the above-mentioned problems. 2) The failure detailed information notification processing method of the present invention is as follows.

中央処理装置と、主記憶装置と、上記中央処理装置から
の指令に対応して入出力装置・主記憶装置間のデータ転
送を制御するチャネルとを少なくともそなえ、入出力装
置側における障害発生に対応して、上記チャネルが上記
中央処理装置に対してユニット・チェック割込みを行う
データ処理システムにおいて、上記チャネル上に上記障
害発生に対応した障害詳細情報を保持すると共に当該チ
ャネルが上記主記憶装置上のアドレス位置に当該障害詳
細情報をストアするよう構成されてなり、上記チャネル
は、上記詳細情報のストアを行った後に上記中央処理装
置に対して、上記主記憶装置上の障害詳細情報をセンス
すべき旨を指示する二ニット・チェック割込みを発する
ようにしたことを特徴としている。以下図面を参照しつ
つ説明する。It is equipped with at least a central processing unit, a main storage device, and a channel that controls data transfer between the input/output device and the main storage device in response to commands from the central processing unit, and responds to failures on the input/output device side. In a data processing system in which the channel issues a unit check interrupt to the central processing unit, detailed fault information corresponding to the occurrence of the fault is held on the channel, and the channel is The channel is configured to store the detailed failure information in the address location, and after storing the detailed information, the channel causes the central processing unit to sense the detailed failure information on the main storage device. The feature is that a two-nit check interrupt is issued to indicate this. This will be explained below with reference to the drawings.

（Ｄｌ　発明の実施例 図は本発明の一実施例処理態様を説明する説明図を示す
。図中の符号１は中央処理装置、２は主記憶装置、３は
チャネル、４は入出力制御装置。(Dl Embodiment of the Invention The figure shows an explanatory diagram for explaining the processing mode of an embodiment of the present invention. In the figure, reference numeral 1 is a central processing unit, 2 is a main storage device, 3 is a channel, and 4 is an input/output control device. .

５は障害、６は詳細情報バッファ、７は主記憶装置上の
固定アドレス位置を表わしている。5 represents a failure, 6 represents a detailed information buffer, and 7 represents a fixed address location on the main memory.

今、中央処理装置１がチャネル６に対してスター　トＩ
１０指令を発し、チャネル６が入出力制御装置を制御し
ているとする。この状態の下で、入出力装置側において
障害５が発生すると、入出力装置側からユニットｅチェ
ック発生がチャネル６に対して通知される。Now, central processing unit 1 starts I for channel 6.
10 command is issued and channel 6 is controlling the input/output control device. Under this state, when a failure 5 occurs on the input/output device side, the input/output device side notifies channel 6 that a unit e check has occurred.

本発明の場合には、従来の如くチャネル３が即刻中央処
理装置１に対してユニットφチェック割込みを行うこと
なく、チャネル３は先づ入出力装置側から障害詳細情報
をセンスしてバッファ６に保持する。そして、チャネル
６は、主記憶装置２上の固定アドレス位置７（アドレス
ＡＤＲ８）Ｋ対して、上記バッファ６の内容をストアす
る。In the case of the present invention, instead of the channel 3 immediately issuing a unit φ check interrupt to the central processing unit 1 as in the conventional case, the channel 3 first senses the detailed failure information from the input/output device side and stores it in the buffer 6. Hold. Channel 6 then stores the contents of buffer 6 at fixed address location 7 (address ADR8) K on main memory 2.

当該ストアが終了した時点において、チャネル６は、（
１）入出力装置側に障害が発生したこと、　（ＩＩ）当
該障害に対応する詳細情報が固定アドレス位置７に保持
されていること＋　（Ｉｉｔｌ中央処理装置１は当該固
定アドレス位置の内容をリードすべきことなどを指示す
る所の、いわば新しい形のユニット・チェック割込みを
、中央処理装置１に対して発する。これに対応して、中
央処理装置１は、上記固定アドレス位置７の内容をリー
ドし、障害の詳細を知り、以後の処置を決定する。At the time the store ends, channel 6 (
1) A failure has occurred on the input/output device side; (II) Detailed information corresponding to the failure is held in the fixed address location 7 + (Iitl central processing unit 1 reads the contents of the fixed address location) A so-called new type of unit check interrupt is issued to the central processing unit 1 to instruct what to do etc. In response, the central processing unit 1 reads the contents of the fixed address location 7. learn the details of the failure and decide on further treatment.

上記説明において、チャネル３が入出力装置側から障害
詳細情報を吸上げること、チャネル３が主記憶装置２に
対してストア動作を行うこと、チャネル６が中央処理装
置１に対してユニットφチェック割込みを発すること、
中央処理装置１が上記憶装］４２との内容をリードする
ことなどは、従来から周知の手段である。本発明の場合
には、チャネル６が「自律的に」詳細情報を吸上げかつ
「自律的に」主記憶装置２に対してストア動作を行うが
、これらは入出力装置側からのユニット・チェック発生
に対応して、これら動作を発動するトリガがかけられれ
ば足りる。また中央処理装置１における対応動作は、所
定の処理を実行するようプログラムを用意しておけば足
りる。In the above explanation, channel 3 collects failure detailed information from the input/output device side, channel 3 performs a store operation on main storage device 2, and channel 6 sends a unit φ check interrupt to central processing unit 1. to utter,
It is a conventionally well-known method for the central processing unit 1 to read the contents of the upper storage device 42. In the case of the present invention, the channel 6 "autonomously" retrieves detailed information and "autonomously" performs a store operation to the main storage device 2, but these are performed by a unit check from the input/output device side. It is sufficient if a trigger to activate these operations is applied in response to the occurrence. Further, for the corresponding operation in the central processing unit 1, it is sufficient to prepare a program to execute a predetermined process.

ｆＦｔｌ　発明の効果 以上鮮明した如く９本発明によれば、障害詳細情報を受
取るに当っての中央処理装置やチャネルにおける負荷が
低減される。fFtl Effects of the Invention As clearly explained above, according to the present invention, the load on the central processing unit and channels when receiving detailed failure information is reduced.

【図面の簡単な説明】 図は本発明の一実施例処理態様を説明する説明図を示す
。 図中、１は中央処理装置、２は主記憶装置、３はチャネ
ル、４は入出力制御装置、６はノ（ソファ。 ７は固定アドレス位置を表わす。 特許出願人　富士通株式会社BRIEF DESCRIPTION OF THE DRAWINGS The figure shows an explanatory diagram illustrating a processing mode of an embodiment of the present invention. In the figure, 1 is the central processing unit, 2 is the main memory, 3 is the channel, 4 is the input/output control device, 6 is the sofa. 7 is the fixed address location. Patent applicant: Fujitsu Limited

Claims (1)

【特許請求の範囲】 中央処理装置と、主記憶装置と、上記中央処理装置から
の指令に対応して入出力装置自主記憶装置間のデータ転
送を制御するチャネルとを少なくともそなえ、入出力装
置側における障害発生に対応して、上記チャネルが上記
中央処理装置に対してユニット・チェック割込みを行う
データ処理システムにおいて、上記チャネル上に上記障
害発生に対応した障害詳細情報を保持すると共に当該チ
ャネルが上記主記憶装置上のアドレス位置に当該障害詳
細情報をストアするよう構成されてなり。 上記チャネルは、上記詳細情報のストアを行った後に上
記中央処理装置に対して、上記主記憶装置上の障害詳細
情報をセンスすべき旨を指示するユニット・チェック割
込みを発するようにしたことを特徴とする障害詳細情報
通知処理方式。[Scope of Claims] The input/output device side comprises at least a central processing unit, a main storage device, and a channel for controlling data transfer between the input/output device autonomous storage devices in response to commands from the central processing unit. In a data processing system in which the channel issues a unit check interrupt to the central processing unit in response to the occurrence of a fault in The failure detailed information is stored in an address location on the main memory. The channel is characterized in that after storing the detailed information, the channel issues a unit check interrupt that instructs the central processing unit to sense the detailed failure information on the main storage device. Detailed failure information notification processing method.
JP58147413A 1983-08-12 1983-08-12 System for informing and processing fault detailed information Pending JPS6039263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58147413A JPS6039263A (en) 1983-08-12 1983-08-12 System for informing and processing fault detailed information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58147413A JPS6039263A (en) 1983-08-12 1983-08-12 System for informing and processing fault detailed information

Publications (1)

Publication Number Publication Date
JPS6039263A true JPS6039263A (en) 1985-03-01

Family

ID=15429736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58147413A Pending JPS6039263A (en) 1983-08-12 1983-08-12 System for informing and processing fault detailed information

Country Status (1)

Country Link
JP (1) JPS6039263A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61197260A (en) * 1985-02-28 1986-09-01 Toshiba Corp Mechanism for printing kana alongside chinese character kanji
JPS61154195U (en) * 1985-03-19 1986-09-24

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61197260A (en) * 1985-02-28 1986-09-01 Toshiba Corp Mechanism for printing kana alongside chinese character kanji
JPS61154195U (en) * 1985-03-19 1986-09-24

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