JPS603906U - Control circuit for tape recorder with radio - Google Patents

Control circuit for tape recorder with radio

Info

Publication number
JPS603906U
JPS603906U JP9391883U JP9391883U JPS603906U JP S603906 U JPS603906 U JP S603906U JP 9391883 U JP9391883 U JP 9391883U JP 9391883 U JP9391883 U JP 9391883U JP S603906 U JPS603906 U JP S603906U
Authority
JP
Japan
Prior art keywords
amplifier circuit
signal
headphone
output
jack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9391883U
Other languages
Japanese (ja)
Inventor
河内 恒佳
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP9391883U priority Critical patent/JPS603906U/en
Publication of JPS603906U publication Critical patent/JPS603906U/en
Pending legal-status Critical Current

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図示した回路は本考案の制御回路の一実施例であZ。 主な図番の説明1・・・第1入力端子、2・・・第2入
力端子、5・・・ヘッドフオンジャック、6・・・接地
端子、7・・・第1信号端子、8・・・第2信号端子、
9・・・第1切換端子、10・・・第2切換端子、11
・・・第1   ′スイッチ、12・・・第2スイツチ
、13・・・第1増幅回路、14・・・第2増幅回路、
15.16・・・入力信号路:、17・・・第1出力コ
ンデンサー、18・・・第2出力コンデンサー、19・
・・スピーカー、23・・・第1スイツチングトランジ
スター、26・・・第2スイツチングトランジスター、
27・・・制御トランジスター、28・・・録音再生切
換スイッチ、30・・・選択スイッチ。
The illustrated circuit is one embodiment of the control circuit of the present invention. Explanation of main drawing numbers 1...First input terminal, 2...Second input terminal, 5...Headphone jack, 6...Ground terminal, 7...First signal terminal, 8... ...Second signal terminal,
9...First switching terminal, 10...Second switching terminal, 11
. . . 1st switch, 12 . . . second switch, 13 . . . first amplifier circuit, 14 . . . second amplifier circuit,
15.16... Input signal path:, 17... First output capacitor, 18... Second output capacitor, 19.
... speaker, 23 ... first switching transistor, 26 ... second switching transistor,
27... Control transistor, 28... Recording/playback selection switch, 30... Selection switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ステレオ信号の中の左チャンネルの信号が入力されると
共に該信号を増幅する第1増幅回路と、ステレオ信号の
中の右チャンネルの信号が入力されると共に該信号を増
幅する第2増幅回路と、前記第1増幅回路の出力端子及
び第2増幅回路の出力端子に夫々出力コンデンサーを介
して接続された第1及び第2の信号端子を有すると共に
ヘッドフオンプラグの挿入に伴ない前記第1及び第2信
′号端子より切離される第1及び第2の切換端子を有す
るヘッドフオンジャックと、該ヘッド7オンジヤツクへ
のへッドフオンプラグの着脱動作に連動して切換えられ
ると共にヘッドフオンプラグの非挿入時前記第1増幅回
路の入力端子に右チャンネルの信号を入力せしめる第1
スイツチと、前記ヘッド7オンジヤツクへのへッドフオ
ンプラグの着脱動作に連動して切換えられると共にヘッ
ドフオンプラグの非挿入時前記第1増幅回路及び第2増
幅回路の出力端子間に前記出力コンデンサーを介するこ
となくスピーカーを接続する第2スイツチと、前記へッ
ドフオンジャックかへッドフオンプラグの非挿入状態に
あるとき前記第1切換端子から前記第1増幅回路の出力
信号を前記第2増幅回路の反転入力端子に導き前記第1
増幅回路及び第2増幅回路をBTL動作せしめる信号径
路と、ヘッドフオンプラグの非挿入時前記へッドフオン
ジャックの第2切換端子を通して印加される直流電流に
よりバイアスされて導通すると共に前記第2増幅回路の
入力信号路を接地する第1スイツチングトランジスター
と、マイクロフォン使用による録音動作状態にあるとき
導通すると共にヘッドフオンプラグの非挿入時前記第1
スイッチ及び第1スイツチングトランジスターとの協働
により前記第1増幅回路の入力信号路を接地する第2ス
イツチングトランジスターとより成り、マイクロフォン
使用による録音動作状態記スピーカーの放音動作を阻止
し、以ってイ1ウリングの発生を防止する゛ようにした
ことを特徴吉するラジオ付テープレコーダーの制御回路
a first amplifier circuit that receives a left channel signal of the stereo signal and amplifies the signal; a second amplifier circuit that receives a right channel signal of the stereo signal and amplifies the signal; The first and second signal terminals are connected to the output terminal of the first amplifier circuit and the output terminal of the second amplifier circuit through output capacitors, respectively, and when the headphone plug is inserted, the first and second signal terminals are connected to the output terminal of the first amplifier circuit and the output terminal of the second amplifier circuit, respectively. A headphone jack having first and second switching terminals that are separated from the headphone jack and a headphone jack that is switched in conjunction with the operation of attaching and detaching the headphone plug to and from the headphone jack, and when the headphone plug is not inserted. The first amplifier circuit inputs the right channel signal to the input terminal of the first amplifier circuit.
The switch is switched in conjunction with the operation of attaching and detaching the headphone plug to the head 7 on-jack, and when the headphone plug is not inserted, the output capacitor is not connected between the output terminals of the first amplifier circuit and the second amplifier circuit. a second switch for connecting a speaker; and when the headphone jack or headphone plug is not inserted, the output signal of the first amplifier circuit is transferred from the first switching terminal to the inverting input terminal of the second amplifier circuit. Guide the first
A signal path for operating the amplifier circuit and the second amplifier circuit in BTL operation, and a signal path that is biased and conductive by a direct current applied through the second switching terminal of the headphone jack when the headphone plug is not inserted, and the second amplifier circuit is biased into conduction. a first switching transistor that grounds the input signal path of the circuit; and a first switching transistor that is electrically connected when the microphone is in recording mode and that is electrically connected when the headphone plug is not inserted.
a second switching transistor that cooperates with the switch and the first switching transistor to ground the input signal path of the first amplifier circuit; A control circuit for a tape recorder with a radio, which is characterized in that it prevents the occurrence of error.
JP9391883U 1983-06-17 1983-06-17 Control circuit for tape recorder with radio Pending JPS603906U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9391883U JPS603906U (en) 1983-06-17 1983-06-17 Control circuit for tape recorder with radio

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9391883U JPS603906U (en) 1983-06-17 1983-06-17 Control circuit for tape recorder with radio

Publications (1)

Publication Number Publication Date
JPS603906U true JPS603906U (en) 1985-01-12

Family

ID=30225077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9391883U Pending JPS603906U (en) 1983-06-17 1983-06-17 Control circuit for tape recorder with radio

Country Status (1)

Country Link
JP (1) JPS603906U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183736U (en) * 1986-05-14 1987-11-21
JPS62183738U (en) * 1986-05-14 1987-11-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62183736U (en) * 1986-05-14 1987-11-21
JPS62183738U (en) * 1986-05-14 1987-11-21
JPH0438737Y2 (en) * 1986-05-14 1992-09-10

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