JPS6037787A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6037787A
JPS6037787A JP14690483A JP14690483A JPS6037787A JP S6037787 A JPS6037787 A JP S6037787A JP 14690483 A JP14690483 A JP 14690483A JP 14690483 A JP14690483 A JP 14690483A JP S6037787 A JPS6037787 A JP S6037787A
Authority
JP
Japan
Prior art keywords
film
metal
thin film
silicon thin
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14690483A
Other languages
Japanese (ja)
Inventor
Norio Kususe
楠瀬 典男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14690483A priority Critical patent/JPS6037787A/en
Publication of JPS6037787A publication Critical patent/JPS6037787A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

Abstract

PURPOSE:To enable to obtain the titled device with a built-in metal-semiconductor diode with a high yield by allowing the ratio of the thickness of a polycrystalline Si film to the thickness of a metallic silicide film formed on this polycrystalline Si to become over a specific ratio. CONSTITUTION:A P type base region 103B is formed on an N type semiconductor substrate 101. Next, a polycrystalline Si thin film 105 is adhered. Then, an Si nitride film 106 is adhered on the surface of the film 105, and the film 106 except the part serving as an electrode wiring line in the future is removed. With the film 106 as a mask, the film 105 is converted into an Si oxide layer 107. Thereby, polycrystalline Si's 108-110 serving as electrode lines in the future are formed. Boron is introduced to the region 110 and to the substrate immediately under it, and phosphorus is introduced to the regions 108 and 109 and to the substrate immediately under them. After the part to serve as the metal- semiconductor diode is exposed, and a metal is adhered, this metal is converted into the metallic silicide 111. Thus, it is contrived that the ratio of the thickness of the film 105 to that of the silicide film 111 become over 1:3.

Description

【発明の詳細な説明】 本づら明は半導体装IIゴに関する。[Detailed description of the invention] The present invention relates to a semiconductor device II.

従来、高速、低消費IF力等の性能を萌し且つ市集積化
された半導体装1自、において、多結晶シリコン薄膜を
用いることが一般化している。特に多結晶シリコン薄膜
全選択的に+H1化することによって互に絶縁分離され
た電極や配線として用することにより、素子の都生芥量
2面積が低減され高性能。
Conventionally, it has become common to use polycrystalline silicon thin films in semiconductor devices that have improved performance such as high speed and low IF power consumption and have been integrated in a commercial area. In particular, by selectively increasing the polycrystalline silicon thin film to +H1 and using it as electrodes and wiring that are insulated from each other, the waste area of the device is reduced by 2, resulting in high performance.

篩集積度全有−ヂ′る半導体装置が可能となっている。Semiconductor devices with a full degree of sieve integration have become possible.

文集′4.′を回路等の半導体装置vc−J’;・いて
、単結晶シリコンのPN接合が1ift方回に導則する
のに必要な電圧より欧い電圧で導通するダイオードが必
要となる1易合が生じる。この様なタイオードとして製
法の筒便さ、及び高周波に卦Qづる特性の良好なことか
ら、金属−半導体ダイオード(以下S。B、Dと略す。
Collection of texts'4. ' is a semiconductor device such as a circuit vc-J', and there is a case where a diode that conducts at a voltage lower than the voltage required for the PN junction of single crystal silicon to conduct in a 1ift direction is required. arise. As such diodes, metal-semiconductor diodes (hereinafter abbreviated as S, B, and D) are used because of their convenient manufacturing method and good high-frequency characteristics.

)が広く用いられている。第1図は8゜1(、J) 全
有効に使用した半導体装16−例の等価回路12勺であ
る。ここでIiN 、1’ Nトランジスターのベース
、コレクタ接合にS、H,JJ(1)側路全段けること
によってペースコレクタ接合か大きく順方向電圧となる
ことを防ぎ、従ってベースに大信号がかかる際vC:F
、−いてもトランジスターのスイッチ時間が速まる。
) is widely used. FIG. 1 shows 12 equivalent circuits of 16 semiconductor devices that are fully utilized at 8°1 (J). Here, by providing all stages of S, H, JJ (1) side circuits at the base and collector junctions of IiN, 1'N transistors, a large forward voltage is prevented from occurring at the pace collector junction, and therefore a large signal is applied to the base. Criminal vC:F
, - the transistor switching time becomes faster.

一方、S、B、JJi構成する為には、市抵統率の栄結
晶半導体と金属又は金属7リザイドが接触している構造
が不可欠である。とCろが多結晶シリコン迦、膜″f:
選択的には化することによって絶縁分離された電極配線
を有する半2n体装1h、にS 、 B 、 I)全組
み込む場合、多結晶シリコン電(グ配腺抵抗仙は小さい
程良いため、該多結晶シリコン薄+1!A上にもS 、
 I3. IJと同じ金属シリナイド全形成する方法が
通常用いられている。
On the other hand, in order to constitute S, B, and JJi, a structure in which the Sakae crystal semiconductor with a certain resistance rate and the metal or metal 7 lyzide are in contact is essential. and polycrystalline silicon, film ″f:
If S, B, I) are all integrated into a semi-2n body 1h with electrode wiring insulated by selectively converting it into a polycrystalline silicon electrode (the smaller the wire resistance is, the better). Polycrystalline silicon thin +1! Also S on A,
I3. The same method as for IJ, in which all metal silicide is formed, is normally used.

又、多結晶シリコン薄膜全通してエミッタ抄成された浅
いエミッタ領域を持つ半導体装置にS、1(・1)全組
み込む場合においても、プロセスの簡11Qさからエミ
ッタ領域上の多結晶シリコン漕膜上にもS、B、Dと回
し金属シリザイド全形成する方法が採られている。
In addition, even when S,1(-1) is completely incorporated into a semiconductor device having a shallow emitter region formed through the entire polycrystalline silicon thin film, the polycrystalline silicon layer on the emitter region is thin due to the simplicity of the process. A method of forming the entire metal silicide by turning S, B, and D is also adopted above.

この様に、金属シリサイドを形成する場合、前者におい
て電極抵抗値を例えVま、10Ω/口以下と小さくする
様々金属シリザイド形成末件では、S 、 13 、 
D特性が而くなる。又、後者ではエミッタ領域上の多結
晶シリコン薄膜上にも金ス・1シリザイド全形成する。
In this way, when forming metal silicide, in the former case, the electrode resistance value is reduced to V, 10 Ω/or less, S, 13,
The D characteristic becomes worse. Furthermore, in the latter case, gold-silicide is entirely formed on the polycrystalline silicon thin film on the emitter region.

このときに、シリコンのくわれ現象によりエミッタ・ペ
ース接合短絡による歩留り低下が起る欠点があった。
At this time, there was a drawback that the yield decreased due to an emitter-paste junction short circuit due to the cracking phenomenon of silicon.

何れにせよ、前記電極配線を有する半導体装置或は、多
結晶シリコン薄膜171Jシエミツタ拡散された浅いエ
ミッタ領域金持つ半導体装置等の既存の半導体腰直にお
いて、 8j3.1)金組み込むことは不可能である。
In any case, 8j3.1) It is impossible to incorporate gold in existing semiconductor devices such as semiconductor devices having the electrode wiring or semiconductor devices having shallow emitter region gold diffused into the polycrystalline silicon thin film 171J. be.

不発明の目的は8.8.D f内蔵した多結晶シリコン
薄膜全含む旨速化ならしめた半導体装置を提供すること
にあl)。
The purpose of non-invention is 8.8. It is an object of the present invention to provide a semiconductor device that is faster and includes a polycrystalline silicon thin film with built-in Df.

jLllJち不発明による半導体装置+d、半導体基板
上の少なくとも−911X分にシリコン薄膜が形成され
、該シリコン薄膜の少なくとも一部分に金〃(1又金λ
・11シリザイドが形成されている半導体%l ll’
iに訃いて。
In the semiconductor device +d according to the uninvented invention, a silicon thin film is formed on the semiconductor substrate at least by -911X, and at least a portion of the silicon thin film is coated with gold
・Semiconductor in which 11 silicide is formed%l ll'
I died.

前記シリ、lン薄膜Q)厚さは該シリコン薄膜に形成さ
れる金漢又は、金ス・)1プリサイド膜厚の3倍以」二
であることをIt−!j畝とする。
The thickness of the silicon thin film is at least three times the thickness of the metal or metal film formed on the silicon thin film. j ridges.

第2図(Δ)〜(I))を参照して本発明の実hfζ例
金説、明する・ N型半2a一体基板101上に所望の開孔部をイ〕する
絶縁被膜全被着する。次いで開孔?Xl5104を7オ
トレジストで被った後開孔部103 J、’ 41’j
不純物全イオン打込−9−全行ないペース領域103H
’を形成する。次いで絶縁fli、膜105及びし1]
孔部103゜104によって蕗出された半立体基板表面
に多結晶シリコン薄膜105f!:気相)IZ長によ−
り被着さぜる。次に多結晶シリコン?tI7膜の表1川
にシリコン電化膜1.06全波着させ将来の電極[)C
線路となる領域上の部分全除くすべてのシリコン鷺化膜
全除去する(第21ヌ1(A))。
A practical example of the present invention will now be explained with reference to FIGS. do. Next is opening? Opening part 103 J after covering Xl5104 with 7 otoresist, '41'j
Impurity full ion implantation-9-full run pace area 103H
' to form. Then insulation fli, film 105 and 1]
A polycrystalline silicon thin film 105f is formed on the surface of the half-dimensional substrate exposed by the holes 103° and 104! : gas phase) depending on IZ length
Warm up the adhesion. Next is polycrystalline silicon? A silicon electrified film 1.06 full wave is deposited on the surface of the tI7 film for future electrodes [)C
All of the siliconized film except for the part on the area that will become the line is completely removed (21st item 1(A)).

その後、シリコン電化膜106をマスクとして熱1圀化
処i44!により多結晶シリコン漕膜全シリコン峻化層
107に俊換する。こ(1)際にシリコン窒化11休1
06で、波われた1j16分の多結晶シリコン状!i、
 1体105は酸化されず、互にシリコン1液化物10
7により絶縁さり、た」、1米の市:極配線1(6とな
る多結晶シリコン108.109,110が11ネ成き
れる(第2図(H) )・ 次に領域110上のシリコン′く化膜のみ全除去し、こ
の領域及び−ぞの直下の単結晶基イ反中にボロン原子全
熱拡赦法により導入する。次にi、 (18。
After that, heat treatment is performed using the silicon electrified film 106 as a mask. As a result, the polycrystalline silicon layer is converted into an all-silicon layer 107. (1) At this time, silicon nitriding 11
06, waved 1j16 minute polycrystalline silicon shape! i,
1 body 105 is not oxidized, and each silicon 1 liquefied substance 10
The polycrystalline silicon 108, 109, 110 which becomes 6 is completed in 11 times (Fig. 2 (H)). Next, the silicon ' on the area 110 is Only the oxidized film is completely removed, and boron atoms are introduced into this region and the single-crystal group directly under the groove by the total thermal expansion method.Next, i, (18).

109上のシリコン璧化11ケ金除去し、これら領域+
08.](+9及びその10下のm結晶基板中にリン原
子を熱拡散法により導入−Jる(第2図(C))。
Silicon layer 11 on 109 is removed and these areas +
08. ] (Phosphorus atoms are introduced into the crystal substrate at +9 and 10 below by thermal diffusion method (FIG. 2(C)).

次に除去されすに残っているシリコン窒化hat全て除
去し多結晶シリコンIgV<蕗出させる。次(c、S、
H,J)となるべき部分全フォトレジスト全マスクにI
Jl」孔・蕗出さぜ金属全被着させた後熱処理をするこ
とにより、該金金属金属シリサイドIJ−1に変換゛T
る(第2図(D) )。この際2 こσ)金L)シリサ
イドが低い抵抗率を有し、シリコン基板と金属−半導体
接触づ−るように前記金属の種類を選ぶことは無i’1
iit、金属シリサイドに変換する条件を電極配線抵抗
値全車さく出来、且っS、B、D特性が良くなるように
設定する必要がある。
Next, all the silicon nitride hats remaining in the removed area are removed and the polycrystalline silicon IgV is exposed. Next (c, S,
H, J) on the entire photoresist mask.
After the entire metal is deposited on the holes and exposed areas of Jl, heat treatment is performed to convert it into the gold metal metal silicide IJ-1.
(Figure 2 (D)). In this case, it is impossible to select the type of metal such that σ) gold L) silicide has a low resistivity and makes metal-semiconductor contact with the silicon substrate.
It is necessary to set the conditions for conversion to metal silicide so that the electrode wiring resistance value can be reduced in all cases, and the S, B, and D characteristics can be improved.

り1才しい金属(1)例として白金の場合(でついで:
+d、;へろ第31’xlfA) vCtt、j:、 
4 #t’i品ノリニア ン1f(4厚5000λの場
合で白金膜厚と電極耐重(抵抗値のj〕i係をボしたも
のである。又b 刑31:21(、IJIには白金++
a厚と&田〕逆方向1酎圧値との関係を示したものであ
る。lf:i1圧値幻2.電流値10μへの点でのm、
 Iih値で測定。883図(〜、 (B)よ勺判る桶
に配線抵抗値1oΩ/口以下で且つS 、+3.JJ特
性も艮い最僧条I/l” id多結晶ノリコン膜厚50
0 o′A、 tr y・ル白金11;j J、I、’
!が、800〜1000λの領域にある。尚、S、Hj
J湧方向耐圧埴の]’i、j八全]へV桿度苧で謂容出
来る場合でQよ、白金膜1“ノ全1600λ稈朋と厚く
することが出来るりで配線砥抗飴全更に小ざくすること
が用能となる。
In the case of platinum (for example, platinum) (then:
+d,;Hero No. 31'xlfA) vCtt,j:,
4 #t'i product Norinian 1f (4thickness 5000λ, platinum film thickness and electrode load resistance (resistance value j) are omitted.Also, b 31:21 (, IJI has platinum ++
This shows the relationship between the a thickness and the reverse direction 1 alcohol pressure value. lf: i1 pressure value illusion 2. m at the point to the current value 10μ,
Measured by Iih value. Figure 883 (~, (B) clearly shows that the wiring resistance is less than 10Ω/hole, and the S, +3.JJ characteristics are excellent.
0 o'A, try 11; j J, I,'
! is in the region of 800 to 1000λ. In addition, S, Hj
In the case where it is possible to accept the pressure-resistant clay in the J spring direction with the V-shaped layer, the platinum film can be made as thick as 1600λ in total, so the wire resistance can be increased. It is useful to make it even smaller.

第4図1(ΔL (1−()全参照して不発明の111
1の実施例を説明する。
Figure 4 1 (ΔL (1-()) All references to uninvented
A first embodiment will be explained.

不純物熱拡17′zrl<にょって形成されたベース全
11域1031.3とシリコン基板101の表面を熱酸
1にしC形成されたシリコンr′変化膜(Si(+2)
102に所望の111極思全開孔し、該酸化片×102
及0−ノー・板101蕗田部分に一43ミな多結晶シリ
コン] (151f成Jそし。
All 11 regions 1031.3 of the base formed by impurity thermal expansion 17'zrl and the surface of the silicon substrate 101 are heated with thermal acid 1 to form a silicon r' change film (Si(+2)
A desired 111-pole hole is fully opened in 102, and the oxidized piece x 102
And 0-No, 143mm polycrystalline silicon on board 101 Fukita part] (151f formation J).

該多結晶シリコン’+、 05 i通して、浅いエミッ
ク拡散領域] (19E及びコレクタ市(、π1ose
を形1曳する。次いで市;棒部分を略÷二〉′ラバター
ンーC多結晶シリコン105ffij基択−〔、、チン
グする次いでS、+3.J)となるべき部分i、112
ノオトレジスト全マスクにIJb孔蕗出さぜる(第4図
(〜)。
Through the polycrystalline silicon'+, 05i, a shallow emic diffusion region] (19E and collector city (,
Draw a shape of 1. Next, cut the rod part approximately ÷ 2〉' rubber turn - C polycrystalline silicon 105ffij base selection - [,, then S, +3. J) part i, 112
Extrude the IJb holes on the entire nootresist mask (Figure 4 (~)).

次に金属を被N式せた後、熱処理することにより該金J
、4+=i f金属シリザイド111に変換する(第4
図(B))。尚こσノ際シリコン基板と金J−「!−半
導体接I)’lする様に前記@属の種類を選ぶことは前
述の実施例と同じである。
Next, after the metal is coated with N, heat treatment is applied to the gold J.
, 4+=if converted to metal silicide 111 (fourth
Figure (B)). It should be noted that selecting the type of the @ group so that the silicon substrate and the gold semiconductor are in contact with each other is the same as in the previous embodiment.

?JS 512.1 v、好ましい金属の例として白金
400A膜厚の場合におけるエミッタ・ベース接合歩留
りと多結晶シリコン膜厚の関係葡示したものである。
? JS 512.1 v, which shows the relationship between the emitter-base junction yield and the polycrystalline silicon film thickness in the case of a platinum 400A film thickness as an example of a preferred metal.

同図からtiJる株に、金ス・凡シリザイドを形成する
際に起るシリコンのくわれ現IJ、に防止し、高歩留り
金イ8するためにr」:多結晶シリ二フン膜厚が1.2
FIOA以上必゛拗であることか判る。
From the same figure, it can be seen that the film thickness of polycrystalline silicide is increased to prevent the formation of silicon silicide and to achieve high yield IJ. 1.2
It can be seen that it is more difficult than FIOA.

以−ヒ述べたむkに多結晶シリコン膜厚と金ス・・)シ
リザイドIIIJ厚の地が1〜3以上とすることにより
高歩留りである半7f)体穫置ケ冥J」1.出来る。尚
、多結晶シリコン膜厚と11輩シリザイド膜厚の比はバ
タニーング精度、装置rの性能、製造能力により決定さ
れるのは言971:でもないが、1:5〜7の所が最適
値である。
As described below, the thickness of the polycrystalline silicon film and the thickness of the gold layer are 1 to 3 or more, resulting in a high yield.1. I can do it. The ratio between the polycrystalline silicon film thickness and the 11th grade silicide film thickness is determined by the batting accuracy, the performance of the equipment, and the manufacturing capacity, but the optimum value is 1:5 to 7. be.

又、ボイポーラ型半導体装置の実施例について説明した
が、MO8型半与休属置装摘要出来ることは云うまでも
ない。
Further, although an embodiment of a vipolar type semiconductor device has been described, it goes without saying that an MO8 type semi-active device can also be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半棉体−金属ダイオード葡有する半導体装置の
等画回路図であ、!71第1図2Δ)〜(J))は各/
r不発明の実が11例の半導体装置をその製造工程にl
′1)って示す1更面図である。第3図(Δ)U:、多
結晶シリコン膜厚5000Aのときの熱処理600’C
I5分における2配線抵抗値メ・j白金膜厚を1jkl
係示すグラフ及び第31ンI (IJIは白金膜)9対
SBD逆方回而」圧値り関係ケホすグラフ、第4図(A
+、 (13)はイ(発明の他の実用例の製;≦に工程
に沿って示す断面図であり、第51¥1は白金膜厚4.
 OOAで熱処理6oo’c 15分におりるエミッタ
・ベース接合歩′1イリメ・[多結晶シリコン膜厚V)
関係を示すグラフで、−:)る。 なお図中において、 101−1.、q’t#;、’;晶シリコン基板、10
2=・・−絶4績被膜、1(13,104・・−絶縁波
11’−における開口部、105・・・・・多結晶シ1
ノコンン則1j労、106・・・・シリコン窒化)11
08,109゜110・・・多結晶シリコン′亀・誤配
線路、107−・・・シリコン(・欧化膜、111・・
・金属シ1ノサイド。 103 B・・・・・P型ベース領域、109E・−・
N型エミッタ領域、金示す。 ・・ 、4.\ イー■1人 41゛ ”−t: 171 1M ° (
゛。 1研fR) 白7外π橋肩 (2) c%)6外船号へ−シz″?■
Figure 1 is an isometric circuit diagram of a semiconductor device having a semi-cotton body and a metal diode. 71 Figure 1 2Δ) to (J)) are each /
r The fruit of non-invention is the manufacturing process of 11 semiconductor devices.
'1) is a further side view. Figure 3 (Δ) U: Heat treatment at 600'C when polycrystalline silicon film thickness is 5000A
2 wiring resistance value at I5 minutes, platinum film thickness is 1jkl
Figure 4 (A)
+, (13) is a cross-sectional view shown along the process in A (manufacturing of another practical example of the invention;
Emitter-base junction step '1 after heat treatment at OOA for 6oo'c 15 minutes [Polycrystalline silicon film thickness V]
A graph showing the relationship -:). In the figure, 101-1. ,q't#;,';crystalline silicon substrate, 10
2=...-absolute 4-layer coating, 1 (13,104...-opening in insulation wave 11'-, 105...polycrystalline film 1
Noconn rule 1j labor, 106...silicon nitride) 11
08,109゜110...Polycrystalline silicon' turtle/wrong wiring path, 107-...Silicon (・European film, 111...
・Metal sinocide. 103B...P-type base region, 109E...
N-type emitter region, gold shown. ..., 4. \ E ■ 1 person 41゛ ”-t: 171 1M ° (
゛. 1st lab fR) White 7 outer π bridge shoulder (2) c%) To 6 outer ship - z″?■

Claims (5)

【特許請求の範囲】[Claims] (1)半導体基板上ヒの少なくとも一部分にシリコン薄
膜が形成され、該シリコン薄膜の少なくとも’r?B分
に全組又は金属シリサイドが形成されている半導体装置
において、前記シリコン薄膜の厚さは該シリコン薄膜に
形成された金4114又に+、全組シソサイド膜厚の3
倍以上であることを特1改とする半導体装置。
(1) A silicon thin film is formed on at least a portion of the semiconductor substrate, and at least 'r? In a semiconductor device in which the entire set or metal silicide is formed in the B portion, the thickness of the silicon thin film is equal to the thickness of the gold 4114 formed on the silicon thin film and 3 of the total set of silicide film thickness.
Semiconductor devices for which special feature 1 is specified as being more than twice as large.
(2)前記シリコンれ9°膜は半導体基板上の絶縁膜に
設けら?lた開孔窓に」二9該半導体基へと接続さi7
,7且つ顔シリコン薄膜が設けられてない他の半導体基
板上の絶縁膜の少なくとも一部分に仮数り開孔窓が形成
されており、前記シリコン薄膜及び前猷俊斂り開孔窓の
少なくとも一部分に金属又は、金属シリサイドが形成さ
れていることを特徴とする特許請、1この範IJj(第
(り項記載の半導体装置。
(2) Is the silicon 9° film provided on an insulating film on a semiconductor substrate? 29 connected to the semiconductor substrate in the aperture window 17
, 7, and a mantissa aperture window is formed in at least a part of the insulating film on the other semiconductor substrate on which the face silicon thin film is not provided, and at least a part of the silicon thin film and the mantissa aperture window are formed. Claim 1: A semiconductor device according to claim 1, characterized in that a metal or a metal silicide is formed.
(3) 前記シリコン薄1j〆が多結晶シリコン薄膜で
あることを特徴とする特許請求の範囲l君(1)項記載
の半導体装置。
(3) The semiconductor device according to claim 1 (1), wherein the silicon thin film 1j is a polycrystalline silicon thin film.
(4)前記金属又は金属シリサイドが白金又は白金シソ
サイド或はモリブデン又はモリブテンシリサイド、タン
グステン又はタンクスデンシリザイドであること全特徴
とする特a/l請求の範囲第(])項記載の半畳体装洒
(4) The semi-condensed body according to claim 1, wherein the metal or metal silicide is platinum or platinum silicide, molybdenum or molybdenum silicide, tungsten or tungsten silicide. Fashionable.
(5)前記シリコン薄膜が多結晶シリコン薄膜であ、!
71前記国数の開孔窓の少なくとも一部分に金属−半導
体ダイオードが形成されていること全特徴とづ−るノ1
へ許請求範囲2−[(21項記載り半ンJア体装置。
(5) The silicon thin film is a polycrystalline silicon thin film!
71 A metal-semiconductor diode is formed in at least a portion of the aperture window of the above-mentioned number of countries.
Claim 2-[(The half-body device described in claim 21.
JP14690483A 1983-08-11 1983-08-11 Semiconductor device Pending JPS6037787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14690483A JPS6037787A (en) 1983-08-11 1983-08-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14690483A JPS6037787A (en) 1983-08-11 1983-08-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6037787A true JPS6037787A (en) 1985-02-27

Family

ID=15418197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14690483A Pending JPS6037787A (en) 1983-08-11 1983-08-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6037787A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5563821A (en) * 1978-11-06 1980-05-14 Nec Corp Semiconductor device
JPS57122540A (en) * 1980-12-09 1982-07-30 Fairchild Camera Instr Co Multilayer metallic silicide mutual wire for integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5563821A (en) * 1978-11-06 1980-05-14 Nec Corp Semiconductor device
JPS57122540A (en) * 1980-12-09 1982-07-30 Fairchild Camera Instr Co Multilayer metallic silicide mutual wire for integrated circuit

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