JPS6037655B2 - Digital/analog conversion circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a digital-to-analog conversion circuit, and particularly to a PC.
The present invention relates to a digital-to-analog conversion circuit suitable for M communication.

In PCM communication, there is a method in which an analog signal is first logarithmically compressed when converted to a digital signal, and then logarithmically expanded using a digital-to-analog (A/D) conversion circuit when demodulating the digital signal.

As one such method, the voltage-current characteristics of a diode are used for logarithmic companding characteristics in a D/A conversion circuit.

However, such methods involve complexity in diversifying parts, increasing the number of parts, selecting parts with good characteristics, etc.
Furthermore, it is difficult to integrate circuits, resulting in larger equipment.
There are also problems with price and reliability. An object of the present invention is to provide a D/A conversion circuit for PCM communication that can be integrated into an integrated circuit.

The present invention includes an input circuit that generates a plurality of digital signals that selectively combine first to nth digital signals, their in-phase signals, and these anti-phase signals, and one transistor group of a differential pair transistor circuit. inputting a plurality of digital signals from the input circuit in correspondence with each other;
A group of 2n analog switches that take out the output from the other transistor, and 1, 2, 4, 8, ... 2 (-
1), the other transistor from which the output is taken out receives the output from the level shift circuit biased by the means for biasing the current source transistor; It is characterized in that it is configured to operate according to the received information. The selection means can be composed of, for example, a NAND or NOR circuit composed of bipolar transistors, and therefore the D/A conversion circuit according to the present invention can be made into a monolithic integrated circuit, resulting in miniaturization, lower cost, and higher reliability. everything is accomplished.

The present invention will be explained below with reference to the drawings.

FIG. 1 shows a logarithmic expansion characteristic approximated to a diode voltage-current characteristic, and shows, for example, the relationship between an analog output and a 3-bit digital input. Table 1 shows the numerical relationship between the digital input and analog output with the characteristics shown in FIG. Therefore, the weight current ratio is 1:2:4:8:16, respectively.
:32:64:128 prepares 8 current sources and 3
If one of the current source outputs is selected based on a logical combination of eight bit inputs and used as an analog output, a D/A converter circuit that satisfies the relationship shown in FIG. 1 will be obtained.
Table 2 shows the relationship between output current values selected for eight combinations of 3-bit logic inputs A, B, and C in this case.
As is clear from Table 2, as the output current selection means of the current source, the combinations of the true complement logic signals of each of the 3-bit logic inputs are ABC, ABC, ABC, ... ABC 8.
only one of these combinations is “1” or “
The so-called NA
ND or NOR circuits can be used. Figure 2 shows
1 is a circuit diagram showing an embodiment of the present invention, showing an example in the case of n=3-bit digital input.

In the figure, current source transistors ~8 are each 12
A bias current amplifier that generates a current having a weight of 8, 64, 32, . . . 2, 1, and is connected between the R-2R ladder network 10 and the reference current input terminals 11 and 12. 9 generates each constant current. Digital logic inputs are input to terminals A, B, and C, and are connected to logic input buffers 21, 22, and 23, respectively, which generate true complement outputs A, A, B, B, C, and C, respectively. On the other hand, the current source outputs, that is, the collector outputs of the transistors 1 to 8 are connected to each of the NAND type analog switches 13 to 2 forming the selection means, and are selected for each of the above combinations of logic inputs A, B, and C. The configuration is such that the signal is supplied to the output terminal OUT. The level shift 3 circuit 21 connected between the ground terminal GND and the negative current source terminal 24 is for biasing the analog switches 13 to 20, and the transistor Tr compensates for the deterioration of DC characteristics caused by the analog switch. It is something to do. Figure 3 shows the N shown in Figure 2.
FIG. 2 is a diagram showing, as an example, a switch 13 section and its peripheral circuit among the AND type analog 4 switches 13 to 20.

In the figure, parts equivalent to those in FIG. 2 are designated by the same reference numerals. The input current from the current source terminal 12 flows through the base current compensation transistor Tr to the reference current source 25 consisting of the transistor Tr2 and the resistor R. A current source 26 made up of the reference current source 25 and the transistor 1 that outputs the weight current 128 is biased by the current source amplifier 9, and the current source 26 operates as a current mirror. The output of the level shift circuit 21 biased by the output of the current source amplifier 9 is connected to the base current compensation transistor T.
It is connected to the base of the switching transistor 30 constituting the r, and n-bit input NAND analog switch 13. By providing this level shift circuit 21, the base of the transistor 30 connected to the output terminal in the analog switch 13 is driven at a higher voltage than the base of the current source transistor. On the other hand, if we bias the base of the transistor 30 with the same voltage as the current source transistor 1 without performing this level shift, the collector potential of the current source transistor will be lower by the base-emitter voltage VBE of the transistor 30. To,
In some cases, the base-collector potential of this transistor cannot be made high enough, and in some cases, the transistor 1 is not turned on. However, by driving the transistor 30 with a level-shifted voltage as in the present invention, the collector potential of the transistor 1 can be kept sufficiently high even if a voltage drop of V88 occurs when the transistor 30 is on. Such inconveniences can be eliminated and stable operation can be ensured.
Analog switch 13 includes transistors 30, 31, 32
, 33, complementary signals A, B, and C of the 3-bit digital input signals A, B, and C are applied to the bases of the transistors 31, 32, and 33, and the outside of the collector is grounded.
The collector of the transistor 30 is the analog output terminal OUT
It is connected to the. The emitters of these transistors 30-33 are commonly connected and connected to the output of a current source 26 which outputs 128 weight currents. transistor 30
~ 31 constitutes an open current switching circuit, and the transistor 30 becomes conductive only when inputs A, B, and C are all low with respect to the base voltage of the transistor 30, and a weight current of 128 is applied to its collector output OUT. Output. Input A
, B, and C become high level, all three transistors are turned off, the transistor on the high level input side is turned on, and the weight current of 128 does not flow to the output terminal OUTUT, but is grounded. Therefore, the base power of each transistor constituting the other switch circuits 14 to 20,
It is clear that if a combination of true complements of logical inputs is input using the connections as shown in FIG. 2, a circuit satisfying the characteristics shown in FIG. 1 can be obtained. In the above embodiment, a NANO type selection circuit has been described, but it goes without saying that other selection circuits may be used, and it is clear that the selection circuit is not limited to 3 bits.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the logarithmic companding characteristics of a D/A conversion circuit for PCM communication, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 is a circuit explaining a part of the circuit of Fig. 2. It is a diagram. In the figure, 1 to 8 are current source transistors, 13 to 20
21 to 23 are input buffer circuits, A, B, and C are digital input signals, and OUT is an analog output terminal. Table] 2. The mark indicates the output weight current. Thrive Zutsutomu'Z Boar Z

Claims (1)

[Claims] 1. An input circuit that generates a plurality of digital signals that selectively combine logical signals of true complements of each of the first to nth digital signals, and one transistor group of a differential pair transistor circuit that is connected to one transistor group of the differential pair transistor circuit. A group of 2^n analog switches which respectively input a plurality of digital signals and take out the output from the other transistor, and 1, 2, 4, 8... A current source transistor that generates a current with a weight of 2^(^n^-^1^) and a resistor network, and the other transistor from which the output is taken out has means for biasing the current source transistor. 1. A digital-to-analog conversion circuit configured to operate in response to an output from a level shift circuit biased by.