JPS6037617B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6037617B2
JPS6037617B2 JP4161880A JP4161880A JPS6037617B2 JP S6037617 B2 JPS6037617 B2 JP S6037617B2 JP 4161880 A JP4161880 A JP 4161880A JP 4161880 A JP4161880 A JP 4161880A JP S6037617 B2 JPS6037617 B2 JP S6037617B2
Authority
JP
Japan
Prior art keywords
film
thermal resistance
base
substrate
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4161880A
Other languages
Japanese (ja)
Other versions
JPS56138931A (en
Inventor
正典 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4161880A priority Critical patent/JPS6037617B2/en
Publication of JPS56138931A publication Critical patent/JPS56138931A/en
Publication of JPS6037617B2 publication Critical patent/JPS6037617B2/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は、ガリウム、枇素（ＧａＡｓ）或いはそれを主
成分とする半導体基板を用いた半導体装置の改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor devices using gallium, GaAs, or a semiconductor substrate containing them as a main component.

従来、前記種類の半導体装置では、ＧａＡｓ基板の背面
に金・ゲルマニウム（Ａｕ蛇）等を真空黍着法等で被着
させ、例えば金・錫（ＡｕＳｎ）からなるロウ材を用い
てステムに固着するようにしている。Conventionally, in the above-mentioned type of semiconductor device, gold, germanium (Au), etc. are deposited on the back surface of a GaAs substrate by a vacuum coating method or the like, and then fixed to the stem using a brazing material made of, for example, gold and tin (AuSn). I try to do that.

しかしながら、ＡｕＱはＧａＡｓに対する密着性が良好
ではなく、また、ＡｕＳｎと合金を作り易いので、Ｇａ
Ａｓ半導体基板にＡｕＧ膜が存在しない部分を生じ、ス
テムから剥離したり、熱抵抗のバラッキ及び増大を生じ
たりして製造歩留りの低下を招来する。However, AuQ does not have good adhesion to GaAs, and it is easy to form an alloy with AuSn.
A portion of the As semiconductor substrate where the AuG film does not exist is formed, causing peeling from the stem and variation and increase in thermal resistance, resulting in a decrease in manufacturing yield.

本発明は、ＧａＡｓ或いはそれを主成分とする半導体基
板を強固に且つ良好な状態で基台に取付けたこ半導体装
置を提供するものであり、以下これを詳細に説明する。The present invention provides a semiconductor device in which a semiconductor substrate made of GaAs or its main component is mounted firmly and in good condition on a base, and this will be described in detail below.

第１図は本発明−実施例の要部側断面図である。図に於
いて、１はＧａＡｓ半導体基板、２はソース電極、３は
ドレィン電極、４はゲート電極、５はダイシング・ライ
ン、６はニッケル・クロム（ＮｉＣｒ）合金膜、７は金
（Ａｕ）蒸着膜、８はＡｕ鍍金膜、９はＡｕＳｎのロウ
材、１０は基台をそれぞれ示す。FIG. 1 is a sectional side view of a main part of an embodiment of the present invention. In the figure, 1 is a GaAs semiconductor substrate, 2 is a source electrode, 3 is a drain electrode, 4 is a gate electrode, 5 is a dicing line, 6 is a nickel-chromium (NiCr) alloy film, and 7 is gold (Au) deposited. 8 is an Au plating film, 9 is an AuSn brazing material, and 10 is a base.

この半導体装置は、基台１とＮｉＣｒ合金膜６との密着
性、ＮｉＣｒ合金膜６とＡｕ膜７，８との密着性などが
極めて良好である為、基板１と基台１０との密着は均一
且つ強固である。In this semiconductor device, the adhesion between the base 1 and the NiCr alloy film 6 and the adhesion between the NiCr alloy film 6 and the Au films 7 and 8 are extremely good, so the adhesion between the substrate 1 and the base 10 is very good. Uniform and strong.

前記実施例を製造する場合の一例を説明すると次の通り
である。An example of manufacturing the above embodiment will be explained as follows.

１ 主表面に電界効果トランジスタが形成されたＧａ船
半導体基板１をガラス板などにワックスを用いて貼付す
る。1. A Ga carrier semiconductor substrate 1 having a field effect transistor formed on its main surface is attached to a glass plate or the like using wax.

２ ラッピング法或いは化学エッチング法などを適用し
て基板１を１００〜２００〔仏の〕程度に薄くする。2. Thin the substrate 1 to about 100 to 200 mm by applying a lapping method or a chemical etching method.

３ 例えば真空蒸着法を適用して基板１にＮｉＣｒ（Ｎ
ｊ８０〔％〕、Ｃｒ２０〔％〕）合金膜６を厚さ例えば
１００〔Ａ〕程度に形成する。3 For example, by applying a vacuum evaporation method, NiCr(N
The alloy film 6 is formed to have a thickness of, for example, about 100 [A].

４ 引き続きＡｕ蒸着腰７を厚さ例えば１０００〜２０
００〔Ａ〕程度に形成する。4 Continue to deposit Au to a thickness of 1,000 to 20, for example.
It is formed to about 00 [A].

５ Ａ収蒸着膜７上に鍍金法に依りＡｕ鍍金膜８を厚さ
例えば１０〔ｙの〕程度と厚く形成する。5. An Au plating film 8 is formed on the A-absorbing vapor deposited film 7 to a thickness of, for example, about 10 [y] by a plating method.

６ 基板１をガラス板から外し、ダィシング・ソーなど
で個々のチップに分割する。6. Remove the substrate 1 from the glass plate and divide it into individual chips using a dicing saw or the like.

７ チップを例えばＡｕＳｎからなるロウ材９を用し、
て基台１川こ固着する。7 The chip is made of a brazing material 9 made of AuSn, for example,
The base is firmly fixed.

前記したように、本発明では、Ｇａ松或いはそれを主成
分とする半導体基板の背面とＡｕ膜との間にＮｉＣｒ合
金膜を介在させてあり、このようにすると、半導体基板
とＮｉＣｒ合金膜との密着性及びＮｉＣｒ合金膜とＡｕ
膜との密着性が良好である為、熱放散が良好で熱抵抗は
低くなる。As described above, in the present invention, the NiCr alloy film is interposed between the Au film and the back surface of the Ga pine or the semiconductor substrate mainly composed of Ga pine, and in this way, the semiconductor substrate and the NiCr alloy film are Adhesion between NiCr alloy film and Au
Since the adhesiveness with the film is good, heat dissipation is good and thermal resistance is low.

ここで、本発明を実施して得られた装置に於ける密着性
及び熱抵抗に関するデータを従来技術を実施して得られ
た装置に於けるそれと比較して説明する。Here, data regarding adhesion and thermal resistance of a device obtained by implementing the present invention will be explained in comparison with that of a device obtained by implementing the prior art.

第２図は厚さが５０〔仏の〕であるＧａＡｓウェハ１
１上に厚さが０．２〔仏机〕であるＡｕ戊（Ｇｅ１２〔
％））膜１２を形成した試料であり、この試料をスクラ
ィブ・ラインで分割して半導体チップにする切断（クラ
ッキング）工程では、その切断面に沿って剥がれを生じ
、また、半導体チップにした後、これをロゥ材で基台に
ダィ付けしてマゥントするが、その際、該半導体チップ
を振動させることが必要であり、そのときにも剥がれを
生じ、これ等の工程で発生する剥がれ不良率は１０〔％
〕にも達する。Figure 2 shows a GaAs wafer 1 with a thickness of 50 mm.
On top of 1 is an Au shell (Ge12) with a thickness of 0.2 [Buddha desk].
%)) film 12 was formed, and during the cutting (cracking) process in which this sample is divided into semiconductor chips by scribe lines, peeling occurs along the cut surface, and after the semiconductor chips are made, peeling occurs. This is mounted by die-fixing it to a base with soldering material, but at that time, it is necessary to vibrate the semiconductor chip, which also causes peeling, which causes peeling defects that occur in these processes. The rate is 10%
].

これは、ＡｕＧｅ膜１２をＮｉ膜とした場合も同様な傾
向になる。第３図は厚さが５０〔仏の〕であるＧａＡｓ
ウェハ２１上に厚さが０．１〔ム肌〕であるＮｉＣｒ膜
２２、厚さが０．２〔りｍ〕であるＡｕ膜２３、厚さが
２〔仏肌〕である鍍金に依るＡｕ膜２４を形成した本発
明に於ける試料であり、この試料を半導体チップに分割
した際、また、基台にマウントした際の何れの場合に於
いても剥がれは皆無であった。The same tendency occurs when the AuGe film 12 is a Ni film. Figure 3 shows GaAs with a thickness of 50 [Buddha].
On the wafer 21 are formed a NiCr film 22 with a thickness of 0.1 [mu], an Au film 23 with a thickness of 0.2 [mu], and a plated Au film with a thickness of 2 [mu]. This is a sample according to the present invention in which a film 24 was formed, and there was no peeling at all when this sample was divided into semiconductor chips or when mounted on a base.

ところで、一般に、ＧａＡｓ、Ａｕ、ＡｕＣも、Ｎｉ、
ＮｊＣｒ等のそれぞれに於いては厚くなるほど熱抵抗は
高くなる。従って、第２図に見られる従来技術に依る試
料は、第３図に見られる試料に比較して熱抵抗が低い筈
であるが、実際には、逆であって、第３図の試料に於け
る熱抵抗は低くなる。By the way, in general, GaAs, Au, AuC, Ni,
The thermal resistance of NjCr and the like increases as the thickness increases. Therefore, the prior art sample shown in Figure 2 should have a lower thermal resistance than the sample shown in Figure 3, but in reality it is the opposite; Thermal resistance in the area is lower.

第４図は第２図に見られる試料の熱抵抗に関するデータ
を示す緑図であり、縦軸に半導体チップの個数をパーセ
ンテージで表し、機軸に熱抵抗を単位〔℃′Ｗ〕で表し
てある。Figure 4 is a green chart showing data regarding the thermal resistance of the sample seen in Figure 2, with the number of semiconductor chips expressed as a percentage on the vertical axis, and the thermal resistance expressed in units of [℃'W] on the vertical axis. .

第５図は第３図に見られる試料に関する第４図と同様の
データを示す線図である。FIG. 5 is a diagram showing similar data to FIG. 4 for the sample seen in FIG.

第４図及び第５図を比較すると、第４図に於ける熱抵抗
の平均値は９．５〔〇Ｃ／Ｗ〕、第５図に於けるそれは
７．５〔ｑ０／Ｗ〕であって、明らかに第５図に見られ
るデータの方が熱抵抗は低くなっている。Comparing Figures 4 and 5, the average value of thermal resistance in Figure 4 is 9.5 [〇C/W], and that in Figure 5 is 7.5 [q0/W]. Obviously, the thermal resistance is lower in the data shown in Figure 5.

このような結果は、本発明に依った場合、密着性及び熱
放散が良好であることから生ずるものと考えられる。It is believed that such results result from the good adhesion and heat dissipation according to the present invention.

尚、Ａｕ蛇膜１２をＮｉ膜に代えた場合のデータはない
が、密着性の点から見て、本発明に依るものが勝つてい
る筈であると考えられる。以上のように、本発明に依れ
ば、ＧａＡｓ或いはそれを主成分とする半導体基板の背
面にＮｉＣｒ合金膜を形成し、その上に金膜を形成し、
該金膜側をロゥ材を介して基台に固着した半導体装置が
得られ、その構成に依り、半導体基板に金膜が一様に付
着し、従って、チップはその全面が基台に良好に密着す
るので、熱抵抗のバラツキを生じないことは勿論その低
減に有効であり、また、チップが基台から剥離するよう
な事故は少なくなる。Although there is no data on the case where the Au snake film 12 is replaced with a Ni film, it is thought that the film according to the present invention should be superior in terms of adhesion. As described above, according to the present invention, a NiCr alloy film is formed on the back surface of a semiconductor substrate mainly composed of GaAs or GaAs, and a gold film is formed thereon.
A semiconductor device is obtained in which the gold film side is fixed to the base via a soldering material, and depending on the structure, the gold film is uniformly attached to the semiconductor substrate, so that the entire surface of the chip is well attached to the base. Since they are in close contact, it is of course effective in reducing variations in thermal resistance, and also reduces accidents such as the chip peeling off from the base.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の要部切断側面図、第２図は
従来技術に依る試料の要部切断側面図、第３図は本発明
に依る試料の要部切断側面図、第４図は第２図に見られ
る試料の熱抵抗に関するデータを示す線図、第５図は第
３図に見られる試料の熱抵抗に関するデータを示す線図
をそれぞれ表わしている。 図に於いて、１は基板、２はソース電極、３はドレイン
電極、４はゲート電極、５はダイシングライン、６はＮ
ｉＣｒ合金膜、７はＡｕ蒸着膜、８はＡｕ鍍金膜、９は
ロウ材、１０は基台である。 舞′図努２図 努３図 ．繁４図 幻づ図FIG. 1 is a cutaway side view of the main part of an embodiment of the present invention, FIG. 2 is a cutaway side view of the main part of a sample according to the prior art, and FIG. 3 is a cutaway side view of the main part of a sample according to the present invention. 4 is a diagram showing data regarding the thermal resistance of the sample shown in FIG. 2, and FIG. 5 is a diagram showing data regarding the thermal resistance of the sample shown in FIG. 3. In the figure, 1 is the substrate, 2 is the source electrode, 3 is the drain electrode, 4 is the gate electrode, 5 is the dicing line, and 6 is N
An iCr alloy film, 7 an Au vapor deposited film, 8 an Au plating film, 9 a brazing material, and 10 a base. Mai'zu Tsutomu 2 Tsutomu 3. Traditional 4th illustration Genzuzu

Claims (1)

【特許請求の範囲】[Claims] １ 砒化ガリウム或いはそれを主成分とする薄い半導体
基板、その背面に形成されたニツケル、クロム合金膜、
その上に形成された厚い金膜、該金膜との間にロウ材を
介して前記基板が固着されている基台を備えてなること
を特徴とする半導体装置。1. A thin semiconductor substrate made of gallium arsenide or gallium arsenide as a main component, a nickel or chromium alloy film formed on the back surface of the substrate,
1. A semiconductor device comprising: a thick gold film formed thereon; and a base to which the substrate is fixed with a brazing material interposed between the gold film and the gold film.
JP4161880A 1980-03-31 1980-03-31 semiconductor equipment Expired JPS6037617B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4161880A JPS6037617B2 (en) 1980-03-31 1980-03-31 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4161880A JPS6037617B2 (en) 1980-03-31 1980-03-31 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS56138931A JPS56138931A (en) 1981-10-29
JPS6037617B2 true JPS6037617B2 (en) 1985-08-27

Family

ID=12613322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4161880A Expired JPS6037617B2 (en) 1980-03-31 1980-03-31 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6037617B2 (en)

Also Published As

Publication number Publication date
JPS56138931A (en) 1981-10-29

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