JPS6037586A - Key error detection system for des cryptographer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a key error detection method for a DBS cryptographic device, and in particular detects when a key input value stored in a key register changes to an incorrect value. This invention relates to a key error detection method.

(bl) Prior Art and Problems The 1lllfi error detection method of the conventional DBS cryptographic device is performed by checking the parity of the key register output.

An example of a key+tab detection method of a conventional DBS cryptographic device will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of a key of a DES encryption device.

In the same figure, (11 to (64) are key bits, P1 to P8
indicates a parity pit, #(out of 641 bits, the parity bit is the (8th), (lfll, (24)).

(321, (40), (4Fl), (56), (64)
It is placed in the bit.

@2 Figure shows an embodiment of the configuration of the T)ES key calculating section of a conventional EDS cryptographic device. In the same figure, 1 is the key, 2 is 1h
Shift register for parallel conversion, 3 is a key register, 41 is a parity check circuit, 5 is a transposition PC-1 circuit, 6 is a first selector, a 7-digit second selector, an 8-digit first circular digit shift circuit (
(hereinafter referred to as the first shift circuit), 9 is the second circular digit shift circuit, and 10 is the first 28th pit flip-flop circuit (
11 is the second 28-bit flip-flop circuit (hereinafter referred to as the first FF circuit), and 11 is the second 28-bit flip-flop circuit (JJ lower, the second FF !i
:ll path), 1217 is transposed PC-2 circuit, 13
14 is a synchronization signal, 15 is a master clock,
16 is a DES key calculation unit;

FIG. 3 shows a time chart of the master clock, synchronization signal, and various signals used in FIG. 2, and comparison signals used in FIG. 4. In Figure 3, ■ is the master clock for various signals! -Semi-standard. ■ is the darkness of this synchronization signal with the Domon layer number!
υIT (one key operation is performed from -t+ to t43.■
is a burst clock consisting of 16 bits.
This 16-bit clock is delayed by Δ from t, ~t,
It is placed at the timing of At the falling edge of this clock, the first FF circuit and ! Parallel data of 28 bits each is output from the @2FF circuit. Then, the output data becomes a waveform with a timing shown in (2). ■ is the comparison signal used in Fig. 4 for the 48-bit key data corresponding to P1 to P16 of data ■.
Output from the circuit.

In FIG. 2, the serial (64) bit key 1 of the IDES standard as shown in FIG.
The signal is input to register 2, converted into serial/parallel, and then stored in register 3. The parallel data key 1 output from the key register 3 undergoes a parity check every 8 bits in the validity check circuit 4, and the 56-bit data excluding the parity bit in the transfer@PC-1 circuit 5. Bits are swapped randomly.

The key data output of the above transposed PC-IF911 path 5 is 28
The signals are branched bit by bit and selected into a-1 and a-2 corresponding to the first selector circuit 6 and the second selector circuit 7, respectively.

The key data of the first and second selectors 6 and 7 are taken into the corresponding first feedback loop system and second feedback loop system, respectively.

The first feedback loop system consists of the first selector 6 - first shift circuit 8 - first FF circuit 10 - first selector 6, and the second feedback loop system consists of the second selector 7 - second shift circuit 9. - It consists of a second selector 7.

In the first feedback loop system, the first selector 6
The data of 1 to 28 bits output from the first shift circuit 8 is shifted by 1 bit or 2 bits according to the DBS algorithm standard using the 16-bit clock (■) shown in Figure 3 (■). . This shifted data is fed back to b-1 of the first selector 6 via the first FF circuit 10.

The above feedback operation stops after 16 operations. For each of these 16 operations, - the above shifted data is
FF circuit] Transposed from 0 1) Input to C-2 circuit 12.

In the second feedback loop system, the 29 input to the second selector 7 is similar to the first feedback loop system.
~56 bits of data are processed by a 16-bit clock (2) and input to the PC-2 circuit 12.

In the transposed PC-2 circuit 12, the 48 bits of transposed data from which 8 bits have been removed are outputted as a lock signal in response to the rising and falling edges of the clock (2). Then, after operating 16 times, it is stopped, and data processing as in previous P is newly performed by the next synchronization pulse. The key data created in this manner is input to the T) ES calculation unit and used to encrypt plaintext and decrypt ciphertext to plaintext.

In the above IF operation, the key is simply checked by the parity checking circuit 4 performing a parity check on the 64 bits of the key register 30 in units of 8 bits.

If an error of the same sign occurs in the 8-bit internal code, there is a drawback that the lesson cannot be detected.

(cl) Object of the Invention In order to solve the above-mentioned drawbacks, the present invention provides a
DES standard encryption that detects error bits in the new key register by comparing and checking the 28-bit key data output from the circuit and the 28-bit key data input to the transposition PC-2 circuit at the timing of the comparison signal. The purpose of this invention is to provide a device key error detection method.

(d) Structure of the Invention In order to achieve the above object, the output of the key register of the key calculation unit of the DES cryptographic device is subjected to digit shift calculation processing according to the DES algorithm via a transposition PC-1 circuit,
The processing output is input to the transposition PC-2 circuit, and in the key register error detection method of the key calculation unit, the transposition P
The present invention is characterized by providing means for comparing the output signal of the C-1 circuit and the input signal of the transposed PC-2 circuit during a period from the end of one key operation to the start of the next key operation. .

(111 Embodiment of the Invention) In the present invention, the output of the key register is passed through the transposed PC-1 circuit to the a-1 and &-
28 bits each are input at all times, and the first and second
Each 28-bit key data input to the selector is taken into the feedback loop system, and the first... @2 selector b-
1 and b-2. In this system, each DE131
The 1- to 2-bit data is shifted 16 times according to the code, and the 7th to 16th shifts return to the initial value. This series of processing is completed,
Until the next synchronization signal arrives, the a −1 and 5t
-2 data and the corresponding data of b-1 and b-2 are compared using an exclusive OR circuit (hereinafter referred to as gXOR) to detect the wA rebit of the key register. You can.

Hereinafter, the DES cryptographic device key deviation detection method of the present invention will be explained using the drawings. FIG. 4 shows a configuration diagram of an embodiment of the DES encryption device key error detection method of the present invention.

In the figure, w, the same numbers and symbols as in Figure 2 indicate the same members.

In FIG. 4, reference numerals 17 and 18 indicate a comparison circuit configured as an EXOR circuit, 19 indicates an OR circuit, 20 indicates a latch circuit, and 21 indicates a failure generation circuit.

Next, FIG. 4 will be explained using the time chart of FIG. 3. In FIG. 4, the key 1 of the key register is checked by the parity detection circuit 4, and the branched 1 to 28-bit key is input to the M1 selector 60a-1 through the output of the transposed PC-1 circuit 5. - This 28-bit data is shifted by 1 to 2 bits in the first feedback loop system, and through this series of arithmetic processing, each of the 28-bit data P1 to P16 shown in Figure 3 is created. , the original data becomes the original data at the 16th bit timing of the clock ■. These PI-B16
The data are sequentially inputted to the transposed PC-2 circuit 121C and also inputted to b-1 of the first selector 6. This calculation stops at J, ts at the end of the 16th bit clock (2), and the key data does not change until t4, when the next synchronization signal arrives.

Also, for the second foo-back loop system, the same method as above is used.The branched first key of 29 to 56 bits is input to a-2 of the second selector 7, and the second key is inputted to a-2 of the second selector 7 at the falling edge of the clock (2). 1 to 16 in the 2 food pack group
The calculation processing is performed twice, and data P17 to P32 are created. This key data is input to the transfer ffPc-2 circuit 12 as raw water and is also input to the second selector b-2. At the 16th bit of the clock @, the original data becomes the original data, and at t and 1, the periodic signal of t and the modulus is input, and the 9-data processing of the one-dop cruise system stops. a-2 of selector 7 at this point
The key data of and b-2 will be the same if the output of the key register 3 is not digitized.

Here, the first selector 6 which is Tagata of the transposed PC-1 circuit 5
The 28-bit data a-1 of the first selector 6 and the 28-bit data b-1 of the first selector 6, which is the input of the transposition PC-2 circuit 12, are input to AI and B1 of the comparator circuit 17, respectively. Similarly, the second selector 70a- which is the output of the transposed PC-1 circuit 5
2 data and the second data which is the transposed PC-2 circuit 120 input.
The 28-bit key data of each b-2 of the selector 7 is simultaneously input to A2 and B2 of the comparison circuit 18. The comparison circuits 17 and 18 described above are configured by EXOR. The output of the transposed PC-1 circuit and the input data of the transposed@PC-2 circuit are compared in comparison circuits 17 and 18, and the comparison result is inputted to the ratte circuit 20 through an OR gate 19, and its The output is input to an alarm generation circuit 21.

In the above circuit configuration, the black mark (2) in Figure 3 occurs 16 times, and the timing t of the 16th bit occurs.

10-, the operation of the feedback loop stops at timing t4t of the next synchronization signal. During this period, data is latched into the latch circuit 2o by the comparison signal shown in FIG. 3(f).

Now, at timing t, ~t4, the first and second sections 1
a-1, b-1 and a corresponding to /kuta 6 and 7, respectively
If the data of 28 bits each of -2 and b-2 are equal, the outputs of the comparator circuits 17 and 18 are all T Of,
Therefore, since the output of the OR gate 19 is also 101, the latch circuit 2 which is read by the comparison signal (f)
Since the output of 0 is also lo', the alarm origination circuit 21 does not issue an alarm. Mashi Mae EXOR 1
If the data 7 and 18 are different, that is, if there is an error, the alarm generation circuit 21 outputs an alarm signal.

FIG. 5 shows a configuration diagram of an embodiment of the comparison circuit of the present invention. In the same figure, 22-1 to 22-28.22-29-22-
56 indicates EXOR.

In FIG. 5, 28 of a-1 and b-1 of the first selector
The bit-by-bit data is sent to terminals A1 to 28 . After Bl~28■
Input to OR (OR) 22-1 to 22-28. Further, the 28-bit data of a-2 and b-2 of the second selector are also transferred to the respective terminals A1-28. EXOR (or) 22- after Bl ~ 28
EXOR input to 29-22-56 22-1
~22-28 and 22-29 to 22-56 outputs are OR
(OR) input to the latch circuit 20 via the gate 19.

(f) Effects of the Invention As explained above, error checking for conventional keys was performed by parity checking in 8-bit units, which had the disadvantage that when an even-numbered bit error occurred, the error was not checked. , in the present invention transposed pc-i
After one key operation is completed for the 56-bit logic 28 bits + 28 bits, which is the output signal of the circuit, and the 56-bit logic 28 bits + 28 bits, which is the input signal of the transposed PC-2 circuit, the next key operation is started. Since 56 bits of each key are compared until
2 = has the advantage of being detectable even when Therefore, the present invention has a great effect of compensating for the drawbacks of parity checking, and by using it together with parity checking, it becomes possible to detect key errors more reliably.

[Brief explanation of drawings]

Figure 1 shows the arrangement of the key and parity pit in the DES standard.
Fig. 2 shows the DTIS key calculation section of a conventional DBS cryptographic device, Fig. 3 shows a time chart of clocks, parallel signals, and control signals used in Fig. 2, Fig. 4 shows an embodiment of the present invention, and Fig. 5 shows 1 shows a configuration diagram of an embodiment of a comparison circuit of the present invention. In the figure, 1 is a key, 2 is a shift register, 3 is a key register,
4 is a parity check circuit, 5 is a transposition PC-1 circuit, 6 is a first selector, 7 is a second selector, 8 is a first shift circuit,
9 second shift circuit, 10 first FF circuit, 11 M2
FF circuit, 12 is a transposed PC-2 circuit, 13 is a control unit, 1
4 is a synchronization signal, 15 is a master clock, 16.16' is a key calculation unit, 17°18 is KXOR (OR), 19 is OR
20 is a latch circuit, and 21 is an alarm generation circuit. 13-

Claims (1)

[Claims] The output of the key register of the key calculation unit of the DBS cryptographic device is tP.
Digit shift calculation processing according to the DES algorithm is performed through the c-1 circuit, and the processing output is input to the transposition PC-2 circuit. 1 circuit output signal and transposition PC-2
A DES cryptographic device key error detection method comprising means for comparing input signals of a circuit during a period from the end of one key operation to the start of the next key operation.