JPS603720B2 - charge-coupled memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge-coupled memory using a charge-coupled device.

In a charge-coupled memory (hereinafter referred to as a CCD memory), signal charges are generally injected as digital information through sampling at the input section, and are stored in wells at the fin level formed as an expanding depletion layer on the surface of a semiconductor substrate. Along the potential well of the semiconductor surface during thermal equilibrium,
It is composed of a charge-coupled device type register (hereinafter referred to as a CCD register) that sequentially transfers data in one direction.

A conventional CCD memory consists of charge-coupled registers arranged in a number of columns, and the stored information is regenerated by a regenerative amplifier provided at one end of the register and then output directly or transferred to the same register or again. The configuration was such that it was rewritten to registers in other columns. In such a configuration, in the worst case, the time required to transfer an entire column of registers is consumed in order to retrieve the information in the memory element. That is, there is a drawback peculiar to the serial transfer CD memory that the average access time from the sending of the issue command to the time when information can be detected is long. In order to alleviate this drawback, the present invention provides a CCD memory having a structure in which output means are provided at two locations, one in the center and one at the end of the CCD register. According to the present invention, the average access time for registers in a fixed transfer direction can be reduced by half.
Output means are provided at the center and end portions of the register in order to make the output more accurate. These output means are formed by providing a potential barrier region in the semiconductor substrate adjacent to the crab plum detection gate to form a potential well for detecting signal charges.
The surface potential under these fin load detection gates and the potential barrier region is
Since it is determined by the DC voltage of a common bias electrode provided on top of the bias electrode via an insulating film, a potential well can be easily formed. With this structure, the signal charges stored between the input means and the central part of the CCD register are transferred by the output means of the central part, and the signal charges stored between the central part and the terminal part of the CCD register are Since this is detected from the output means provided at the end of the register, the access time is shorter than that of a memory with the same number of bits that has an output means only at the end of one column of registers. 1
With a CCD register configuration having only one CCD register, the number of input means is reduced compared to a memory having 1/2 the number of bits, so a high-density and large-capacity CCD memory can be constructed. below,
The present invention will be explained in detail with reference to the drawings.

FIG. 1 is a schematic diagram of a CCD memory showing an embodiment of the present invention. CCD registers 1 are arranged in three stages in parallel, and each register 11 writes and transfers data transmitted through input lines 1, 12, and 13 from the input means.

The information that has passed through the reproduction signal line 0 is non-destructively written again by the input means. After that, it continues to circulate repeatedly. When it becomes possible to issue a question, information A, . , Aa, or A
,2,n2 or A,3,n3 are the output lines D, respectively.
2, D4, and D6, and sends out a digital signal. At this time, information B, . , &, or B, 2, & 2 or B, 3, and Bsha are also output from the output lines D, , D3, and wide, respectively. Since information is transferred serially, the information in the registers on side A is transferred in chronological order to A. ,,A. 2, or goods A, A22, or goods A, 3, and A23. Similarly, B
B.・,B12, or B,2,
It is read out in the order of B base or B3 and B23. This information is revealed non-destructively. Writing/reading of information may be performed using only one CCD register, or a plurality of CCD registers may be used for this operation. In addition, "the signal processing data for honoring/proposing may be only a single dot information,"
It may be data in block units, which is a collection of such data. When transferring, it is possible to use only the information on either side A or B, or it is possible to use both information simultaneously as a data signal. In this example, 3
Although an example is described in which the CCD register is configured in tiers, the purpose of the content will not be lost even if the structure is configured in more tiers. FIG. 2 is a diagram showing a specific configuration of the embodiment.

Of the configuration shown in FIG. 1, two stages of CCD registers are extracted and shown. The data supplied to the input line 1 or 12 as a digital signal of “1” or “0” is sent to the gate circuit 15.
, it is ANDed with the write command signal WE and sent to the signal line 26. That is, when WE is at a high level (TTL level, 2.4V or more), the data sent to 1 or 12 passes through the gate circuit 15. Data on one of the signal lines 26 is selected in the gate circuit 16 by ANDing it with the decoded address signal A or A2. For ease of explanation, assume that data on input line 1 is selected. The time-series data on the signal line 27 selected by the address signal is logically summed with the data on the signal line 25 (described later) in the OR gate 17, and the data is logically summed with the data on the signal line 25, which will be described later, and the data is logically summed with the data on the signal line 25, which will be described later. The amplifier 18 inverts and converts the level. The level-converted data is sent to the input data line D1, and is connected to a reverse biased PN junction diode.
Signal charges are injected into the CCD register 11 by varying the surface potential on the cathode side of the gate 12. If the data on the input data line D1 is the digit "1", no charge is injected, and it is converted to the information of the digit "0" and sent to the CC.
Stored in D register 1. Conversely, digit “0”
In the case of ``, the fin charge is injected and stored in the CCD register 11 as information of digit ``1''.As described above, the digital signal is inverted in the input means 12.The injected charge is , the surface of the P-type semiconductor substrate constituting the CCD register 1 is transferred toward the output means 13a or 13b by a transfer clock pulse supplied from the outside.The information transferred in the CCD register 11 will be described later. It is detected as an inverted signal in floating game amplifier 13a or 13b, and output signal line D02, respectively.
,D○,. A floating gate amplifier is provided as 13a at the center of the CCD register 11 and as 13b at the end of the CCD register 11, and detects information in the CCD register 11 non-destructively. Therefore, even if the floating gate amplifier 13a detects a signal on the output signal line D02, the information in the CCD register 11 is not lost and continues to be transferred to the output means 13b. The signals on the output signal lines ○○, D02 detected simultaneously by the floating game amplifiers 13b and 13a are converted to TTL level by the buffer amplifier 19, and then sent to the signal line 22.
sent to. The data on signal line 22 is delayed by 1/2 bit by delay gate 40 and sent to signal line 28. Signal line 28 corresponds to loop 10 in FIG. When the write command signal WE is at a low level (0.4 V or less at TTL level), data other than data on the input line 1 is not sent to the signal line 27.
At this time, since the inverted output 24 of the WE by the inverter 20 is at /. level, the reproduction delay information D of the signal line 28 is
F, is inverted by the NAND gate 21 and connected to the signal line 2.
Sent to 5. The reproduced data on the signal line 25 passes through the OR gate 17, is inverted by the buffer amplifier 18, and undergoes level conversion. In this case, since no data is sent to the signal line 27, the reproduced data on the signal line 28 and the input data on the input line 1 are completely separated. The level-converted reproduced data on the input data line D1 is again written to the CCD register 11 via the input means 12. As long as the write command signal WE is not activated (no level), the information in the CCD register 11 continues to be circulated. C
The data in the CD register 11 is transferred to the floating gate amplifier 13.
After being detected at point b, it is absorbed by the reverse biased sink diode 14.

This sink diode is composed of a PN junction diode, and absorbs majority carrier electrons sent to the cathode side into a power supply line that is in ohmic contact with the cathode. When data is to be read from the CCD register 11, a pulse signal activated (in a state of /-level) is sent from the read command signal RE.

Then, the reproduced data DF of the signal line 28 is inverted by the inverter 3, passes through the gate circuit 29a,
It is output to the output line D. Since the input to D is non-destructive, the data outside the output signal line ○○ is written to the CCD register 11 as reproduced data at the same time as it is read. When data is being sent to the output line D, the data on the output signal line 02 is simultaneously read out to the output line D2 via the gate circuit 26b. That is, A of the CCD register 11
The information on side and B side is sequentially D2 and D after the issue command, respectively.
, is read from. So far, we have described the processing process of information written from input line 1, but address signal A2
When the data on the input line 12 is selected, signal processing is performed in a similar process.

Data input to the CCD register 11 is supplied from an input data line D12. When data is output, delayed signals DF3 and DF4 generated by delaying the data on output signal lines D03 and D04 by 1/2 bit are simultaneously outputted to output lines ○3 and D4, respectively. The floating gate amplifier 13a or 13b is on-chip on the CCD register 11, and has gate circuits 15, 16, 17, 21, 29a, 29
b, delay gate 40, inverters 20, 30, buffer amplifiers 18, 19, including CCD register 11.
It can be converted into C.

These gate circuits, delay gates, inverters, and buffer amplifiers can be realized as ordinary MOS circuit elements. Next, the structure of the CCD that constitutes the CCD register,
By revealing the structure of a floating gate amplifier,
Let us explain the situation in which signal charges are transferred within a register.

FIG. 3 shows the structure of the one-stage CCD register and the input/output means.

This figure represents the portion indicated by the dashed-dotted line 23 in FIG. In this specification, a configuration example will be explained using a P-type conductive silicon substrate, but the present invention can also be implemented using an N-type conductive material. Furthermore, the present invention is not limited to silicon, but can be implemented using any material that can form a charge-coupled device. In the CCD in this specification, an insulating film 32 is formed on a P-type semiconductor substrate 31.
Conductive electrodes for the DC gate VB and the transfer gate are formed through the gate electrodes, and in order to give directionality to the transfer, high concentration impurity P regions 35 are periodically provided under each gate electrode.

In such a structure, the surface potential of the high concentration region 35 is shallower than the surface potential of the P region 31. That is, a step is created in the potential distribution under each electrode, and charges can be transferred by the means described later. The CCD shown in Figure 3 is 1
Although the gate electrode is arranged for phase drive, DC VB
Two-phase driving is also possible by setting the transfer pulse to a pulse whose phase is shifted by 1800 degrees. Injection (writing) of signal charges into the CCD register is achieved by varying the surface potential of the N+ region provided on the surface of the P-type semiconductor substrate 31 in accordance with the digital signal of the input data line DI.
Here, the input data line DI corresponds to the input data line D1i (i 1, 2) shown in FIG. The data writing process will be explained with reference to FIG. 4 showing operating waveforms. FIG. 4 shows the case where address signal A is activated during period To. When the write command signal WE is activated, the data group “1011” supplied to the input line 1
It becomes writable only during the power period. Data group “101”
r is shown as an example. At time t,
The start data "1" is inverted and level-converted and supplied to the input data line DI. That is, the surface potential of the N+ region 34a forming the input means is shallow and is set to the potential of 36a. Reference numeral 36 in FIG. 3 represents the surface potential distribution of the r+ region 39 covering the semiconductor surface under each gate electrode, around the N+ region and the effective channel CCD region.
Since the M10 region 39 is an impurity region with a higher concentration than the P10 region 35, its surface potential is the shallowest Q transfer pulse? Under the electrode, when ◇=OV, there is a shallow potential distribution of 37, and when 0=VP, it is deep. A potential distribution of 36c is formed. Further, the voltage VB is applied to the DC VB electrode so that its surface potential forms a distribution 36d located approximately in the middle of the potential distribution where the surface potential under the electrode of transfer pulse 0 forms the maximum and minimum.
is supplied. The input data line DI is connected to the surface potential under the DC VB electrode 33a, and the information "0",
In response to "1", a voltage level is supplied such that the potential distributions of 36a and 36b are formed, respectively. The voltage of such a bell is generated by a buffer amplifier 18 shown in FIG. In the potential distribution 36 formed as described above, N+
Transfer pulse closest to region 34a? A potential valve door 36e is formed below the electrode. Therefore, the majority carrier fin 38a under the N+ region 34a is transferred to the potential well 36e as a signal charge having information of "1". As time progresses to time t2, the surface potential under each gate electrode, such as the N0 region, becomes 37.
The distribution changes to the one shown in . Therefore, the "1" signal charge stored in the potential well 36e is transferred to the potential well 37b below the electrode of the DC gate V8. At this time, N+
Even if data is supplied to the region 34a, no signal charge is supplied into the CCD register due to the potential barrier formed under the transfer pulse gate & electrode. When the time comes, N
The surface potential of the + region 34a forms a distribution 36b.
Therefore, no charge injection occurs. That is, information “0” is C
This means that it has been transferred to the CD register. Thereafter, in the same manner, the entire data group "1011" is written into the CCD register. Even after data writing is completed, charge continues to be transferred to the W region 34b forming the sink diode. Eventually, it is transferred to the surface of the N0 area 34b. For example, when writing new data, that is, at time t,
The signal charge 38d (old data) stored in the well at the fin level under the transfer electrode adjacent to the DC electrode 330 is stored at time t2.
, passing through the lower surface of the electrode 33b and forming the N+ region 34.
transferred to the surface of b. Since the diode made up of the P region 31 and the N+ region 34b is reverse biased by the positive power source Vo, it absorbs all the charge to the supply line of the power source Vo. The surface of the N+ region 34b always forms a potential of 37c. Even if the charge is finally eliminated, the CCD memory of the present invention has a reproducing function.

That is, the presence or absence of signal charges under the floating gate electrode 33c, which is a well-known example, is detected.
In the present invention, in order to form a potential well for detecting signal charges, a bias electrode 33d provided on the floating gate 33c via an insulating film 32 is placed directly below the floating gate 33c.
This gate 33 is expanded to the region of the insulating film 32 where there is no gate 3c.
A P region 3 is formed at the interface between the insulating film 32 and the substrate 31 without c.
5a was provided. A power supply voltage VB common to the DC electrode 33 is supplied to the electrode 33d. Further, since the impurity concentration of P+ region 35a may be the same as that of P+ region 35, the manufacturing process is simplified. Since the surface potential of P+ region 35a is shallower than the surface potential of substrate 31 under gate 33c, a step in potential is created on the semiconductor surface under electrode 33d. In a conventional floating gate amplifier, a step diamond of this potential was formed by applying separate voltages to two electrodes, but according to the present invention, the surface of the substrate 31 under the electrode 33c is formed using only a single electrode. can generate a potential well. However, since the bias electrode can be shared with the power source VB of the DC electrode that forms the potential distribution during charge transfer, the number of external sources to be supplied to the memory system is reduced. FIG. 5 shows a planar structural diagram of a floating gate amplifier using the aforementioned floating gate, bias electrode, and P+ region as charge detection means.

FIG. 6 also shows a sectional view taken along the line x-X' in FIG. In FIGS. 5 and 6, each number means the same component as shown in FIG. 3. In addition, the output terminal 00 of the amplifier is connected to the output signal line Di (i=1...4) in FIG.
corresponds to Assume now that, as shown in FIG. 3, at time t, signal charges 38c are stored under the electrode of the transfer gate J adjacent to the floating gate amplifier. At this time,
The surface below floating gate 33c is fixed at potential 36f. At time t2, the signal charge is transferred to the potential well 36f generated under the electrode of the floating gate, and is stored in this potential well while the transfer pulse J maintains the level (VP). Then, the surface potential under the electrode 33c becomes shallower in accordance with the amount of stored charge. When a signal charge of ΔQ is stored under the electrode 33c at a certain time, the potential fluctuation ΔV of the electrode of the floating gate 33c with respect to the substrate is given by the following equation. Here, c, is the signal charge Q and the floating gate 33
c2 is a capacitor between floating gate 33c and bias electrode 33d, c3 is a capacitor between signal charge ΔQ and substrate 31 (connected to ground 0), c
4 is a capantor between floating 33c and P++ region 39, c
5 is a MOS whose drain is 34c and source is 34d.
Represents the input gate capacitance of a transistor.

'11 type is the original of Solid State Circuits (IE3) published by King 12 in 1974.
JomM1 of Solid - Sta to Circu
"Design and Observation of a Floating Gate Amblyire (Desi Rice and Operati)" published on page 410 and later of iG)
Amplihe onof a FloatingGa
r)” is described in the paper.

The voltage change ΔV at the gate 33c is amplified by the source follower type amplifier shown in FIG. 5 and is generated at the output terminal DO. The source follower type amplifier has a gate 33c, an N0 region 34c connected to the positive power supply VPP, an N0 region 34d connected to the output terminal DO, an output terminal DO and a ground terminal 0.
It consists of a resistor R provided in between. The impurity degree of the N+ regions 34c and 34d may be the same as that of the N+ regions 34a and 34b shown in FIG. The resistance R may be a diffusion layer having a layer resistance of several hundred Q/□ or a passive element provided externally.
A MOS transistor consisting of a gate 33c, a drain 34c, and a source 34d is integrated into an IC on the same chip as the CCD. When the voltage change at the gate 33c is ΔV, the voltage variation ΔVo generated at the output terminal DO is ΔV, where gm is the mutual conductance of the MOS transistor. =△v,
Hayabusa R. -. If the voltage of the output DO of the source follower type floating gate amplifier when there is no signal charge is VsB, then the charge △Q corresponding to the digital signal "1" is supplied to the potential 36f given by the equation: '2. V
When fed, the fin level of the gate 33c increases by △V.

Therefore, the potential of the output terminal DO also decreases by ΔVo, and is set to the potential of Vs. That is, it is detected in the CCD register. Even if the voltage of the transfer pulse becomes 0, the charge remains at a potential of 36
If it is not transferred to f, the potential of the output terminal DO will not fluctuate and will be maintained at the potential of VsB. In this case, CC
Information "0" in the D register is detected as a digit "1". FIG. 4 shows an example in which the signal electrodes 38d and 38c are successively detected in the output signal D◯ from the floating gate amplifier provided near the sink diode of the CCD register during the period T. At the same time, an example is also shown in which a signal charge 38b is detected on the output signal line ○02 from another floating gate amplifier provided in the center of the CCD register. Output signal line DO. Alternatively, the information of D02 is valid during the off period of J. In this way, in the continuous transfer process, the signal charges transferred under the floating gate are constantly output to the output signal D0 or D in synchronization with the clock pulse J.
02 is detected. As mentioned above, the output signal line○
The information reproduced in ○, is re-alerted from the input means to the CCD register during the off period of the write command signal, and continues to be circulated repeatedly. That is, the period T2 in FIG. 4 corresponds to the quasi-cyclic period of data. In Figure 3, a unit consisting of one transfer gate and one DC gate next to it is taken as one bit, and a bias gate for signal charge detection is included.
A CCD register consisting of 6-bit elements t, is shown.

Data group “10” of input line 1 written sequentially after time etc.
11" is sent to the output signal line D02 from the input section 12, and after 3 bits are transferred, the data is inverted in chronological order after time t4 and detected as information of "0100'1" as shown in FIG. be done. After time 1, there is no write data, so the information is '11' continuously.On the other hand, after time t4, after 3 more bits are transferred to the output signal line D○,
Information of "010pi" is detected in chronological order after time t5.
After the time, since there is no write data, "1" information continues. The information on this world power signal line ○○ is 1/2
The signal is bit delayed and sent to the input data line D1 through the signal lines 22, 28, and 25 shown in FIG. 2 during the period T2. Then, it is inverted again and “1011” is written in the CCD register.
” information and written. 1/2 bit delay root 4
Kawama is conductive only during the high level period of the gate pulse ◇, which is synchronized with the transfer pulse J, and sends the information on the output signal line ○○ to the signal line 28 as a time-series signal shown in DF in FIG.

Similarly, the information on the output signal line ○02 is delayed by 1/2 bit and sent to the signal line 28 as the signal DF2 in FIG. When the output command signal RE is activated during the L period, the reproduction delay signals DF and DF2 are inverted and read out as data groups "1011" and "100" information to the output lines D, D2, respectively.

Data reading to output lines D3 and D4 is performed in the same manner. Which of the one CD register data or the two output data is selected for signal processing is determined by the function of the external device receiving the data.

The access time is shorter if the information on the A side of the CCD register is output to the output line D. Moreover, information on only the output line D, or only on the output line D2 can be selected by an external device. Further, it is also possible to simultaneously access information on sides A and B and perform signal processing. Furthermore, multiple CCD registers can be accessed/addressed simultaneously. It is also possible to access only a single CCD register.
As mentioned above, CCD register having 6 bits as one column
Although the signal processing process of the CD memory has been described, the gist of the present invention can generally be extended to n-bit CCD registers without detracting from the spirit of the present invention.

In the case of an n-bit CCD register configuration, the average access time ta is equal to n/4 bit transfer time. According to the present invention, an n-bit CCD register (SR) having a playback/output function only at one end of the register for serial transfer is provided.
Compared to the configuration memory, ta is shortened by 1 to 2. Furthermore, a CC in which the above PRs of n/2 bits are arranged in two columns in parallel.
Since there is one less input means than the D memory, the integration density can be improved and a large-capacity memory can be realized. In addition, each CCD
Since register transfer is performed by one-phase drive, clock pulses to be supplied to the CCD register can be easily generated.
It also becomes easy to integrate the crop pulse generator and the CCD memory on the same chip. In addition, since the power supply to be supplied to the floating gate amplifier for reproduction can be used in common with the DC gate of the CCD register, the number of power supplies is small, and the CCD
Memory can be realized. Furthermore, since the CCD memory of the present invention has a playback function, it has the feature that once written information can be read out non-destructively. Furthermore, it is possible to write/read data (1/0) simultaneously to each CCD register in m columns, and to perform 1/0 operation every division.
Only one or some of the D registers can be set to 1.
/0 operation is also possible. Another feature is that information stored on both sides of the CCD register can be displayed at the same time, with the central portion of each CCD register serving as a boundary. From an embodiment of the invention, each CC of n bits
It is obvious that even faster access can be achieved by providing the output means described in this specification at locations where the D register is divided into a plurality of parts.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a charge-coupled memory configuration according to an embodiment of the present invention, and FIG. 2 is a diagram showing two charge-coupled registers and their peripheral circuits constituting the charge-coupled memory of the present invention.
FIG. 3 is a sectional view of one charge-coupled resistor, FIG. 4 is a diagram showing operating waveforms of the memory of the embodiment shown in FIGS. 2 and 3, and FIG. 5 is an output means of the charge-coupled memory. plan view of
FIG. 6 is a sectional view of the output means shown in FIG. 5. In the figure, 10... Reproduction signal line, 11... CCD
Register, 1, ~13... Input line, D, ~A6... Output line, 12... PN junction diode, 13a, 13b...
Floating gate amplifier, 14... sink diode, 15
, 16, 17, 21, 29... gate circuit, 18, 1
9... Buffer amplifier, 20, 30... Inverter, 40.
... Delay gate, 31... P-type semiconductor substrate, 32... Insulating film, 33... Electrode Y 34... N+ region, 35...
...P-region. Murasaki'zu 2 Hiiragizu zu ~ Sphere ※ *4 fig.

Claims (1)

[Claims] 1. A charge-coupled register having an input means for inputting a data signal charge is provided with data signal charge detection and amplification means in each of the central part and the terminal part, and is selected by an address signal supplied from the outside. A control circuit that activates a write command signal to shift data to the charge-coupled register, and a data signal charge detection amplification means provided at the terminal end of the charge-coupled register delays the data reproduced by 1/2 bit, and a control circuit for shifting the data into the charge-coupled register via the input means when the write command signal is inactive; and a central portion and a terminal portion of the charge-coupled register when the read command signal is activated. A charge-coupled memory comprising: a control circuit for simultaneously accessing reproduction delayed data from a data signal charge detection and amplification means provided in a charge-coupled memory. 2. A bias electrode in which data signal charge detection and amplification means is provided via an insulating film on a semiconductor substrate, a floating gate electrode embedded in the insulating film under the bias, and the semiconductor substrate under the floating gate electrode. The charge is generated by converting the charge supplied by a signal charge detection section formed of an impurity region having a higher concentration than the semiconductor substrate provided on the surface portion and a control means provided adjacent to the signal charge detection section. The invention is characterized in that it is constituted by an amplifier circuit that generates a potential change of the floating gate electrode as a voltage change between a resistor connected to the source of a MOS transistor using the floating gate electrode as a gate, and ground. A charge-coupled memory according to scope 1.