JPS6035778A - Magnetic display - Google Patents

Magnetic display

Info

Publication number
JPS6035778A
JPS6035778A JP14469483A JP14469483A JPS6035778A JP S6035778 A JPS6035778 A JP S6035778A JP 14469483 A JP14469483 A JP 14469483A JP 14469483 A JP14469483 A JP 14469483A JP S6035778 A JPS6035778 A JP S6035778A
Authority
JP
Japan
Prior art keywords
display
circuit
small
drive circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14469483A
Other languages
Japanese (ja)
Other versions
JPH0135355B2 (en
Inventor
武田 鷹士
幸雄 工藤
山本 芳孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Frontech Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Frontech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Frontech Ltd filed Critical Fujitsu Ltd
Priority to JP14469483A priority Critical patent/JPS6035778A/en
Publication of JPS6035778A publication Critical patent/JPS6035778A/en
Publication of JPH0135355B2 publication Critical patent/JPH0135355B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は一般市販の単体形磁気表示器(以下表示器と略
す)と表示器駆動用信号増幅回路(以下バッファ)を1
体化した磁気表示装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention relates to a single unit magnetic display device (hereinafter referred to as a display device) and a signal amplification circuit for driving the display device (hereinafter referred to as a buffer).
The present invention relates to an embodied magnetic display device.

(2)従来技術及び問題点 従来の表示器は外部からの信号で直接駆動するようにな
っていた。この表示器を駆動する場合通常のL’EI)
表示器駆動に比して入電iQを要するために、表示器と
LED表示器が混在するシステムに於てはLED表示器
駆動用に小容量形駆動回路を、表示器駆動用に大容量形
駆動回路を用意しなLJればならない不都合があった。
(2) Prior Art and Problems Conventional displays are directly driven by external signals. When driving this display, normal L'EI)
Since input power iQ is required compared to driving a display, in a system where a display and an LED display are mixed, a small-capacity drive circuit is used to drive the LED display, and a large-capacity drive circuit is used to drive the display. There was the inconvenience of having to prepare a circuit for LJ.

また小官■:形駆動回路に統一すると表示器用に別に増
幅回路を設りねばならずシステム構成が庚5“Il、に
なり、逆に大容量形駆動回路に統一するとシス1アツプ
になる欠点があった。
Also, a small point: If you unify to a large-capacity type drive circuit, you will have to install a separate amplifier circuit for the display, resulting in a system configuration of 5"Il," and conversely, if you unify to a large-capacity type drive circuit, the system will increase in size. was there.

またさらに従来の表示器では駆動に際してパルス駆動す
る必要があり、LED表月く器用は1ヒツトの連続信号
にし、表示器用は反転用と復旧用の2ビットのパルス信
号にしなければならない不便があった。加えて表示器は
平常の状態表示時は消費電力が零という利点がある半面
、状態変化時に於りる表示器の反転・復旧峙は消費電力
がL IF、 D表小ン:(に比して非常に大きいとい
う欠、1j、l、がある。
In addition, conventional displays require pulse drive when driving, and there is the inconvenience that a one-bit continuous signal must be used for the LED display, and a two-bit pulse signal for inversion and recovery for the display. Ta. In addition, while the display has the advantage of consuming zero power when displaying normal conditions, it consumes only a small amount of power when reversing and restoring the display when the status changes. There is a defect, 1j,l, which is very large.

1足−1“(表小器を状態表示用として多数使用するン
スう一〕・の場合、平常時用にば消費電力か零でも全表
小器が−・斉に状態変化した場合を想定すると非富に大
きな電源装置を用意しなければならない欠点かあった。
In the case of 1 foot - 1 " (a case where many small devices are used for status display), assume that all small devices change their status at the same time even if the power consumption is zero in normal times. Then, there was a drawback that a large power supply device had to be prepared.

(3)発明の目的 本発明の目的は上記問題点を解決するために表示器側に
1ビットの状態表示用連続信号及び1ビットの駆動タイ
ミング用パルス信号の増幅回路とAND回路を含むへソ
ファを1体として組み込む。
(3) Object of the Invention The object of the present invention is to solve the above-mentioned problems by including an amplification circuit and an AND circuit for a 1-bit status display continuous signal and a 1-bit driving timing pulse signal on the display side. Incorporate as one body.

それによりLED表示器と同様に小容量形駆動回路で且
つ1ビットの連続信号で直接駆動可能にしただけでなく
、多数表示器が一斉に状態変化表示をしないように表示
タイミングの制御を可能にした表示器を提供するにある
This not only makes it possible to drive directly with a 1-bit continuous signal using a small-capacity drive circuit like an LED display, but also enables control of display timing so that multiple displays do not display status changes all at once. The purpose is to provide an indicator that shows the

(4)発明の要点 本発明は従来表示器を小容量形駆動回路で駆動する場合
に中間に設りていたバッファを表示器と1体化し、その
バッファ内に小容量形駆動回路からの状態表示用信号の
増幅回路の他に駆動タイミング用信裾の受信増幅回路そ
して両信号のAND条件作成回路を設けたことを特徴と
する磁気表示装置である。
(4) Key Points of the Invention The present invention integrates a buffer, which was conventionally provided in the middle when driving a display with a small-capacity drive circuit, with the display, and stores the state from the small-capacity drive circuit in the buffer. This magnetic display device is characterized in that, in addition to an amplification circuit for display signals, a reception amplification circuit for a drive timing signal and a circuit for creating an AND condition for both signals are provided.

(5) 発明の実施例 以1・本発明を図面に基づいて説明子る。第1図は本発
明I実施例の回路構成図で1は磁気表示装置、2は小容
量形駆動回路、3は表示器、4はバッファ、15は表示
タイミンク制御回路をそれぞれ示す。常時表示タイミン
グ制御回路15からの人力信号が無い時、タイミング伯
′弓増幅l・ランノスタ9はOFFで信号電源ライン1
3はO■になっているが、表示タイミング制御回路15
から信号か人力されるとタンミング信℃増幅I−ランノ
スク9はONになり信号電源ライン13は4になる。
(5) Embodiments of the Invention 1 The present invention will be explained based on the drawings. FIG. 1 is a circuit configuration diagram of an embodiment of the present invention I, in which 1 is a magnetic display device, 2 is a small capacity drive circuit, 3 is a display device, 4 is a buffer, and 15 is a display timing control circuit. When there is no human input signal from the constant display timing control circuit 15, the timing output amplifier L/Rannostar 9 is OFF and the signal power line 1 is turned off.
3 is O■, but the display timing control circuit 15
When a signal is input manually, the tamming signal amplification I-rannosk 9 is turned on and the signal power line 13 becomes 4.

従って表示タイミング制御回路15からの入力信号があ
る場合にのみ小容量形駆動回路2の状態をバッファ4で
検出する。小容量形駆動回路2がONの時信号電源ライ
ン13からゾルアップ抵抗10を通して小容量形駆動回
路2に電bitか流れインバータアンプ7の入力は■、
レヘルとなるためインバータアンプ7の出力はI−ルヘ
ル、・インバータアンプ)3の出力はLレベルとなる。
Therefore, the buffer 4 detects the state of the small capacity drive circuit 2 only when there is an input signal from the display timing control circuit 15. When the small capacity drive circuit 2 is ON, a bit of current flows from the signal power line 13 to the small capacity drive circuit 2 through the sol-up resistor 10, and the input of the inverter amplifier 7 is
Therefore, the output of the inverter amplifier 7 becomes I-level, and the output of the inverter amplifier 3 becomes L level.

tjf=って信冒電高Iう・イン13からセy l・コ
イル5を通ってインハークアンプ8の出力へ電流が流れ
゛(セットコイル5が動作し表示器3が反転する。逆に
小容量形駆動回路2がOFFの時信号電源ライン13か
ら入力側への流出電流が無い為インハークアンプ7の人
力は+ルヘルとなる。従ってインバータアンプ7の出力
はLレベル、インバータアンプ8の出力は1■レヘルと
なり、信号電源ライン13からリセットコイル6を通っ
てインハークアンプ7の出力へ電流か流れてリセットコ
イル6が動作し表示器がfjH[:目−る。この際表示
タイミング制御回路15がらの信号を表示器3が反転・
復旧するに必要なパルス幅とすることによりパルス駆動
が可能となる。
tjf=A current flows from the input 13 through the coil 5 to the output of the in-hark amplifier 8 (the set coil 5 operates and the display 3 is reversed. When the small capacity drive circuit 2 is OFF, there is no current flowing from the signal power supply line 13 to the input side, so the power of the inverter amplifier 7 is +l. Therefore, the output of the inverter amplifier 7 is at L level, and the output of the inverter amplifier 8 is at L level. The output becomes 1■ level, and a current flows from the signal power line 13 through the reset coil 6 to the output of the in-hark amplifier 7, the reset coil 6 operates, and the display changes to fjH[:].At this time, the display timing is controlled. The display 3 inverts the signal from the circuit 15.
Pulse driving becomes possible by setting the pulse width necessary for recovery.

またプルアンプ抵抗10を小容量形駆動回路2の容量に
適した値、そしてプルアップ抵抗11を表示タイミング
制御回路5の容量に適した値に人々設定するごとにより
小容量形駆動回路2や表示タイミング制御回路16は小
容量形に出来る。−″方インバータアンプ7、インバー
タアンプ8そしてタイミング信号増幅トランジスク9の
定格を表示器3を駆動・反転させるに必要十分な値にす
る。
In addition, each time the pull-up resistor 10 is set to a value suitable for the capacity of the small-capacity type drive circuit 2 and the pull-up resistor 11 is set to a value suitable for the capacity of the display timing control circuit 5, the small-capacity type drive circuit 2 and the display timing are set. The control circuit 16 can be of small capacity type. - The ratings of the inverter amplifier 7, inverter amplifier 8, and timing signal amplification transistor 9 are set to values necessary and sufficient to drive and invert the display 3.

回り込み防止ダイオード12は磁気表示装置lの小容量
形駆動回路2からの入力を複数台並列接続し−(表示器
・イミング制御回路1Gからの信号を別々に入力するよ
うなシステムに於て有効とな、5゜本発明の1実施例に
よればバッファを半導体回路で構成しているため磁気表
示装置を小形軽量にできる上、速動速復の動作が出来る
のでパルス駆動に適している。また平常時の消費電流か
零となり表示器使用の効果を100%店か3°ことがで
きる。
The loop prevention diode 12 is effective in a system in which multiple inputs from the small capacity drive circuit 2 of the magnetic display device 1 are connected in parallel (in which signals from the display/timing control circuit 1G are input separately). 5. According to one embodiment of the present invention, the buffer is formed of a semiconductor circuit, so that the magnetic display device can be made small and lightweight, and it is also suitable for pulse drive because it can perform fast-acting and quick-returning operations. The current consumption during normal operation becomes zero, and the effect of using the display device can be reduced to 100% or 3°.

第2図は本発明の他の実施例を示すもので、第1図と異
なるのは小容量形駆動回路2からのイ11伺1rAバッ
フ了をリレーにしたこと−である。ずな才)t)リレー
巻線14は小容量形駆動回路2の容置に通した直流抵抗
の物とし、リレー国点(にの定格はセットコイル5やリ
セットコイルGを駆動するに必要I−分な値とする。動
作は小吉M形4Bg勤回路2かONの11.1リレーS
線14に電流かblされリレー接点IGIJセットコイ
ル5側i:o F Fの時リレーを線14に電流が流れ
ないのでリレ−1u点](i!lすセットコイル6側に
倒れる。リレー接点16は小容量形駆動回路2の状態に
応してセットコイル5側又はリセットコイル6側に倒れ
ているので、表示タイミング制fa11回路15からの
信号かある時にリレー接点16の状態に応して表示器3
は反転又は復旧する。この実施例では部品点数か少く回
路が中線になる効果がある。
FIG. 2 shows another embodiment of the present invention, which differs from FIG. 1 in that the I11 and 1rA buffers from the small capacity drive circuit 2 are replaced by relays. t) The relay winding 14 is a DC resistor passed through the container of the small capacity drive circuit 2, and the relay winding 14 is rated at the I required to drive the set coil 5 and reset coil G. - minute value.The operation is Kokichi M type 4Bg circuit 2 or ON 11.1 relay S
When the current flows through the wire 14 and the relay contact IGIJ sets coil 5 side i:o F 16 is tilted toward the set coil 5 side or the reset coil 6 side depending on the state of the small capacity drive circuit 2, so that when there is a signal from the display timing control fa11 circuit 15, the signal is turned on depending on the state of the relay contact 16. Display 3
is reversed or restored. This embodiment has the effect that the number of parts is small and the circuit becomes a center line.

(7)発明の効果 本発明によれば小容量形駆動回路で一旦磁気表示装置内
蔵のバッファで表示すべき状態を設定し、反転・復旧は
別に設げた表示タイミング制(311回路で行うので、
表示器用と1.、 IE D表示器用とで駆動回路を別
にせず統一して標準化できる効果がある。
(7) Effects of the Invention According to the present invention, the state to be displayed is set once in the buffer built into the magnetic display device using a small-capacity drive circuit, and inversion and recovery are performed using a display timing system (311 circuit) provided separately.
For display device and 1. This has the effect of unifying and standardizing drive circuits for IED display devices without having to use separate drive circuits.

ま)(小容量駆動回路と出来表示装置間に別のパノソア
を設りる必要がないこと、小容量駆動回路からの信号は
1表示器あたり1ヒツトで良いことがら1、E I)表
示器駆動時と同様接続か単純になる効果がある。ざらに
表示は表示タイミンク制御回路で行うので多数表示器用
の状態が一斉に変化しても、表示器の反転・)M旧を順
序よく制御するごとがuJfiヒであり、無用の人きな
電りノ、1装置を用意しなくて良い効果がある。
M) (There is no need to install a separate panosore between the small-capacity drive circuit and the display device, and the signal from the small-capacity drive circuit only needs to be one per display device.1) E I) Display device This has the effect of simplifying the connection in the same way as when driving. Since the rough display is performed by the display timing control circuit, even if the status of multiple displays changes at the same time, it is necessary to control the inversion of the display and (2) There is an advantage that there is no need to prepare one device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明1実施例の回路構成図、第2図は本発明
の他の実施例の回路構成図である。図においillは磁
気表示装置、2は小容量形駆動回路。 3は表示器、4はバッファ、5は七ノI・コイル。 6番、1リレノ1〜コイル、7,8はインバータアンプ
。 !] L:l夕(ミング信号増幅トランジスタ、10.
11(、Iゾル)′ツブ抵抗、12は回り込み防止ダイ
オ−1,+3は信号電源ライン、J4はリレー/8線。 J 5 II表示タイミング制御回路を示す。
FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of another embodiment of the present invention. In the figure, ill is a magnetic display device, and 2 is a small capacity drive circuit. 3 is a display, 4 is a buffer, and 5 is a seventh I coil. No. 6 and 1 reno 1 to coil, 7 and 8 are inverter amplifiers. ! ] L:1 (mining signal amplification transistor, 10.
11 (I sol) 'tube resistor, 12 is the loop prevention diode -1, +3 is the signal power line, and J4 is the relay/8 wire. The J 5 II display timing control circuit is shown.

Claims (1)

【特許請求の範囲】[Claims] 単体形磁気表示器のセットコイルとりセントコイルの一
端を表示タイミング制御回路に接続し、他端を論理積条
件作成回路を介し”C駆動回路に接続し、該表示タイミ
ング制御回路からの出力パルスと駆動回路からの出力パ
ルスの論理積が取れた時該セットコイルに電流を供給し
、論理積がとれない時該リセットコイルに電流を供給す
る様にした磁気表示装置。
One end of the set coil and cent coil of the standalone magnetic display is connected to the display timing control circuit, and the other end is connected to the "C drive circuit" through the AND condition creation circuit, and the output pulse from the display timing control circuit and A magnetic display device that supplies current to the set coil when the logical product of output pulses from a drive circuit is obtained, and supplies current to the reset coil when the logical product cannot be obtained.
JP14469483A 1983-08-08 1983-08-08 Magnetic display Granted JPS6035778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14469483A JPS6035778A (en) 1983-08-08 1983-08-08 Magnetic display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14469483A JPS6035778A (en) 1983-08-08 1983-08-08 Magnetic display

Publications (2)

Publication Number Publication Date
JPS6035778A true JPS6035778A (en) 1985-02-23
JPH0135355B2 JPH0135355B2 (en) 1989-07-25

Family

ID=15368094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14469483A Granted JPS6035778A (en) 1983-08-08 1983-08-08 Magnetic display

Country Status (1)

Country Link
JP (1) JPS6035778A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155143A (en) * 1974-06-03 1975-12-15
JPS575668U (en) * 1980-06-11 1982-01-12

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50155143A (en) * 1974-06-03 1975-12-15
JPS575668U (en) * 1980-06-11 1982-01-12

Also Published As

Publication number Publication date
JPH0135355B2 (en) 1989-07-25

Similar Documents

Publication Publication Date Title
US4050064A (en) Four-level voltage supply for liquid crystal display
JP4147360B2 (en) Two-port SRAM
JPS6035778A (en) Magnetic display
JPS60170320A (en) Cmos output drive circuit
JPS58198084A (en) Display element
US5594362A (en) Gatable level-pulling circuit
EP0124535A4 (en) Buffer circuit.
JPH0469896A (en) Sense amplifying circuit
JP2782946B2 (en) Semiconductor integrated circuit
JP3101091B2 (en) Enable circuit
JPH11186881A (en) Latch device
JPS62214583A (en) Memory output circuit
JPS5869121A (en) Semiconductor integrated circuit
JPH0573491A (en) Bus circuit
JPH04313864A (en) Magnetic disk device
JPS61217906A (en) Writing circuit of magnetic storage device
JPH05268050A (en) Output buffer circuit
JPS6035789A (en) Liquid crystal driving circuit
JPH06162777A (en) Storage circuit device
JPS6129485A (en) Memory circuit
JPH03185604A (en) Head selection circuit
JPS62112203A (en) Writing circuit for magnetic storage device
JPH04329453A (en) Information processor
JPH02121189A (en) Semiconductor memory
JPS62188091A (en) Cmos type semiconductor memory circuit