JPS6035754B2 - Count display method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for counting and displaying the amount of tape travel in a magnetic tape reproducing device such as a cassette tape recorder.

In magnetic tape playback devices such as cassette tape recorders,
Generally, the amount of tape running is displayed using a mechanical tape counter, but in recent years, electro-optical display devices such as liquid crystal display devices have been used in addition to this tape counter, and various types of display devices including the amount of tape running have been used in this display device. Systems that simultaneously or exclusively display information such as timing information are being considered and are being put into practical use.

By the way, when the above-mentioned display device displays various other information in addition to the tape running amount, in other words, when the device itself such as a cassette tape recorder has the function of handling the above-mentioned other information, the internal In addition to counting the amount of tape travel, the circuit must simultaneously perform a timekeeping operation to obtain timekeeping information, a count content determination operation for repeat play, etc. However, when these operations are performed using sequential control using a microprogram, especially when high-speed count pulses are output, that is, when the tape is running quickly, count pulses may be input while other functions are being controlled. There was a risk of a counting error. Fig. 1 is a time chart showing such a conventional example, and shows a pulse as shown in Fig. 1a (the output period of this pulse is in a 1:1 relationship with the rotation period of the capstan shaft or reel shaft). , this rotation period is a period of rotation of , art, third order, or less)
When is output, the counting section in the device performs a counting operation in synchronization with the rising edge of the pulse as shown in Fig. 1b, and then judgment operations for repeat play etc. are performed as shown in Fig. 1c. .

However, as shown in Figure d, other processing, such as a timing operation, is performed following the above judgment operation, and if that processing and the rising edge of the input pulse are perpendicular to each other, the counter recognizes that there is a new input pulse. It could not be detected, and in the end, the counting section assumed that there was an input as shown in figure e, and the figure f
Obtain the count value shown in . In addition, this count value is “10
It is assumed that it started with '. Here, as is clear by comparing the input pulse shown in Figure 1a with the counting pulse shown in Figure 1e, the count value is "12".
A counting error occurs when proceeding from "13" to "13", and in such a conventional tape counter, the reliability of the tape counter is lost. Therefore, in order to prevent such malfunctions, a method can be considered to separate the counting function section of the tape counter from the circuit system that processes other information and operate it independently, but such a method requires that the circuit configuration is complicated. The drawback was that it not only became more expensive, but also more expensive.

In addition, when a liquid crystal display device is used as a display device, it becomes difficult to read the display contents due to the response speed of the liquid crystal display element, especially when running at high speeds such as fast forwarding or rewinding. There was also the problem that it was difficult to stop the tape running at the position where the tape counter was running, and the function of the tape counter could not be fully demonstrated.

The present invention has been made in view of the above circumstances, and eliminates the drawbacks of the conventional method by displaying the results of skip counting for the amount of tape travel, and achieves high counting accuracy and ease of discussion. The purpose is to provide a counting display method. In order to achieve the above-mentioned object, the present invention is designed to provide "n" or a predetermined value based on this "n" (for example, a length of It was done as if counting by
An example in which counting is performed in increments of "n" will be described below with reference to FIGS. 2 to 5.

Figure 2 shows the schematic configuration of this embodiment.
is a cassette tape.

This cassette tape is mounted on the mounting section 2, and a pinch roller 4 is rotated by a capstan shaft 4a that rotates with the rotation of the motor 3 by a predetermined interlocking mechanism (not shown).
b and the reel shafts 5, 52. The motor 3 is provided with a first pulley 6 directly connected to the motor shaft for rotationally driving a pulse generator 8, which will be described later, in addition to the above-mentioned interlocking mechanism for the capstan shaft 4a, etc. The rotation of the first pulley 6 is caused by the belt 7
A second pulley 9 provided on the pulse generator 8 by
transmitted to. The rotation ratio between the first pulley 6 and the second pulley 9 is a:b (the rotation ratio between the capstan shaft 4a or the reel 5, 52 and the second pulley 9 is n).
:1), and a 1/n frequency divider is constructed by mechanical means. The pulse generator 8 is composed of a second pulley 9, a disc-shaped electrode 10 and a detector 11, which are integrally configured, and the detector 11 is in elastic contact with the periphery of the disc-shaped electrode 10. . In addition, an insulating part is provided on a part 10a of the periphery of the disc-shaped electrode 1, and at least the periphery thereof is conductive, and this conductive part is grounded via the rotating shaft. . On the other hand, since the detector 11 is pooled up to a potential of 10 V (volts) via the resistor 12, the rotation of the disc-shaped electrode 10 causes the detector 11 to relatively slide on its periphery. Logic “1” (
10V) and "0" (ground) outputs are obtained. That is,
This output is transmitted between the insulating part 10a of the disc-shaped electrode 10 and the detector 11.
It is "1" when it is in contact with the detector 11, and it is "0" when the detector 11 is in contact with the surrounding green (conductive) other than the insulating part 10a of the disc-shaped electrode 10. The rotation period of the capstan shaft 4a or the reel shafts 5, 52 (hereinafter, the capstan shaft 4a and the IJ-le shafts 5, 52 will be simply referred to as the drive section) is in a relationship of n:1. The output signal obtained from this detector 11 is input to a one-shot circuit 13 which detects a rise from logic "0" to "1" and generates a one-shot trigger pulse. On the other hand, 14 is each controller 15a, 15 that controls other functions such as mileage counting, timekeeping, and judgment.
b and 15c, and each of these controllers 15a to 15
The trigger pulse outputted from the one-shit circuit 13 is applied to the distance counting controller 15a.

The traveling distance count controller 15a outputs a counting command signal by applying this trigger pulse,
It is applied to one input terminal of the AND gate 17 as an opening/closing control signal. Further, the code signal "n" output from the code generator 18 is applied to the other input terminal of the AND gate 17, and every time a counting command signal is applied from the AND gate 17, the code signal "n" is outputted from the code generator 18. A code signal is output and given to the counting circuit 16. Therefore, in the counting circuit 16,
Counting by "n" is performed every n rotations of the drive section. The controllers 15a to 15c exchange control signals (for example, address signals) with each other, and operate as a sequential controller as a whole. In addition, the counting circuit 16 includes a counter for counting the running distance of the tape as well as a counter for timing, etc. The contents of each of these counters are appropriately selected and sent to the display section 19, and the contents of each counter are selected as appropriate and sent to the display section 19. Or displayed exclusively. Further, there is a travel drive control section that controls the running of the tape, etc., and this control section performs various controls while exchanging control data with the logic section 14 described above. Next, the specific configuration of the logic section 14 in FIG. 2 will be explained with reference to FIG. 3.

Note that since the logic section 14 in FIG. 2 shows its outline, it will be explained with new reference numbers in FIG. This is a ROM (read only memory) in which a microprogram that controls the operation of each circuit in the logic section 14 is fixedly stored, and from this ROM 21, row address designation signals [Fu] and [Su] are sent to the RAM 22, which will be described later. ], counting data “
code signal [C] such as "n", column address designation signal [F, SL] that specifies the processing column of the RAM 22, various operation commands [INS], and next address signal [NA] that specifies the next address of itself. The next address signal [NA] is input to the address decoder 25 via the address modification circuit 23 and address buffer 24. The address decoder 25 specifies the address of the ROM 21 based on input address information, and the ROM 21 and the address decoder 25 perform sequential control of each circuit. Further, the row address designating signals [Fu] and [Su] outputted from the ROM 21 are applied to AND circuits 26 and 27 whose opening and closing are controlled by timing signals t and t,', respectively (the timing signals will be described later). The address designation signals [F, SL] are sent to the column address controller 28, which includes an address counter that specifies and controls processing columns (so-called digits) of the RAM 22, and the operation command [WS] is sent to the column address controller 28, which includes an address counter that specifies and controls processing columns (so-called digits), and the operation command [WS] decodes the contents of this command and sends various control signals. The signals are sent to an instruction decoder 29 which outputs control signals for the mountain to mountain 2 and column address controllers 28, respectively. Further, the output of the code signal [C] is sent to three AND circuits whose opening and closing are controlled by the control signal q output from the instruction coder 29. On the other hand, the above-mentioned marks AM22 are arranged in an area A for counting the running distance of the tape arranged in the row direction (hereinafter referred to as area A) and an area B for counting time (hereinafter referred to as area B). B
Each register is designated by the collective output of the AND circuits 26 and 27, that is, by the row address designation signal [Fu] or [Su] of the ROM 21. This is done by applying it to the row address input end [RAU] of the RAM 22.

Further, the column to be processed is column address controlled based on the column address designation signal [F, SL] output from the ROM 21. This is done by applying the column address output from the controller 28 to the column address input terminal [RAL] of the RAM 22, and the RAM 22 inputs each of these address input terminals [RAU].
] and [RAL], data at that address is output from the output terminal [OUT].
In addition to the above-mentioned addresses, the RAM 22 is also applied with the output of the band circuit 31 to which the timing signal t3 and the control signal o2 are applied, and as a read/write control (R/W) signal. When the signal is "0", reading is being performed, and when the signal is "1", writing is being controlled. Therefore, if the data output from the output end [OUT] of the RAM 22 is the content of the register specified by the row address designation signal [Su], the data is output from the read clock t. The buffer 32 to which g, is applied, the open/close control signal is sent to one input terminal a of the arithmetic circuit 34 via the AND circuit 33 to which o3 is applied, and designated as the row address designation signal [Fu]. If the contents of the register are the same, the opening/closing control signal t. - It is sent to the other input terminal b of the arithmetic circuit 34 via the AND circuit 35 to which o4 is applied.

Note that the AND circuit 35 includes the output of the AND circuit 30,
That is, the code signal [C] output from the ROM 21 is also applied, and is sent to the other input terminal b of the arithmetic circuit 34 in the same way as the data read from the RAM 22. This arithmetic circuit 34 is composed of an adder and its peripheral circuits that execute operations such as addition and subtraction under the control of the control signal 34, and executes predetermined operations based on data input from input terminals a and b. The result (data) and carry/borrow signal are output. Thus, the data output from the arithmetic circuit 34 is transferred to the data input device [IN] of the RAM 22.
] and is applied to the output decoder 36 and OR gate 37, and the RAM 22 receives the above-mentioned R/W signal “
1", the data applied to the data input terminal [IN] is written. The address to be written in the RAM 22 is specified by the same address specification as the above reading. Also, the output decoder 36 receives the control signal o6 from the above control signal o6. The travel drive control unit shown in Fig. 2 outputs two control signals, and also converts the input data into display data, and converts the input data into display data using a plurality of buffers provided corresponding to each display digit. The display buffer 38 statically stores the display data sent from the output decoder 36, and its output is transmitted through a predetermined drive circuit (not shown) as shown in FIG. On the other hand, the output of the OR gate 37 is released to the data side latch 89a of the judgment latch circuit 39 controlled by the control signal o7, and the carry signal output from the arithmetic circuit 34 is /The borrow signal is directly determined by the latch 39.
is applied to the carry-no-borrow side latch 39b.

Therefore, each latch 3 of this judgment latch circuit 39
Outputs JL and JH of 9a and 39b are connected to OR gates 23a and 23b of the address modification circuit 23 via AND gates 40 and 41, respectively, which are controlled to open and close by the control signal o8.
and modifies the next address signal [NA] output from ROM21. Further, 42 is an oscillator composed of a crystal oscillator or the like that outputs a fundamental frequency for timekeeping, and its oscillation output is applied to a frequency divider 43 having a predetermined number of stages.
The frequency divider 43 outputs a 1-second period signal (1-second signal) and applies it to a 1-second latch 44 that stores that the 1-second signal has been output.

The output of this one second latch 44 is the control signal o9.
It is sent to the OR gate 23c of the address modification circuit 23 via the AND gate 45 whose opening/closing is controlled by , and modifies the next address signal [NA] output from the ROM 21 similarly to each output of the judgment latch circuit 39. Furthermore, the second
The output of the one-sit circuit 13 in the figure is applied as a set signal to a counting latch 46 which has the same function as the one-second latch described above, and the output of this counting latch 46 is applied to an AND gate whose opening and closing are controlled by the control signals o and o. 47 to the OR gate 28d of the address modification circuit 23,
The next address signal A] is modified in the same manner as described above. Note that each of the latches 44 and 46 receives the control signals o, 46, respectively.
．． and o8.
Further, clock signals ◇,,02 for driving each of the above circuits are outputted from a predetermined frequency dividing stage of the frequency divider 43, and these clock signals ◇,, ? 2 is sent to each of the above circuits and also to the timing signal generation circuit 48.

The timing signal generation circuit 48 outputs timing signals t, , t, and t3 that are not superimposed and are output in sequence according to the input clock signals 0, , and 2, and sends them to each of the gate circuits described above. It is also sent to the instruction decoder 29. The timing signal generation circuit 48 generates the timing signal t3 because the RAM 22 in this embodiment operates in three phases as shown in Table 1. Table 1 Next, the operation of the above configuration will be explained with reference to the flowchart of FIG. 4 and the time chart of FIG. 5.

In FIG. 4, step A detects the set state of the counting latch 46, and the instruction decoder 29 outputs a control signal b.

is output, and the output of the counting latch 46 is output to the AND gate 47.
The signal is applied to the OR gate 23d of the address modification circuit 23 via the address modification circuit 23. At this time, the logic of the bit to be input to the OR gate 23d of the next address signal [NA] output from the ROM 21 is set to "0", and when the counting latch 46 is in the set state, that is, the deflection output is "1". is address-modified, but in the reset state, that is, when its output is "0", the address is not modified and the process proceeds to step B. Step B is to detect the set state of the one-second latch 44 by the same means as detecting the set state of the counting latch 46, and the instruction decoder 29 outputs the control signal o9, and the output of the one-second latch 44 is output from the AND gate. 45 to the OR gate 28 of the address modification circuit 23
applied to c. If the 1-second latch 44 is in the set state, the address is modified, but if it is in the reset state, the address is not modified and the process returns to step A, where the count and 1 second latch 44 are set.
The latch state detection operations of steps A and B continue to be executed until either of the second latches 46, 44 is set. If, at time t shown in FIG. 5, there is an output from the one-shot circuit 13 as shown in FIG. 5b, the counting latch 46 is set as shown in FIG. After the modification, the counting process of steps C to E is performed as shown in g of the same figure. Step C is to reset the counting latch 46 which is in the set state, and the instruction decoder 29 outputs the reset control signal b. 2 is output, the counting latch 46 is reset, and the process proceeds to step 0. Step D is R
It performs counting for the counting A register in the AM22.The row address designation signal [Su] of the ROM21 indicates the row address of the A register, and the code signal [C] indicates "n=3" (here, n=3). The reason for this is that in this embodiment, the relationship between the rotation period of the drive section and the output period of the one-sit circuit 13 is set to 3:1, and this code can be arbitrarily set according to the above relationship). The designation signals [F, SL] output column addresses for designating processing columns "1 to 4", and the operation command [INS] outputs an instruction for instructing addition. Therefore, from the data output terminal [OUT] of the RAM 22, the contents of the A register (assuming that the contents are "m-6") are sequentially read out one digit at a time, and are passed through the buffer 32 and the AND circuit 33 at t2. and t3 timing signals are applied to one input terminal a of the arithmetic circuit 34. on the other hand,
The code signal "3" is applied to the other input terminal b of the arithmetic circuit 34 via AND circuits 30 and 35, and the code signal "3" is applied to the other input terminal b of the arithmetic circuit 34.
are the data ``m-'' applied to each input terminal of a and b.
6'' and ``8'' are operated under the control of the control signal Q output from the instruction decoder 29 that instructs addition, and the result ``m-3'' is transferred to the data input terminal [I of the RAM 22].
N]. The RAM 22 is connected to this data input terminal [I
The data "m-3" inputted into the A register is stored again in 1 to 4 digits of the A register, and the process then proceeds to step E. Step E
is to send the count contents of the A register calculated and updated in step D to the display buffer 38, and
The contents of the A register are sequentially outputted one digit at a time from the data output terminal [OUT] in the same way as in step D above, and the contents "m-3" are outputted via the buffer 32, AND circuit 33, and arithmetic circuit 34. The signal is sent to the decoder 36. The output decoder 36 converts the input data "m-3" into display data and sends it to the display buffer 38. Therefore, the display device 19 displays the stored content of the display buffer 38 "m-3".
' will continue to be displayed until the next update. When this step E is completed, the process proceeds to step F at time t2 as shown in FIG. That is, in step F, the contents of the A register are sequentially read out one digit at a time by the same operation as in step D, and sent to one input terminal a of the arithmetic circuit 34, and the code signal [C] is Outputs "m". The instruction decoder 29 sends a subtraction command (control signal) to the arithmetic circuit 34, a control signal o7 to the judgment latch circuit 39, and an AND gate 4.
The opening/closing control signals o8 of 0 and 41 are output, and the arithmetic circuit 34 executes "(m-3)-m" subtraction. The result of the judgment in step F is made by modifying the next address signal A], which is the same as in steps A and B above, but when at least the data side latch 39a of the judgment latch circuit 39 is set by the above judgment. That is, if the judgment result is "NO", the output JL is applied to the OR gate 23a of the address modification circuit 23 via the AND circuit 40, and at the fifth time t3, the step B is executed.
Return to If the one-second latch 44 is not yet set in step B, the latch state detection operation continues to repeat steps A and B by the same operation as described above. Time t during this latch state detection operation
4, when the 1 second signal is output from the frequency divider 43 as shown in FIG. 5c, the 1 second latch 44 is set by the output signal as shown in FIG. Detected. Therefore, in step B, the output "1" of the 1-second latch 44 is applied to the OR circuit 23c via the AND circuit 45, and the process then proceeds to step G and the time counting process of the processing date, as shown in FIG. 5i. Step G is 1 second latch 4
4, and the control signals o, . This is accomplished by outputting the following, and then the processing step proceeds. This processing date is stored in B of RAM22.
It also performs calculations for "11" seconds on the timekeeping information stored in the register and conversion processing to obtain timekeeping information for 6G vessels, 12 digits, or 2-ship Hayabusa, and when this process is completed at time t5. Next, the process returns to step A again and repeats steps A and B as shown in FIG. However, when time k' comes, the fifth
As shown in Figure b, a trigger pulse is output from the one-shot circuit 13, and the counting latch 46 is set as shown in Figure d. Therefore, in step A, a determination result of "YES" is obtained by the address modification described above, and then, as shown in FIG. ” is RAM22
The data is written into the A register of , and is sent to the display section 19 for display. After completing this series of counting processes, the counting contents are determined in step F as shown in FIG. Latch circuit 3 for determining the result of
Both latches 39a and 39b of No. 9 are not set, and the process then proceeds to process 1 as shown in FIG. 5j. Processing 1 performs various processes for outputting control signals such as stopping traveling to the traveling drive control section 20, and this control signal is sent to the output decoder 3.
6 and sent to the travel drive control section 20.
When this process 1 is completed, the process returns to step B (time) and the latch state detection operation consisting of steps A and B is performed. Next, regarding the case in which the maximum processing time is required in the flowchart of FIG.
A case in which a 1 second signal is output will also be explained.

That is, during the latch state detection operation consisting of steps A and B. When the trigger pulse is output from the one-shit circuit 13 as shown in FIG.
6 is set as shown in d of the same figure, the process proceeds from step A to step C, and the counting process of steps C to E is performed as shown in g of the same figure. It is assumed that the count value up to the time ratio and o is "m-3", and that the count value becomes "m" through this counting process. It is also assumed that during this counting process, the frequency divider 43 outputs a 1-second signal as shown in FIG. 5c, and the 1-second latch 44 is set as shown in FIG. 5e. However, at time t, . As a result of determining the count contents in step F as shown in FIG. Execute (time 2 to L3) and return to step B. In step B, the set state of the one-second latch 44 is determined by the same operation as described above, but now the one-second latch 44 is set as shown in FIG. 5e.
is in the set state, the determination result is ``YES'', and then a time measurement process consisting of step G and the processing date is performed (time t, 3 to 4), and the process returns to step A. Then, at time t, 5, a trigger pulse is output from the one-shot circuit 13, and the latch state output operations of steps A and B are performed until the counting latch 46 is set. Next, a case will be described in which, contrary to the above example, a one-second signal is output and a trigger pulse is output from the one-shot circuit 13 while the timekeeping operation is being performed.

That is, at time t and 6 during the latch state detection operation consisting of steps A and B, when the 1 second signal is output from the frequency divider 43 as shown in FIG. 5c, the 1 second latch 44 is activated as shown in FIG. As a result of the determination in step B, a time counting process consisting of step G and processing date is performed as shown in FIG. During this counting process, the one-sit circuit 13 to the fifth
When the trigger pulse is output as shown in FIG. b, the counting latch 46 is set as shown in FIG.
6 set status is determined. Therefore, the result of the judgment in step A is "YES", and the one-shit circuit 13
Although there is a slight time delay with respect to the trigger pulse output from the trigger pulse, counting processing and judgment operations based on the trigger pulse are performed as shown in FIGS. 5g and 5 (times 7 to t, 9). As described above, in this embodiment, the rotation period of the drive section and the output period of the one-shot circuit 13 are set to 3:
1, and based on the output of the one-shot circuit 13,
'', even if a process requiring the maximum processing time is performed, the process is completed within one cycle of the output cycle of the one-shot circuit 13, and there is no possibility of a counting error occurring.

Further, in this embodiment, the one-shot circuit 13 and the frequency divider 4
A counting latch 46 and a 1-second latch 44 are provided to hold the outputs of 3 and 1 seconds until each process starts, so even if the outputs are simultaneous in time, one microprogram Even if sequential control using (ROM 21) is adopted, there is no risk of a counting error occurring.

In the above embodiment, the rotation period of the drive unit and the output period of the one-shot circuit 13 are set at a ratio of 3:1.
Although the present invention is not limited to this, the frequency division ratio and the count value can be set arbitrarily.

Further, in the above embodiment, a case has been described in which the frequency divider 8 is formed by mechanical means, but this frequency divider is not limited to the embodiment and can be implemented by other mechanisms or electrical means.

Further, in the above embodiment, a case was explained in which the number of revolutions of the drive unit is counted and displayed, but the present invention is not limited to counting and displaying the number of revolutions of the drive unit, and for example, the number of revolutions of the drive unit is counted and displayed. It is also possible to count and display the running length of the tape based on "n".

That is, in this case, it is sufficient to change "n" in step F in FIG. 4 to a predetermined value. As explained in detail above, the present invention counts "n" or a predetermined value based on this "n" every time a periodic pulse of n:1 is generated with respect to the rotation period of the drive unit, and As a result, by performing skip counting, counting can be performed with a simple configuration and without counting errors, and even if the display device is configured with, for example, a liquid crystal display device, the displayed contents can be easily read. It is possible to provide a counting display method that has various advantages such as:

[Brief explanation of the drawing]

Figure 1 is a time chart showing the operating status of the conventional example;
The figure is a block diagram showing one embodiment of the present invention, and FIG.
4 is a flowchart for explaining the operation of the above embodiment, and FIG. 5 is a time chart of the same. 4a...capstan shaft, 8...pulse generator, 13 one-shot circuit, 14...logic section, 19...display section, 21...ROM, 22...RAM,
34... Arithmetic circuit, 46... Counting latch. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. In a magnetic tape playback device that counts and displays the running distance of the magnetic tape and also performs other processing other than this count display process, a periodic pulse of n:1 is applied to the rotation period of the drive unit that drives the magnetic tape to run. a pulse generating means that generates a pulse, a counting means that counts by n or a predetermined value based on n according to the pulse output from the pulse generating means, and a count content of the counting means is displayed as a running amount of the magnetic tape. a display means, a processing means for performing processing other than the above-mentioned count display processing, and a processing means for controlling the operation of the count display processing in the above-mentioned counting means and the above-mentioned display means at the time of pulse output from the above-mentioned pulse generation means, and controlling the operation between the above-mentioned pulse outputs. and a single control means for controlling the operation of other processes in the processing means.