JPS6035568U - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS6035568U JPS6035568U JP12680183U JP12680183U JPS6035568U JP S6035568 U JPS6035568 U JP S6035568U JP 12680183 U JP12680183 U JP 12680183U JP 12680183 U JP12680183 U JP 12680183U JP S6035568 U JPS6035568 U JP S6035568U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- substrate
- dielectric
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の集積コンデンサ内蔵誘電体基板の斜視
図、第2図は集積抵抗板の斜視図、第3図は本考案の混
成集積回路の斜視図、及び第4図は第3図の回路例を示
す。図中型な部分は次の通りである。
10:コンデンサ内蔵誘電体基板、11,12:電極、
T1〜T89 Tl’〜T、′:外部端子、13:抵抗
板、14:絶縁板、R19R29R39R4:抵抗。FIG. 1 is a perspective view of a dielectric substrate with built-in integrated capacitors of the present invention, FIG. 2 is a perspective view of an integrated resistor plate, FIG. 3 is a perspective view of a hybrid integrated circuit of the present invention, and FIG. 4 is a perspective view of a hybrid integrated circuit of the present invention. An example of the circuit is shown below. The large parts in the figure are as follows. 10: Dielectric substrate with built-in capacitor, 11, 12: Electrode,
T1-T89 Tl'-T,': External terminal, 13: Resistor plate, 14: Insulating plate, R19R29R39R4: Resistor.
Claims (1)
、複数のコンデンサを内蔵する誘電体基板と、前記誘電
体基板の表面に形成された配線パターンと、複数の抵抗
層を表面に固着した絶縁体基板であって前記配線パター
ンの所定個所に搭載結線されている絶縁体基板とより成
る、混成集積回路。A dielectric substrate containing a plurality of capacitors, which is made by laminating a plurality of sets of electrodes and dielectric layers alternately and sintering them together, a wiring pattern formed on the surface of the dielectric substrate, and a plurality of resistance layers on the surface. 1. A hybrid integrated circuit comprising: an insulating substrate fixed to a substrate, the insulating substrate being mounted and connected at predetermined locations of the wiring pattern;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12680183U JPS6035568U (en) | 1983-08-18 | 1983-08-18 | hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12680183U JPS6035568U (en) | 1983-08-18 | 1983-08-18 | hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6035568U true JPS6035568U (en) | 1985-03-11 |
JPH051100Y2 JPH051100Y2 (en) | 1993-01-12 |
Family
ID=30288198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12680183U Granted JPS6035568U (en) | 1983-08-18 | 1983-08-18 | hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6035568U (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4970439U (en) * | 1972-09-27 | 1974-06-19 | ||
JPS5414349U (en) * | 1977-07-02 | 1979-01-30 | ||
JPS5583201A (en) * | 1978-12-19 | 1980-06-23 | Fujitsu Ltd | Associated resistor module |
JPS56164516A (en) * | 1980-05-23 | 1981-12-17 | Tdk Electronics Co Ltd | Composite part |
-
1983
- 1983-08-18 JP JP12680183U patent/JPS6035568U/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4970439U (en) * | 1972-09-27 | 1974-06-19 | ||
JPS5414349U (en) * | 1977-07-02 | 1979-01-30 | ||
JPS5583201A (en) * | 1978-12-19 | 1980-06-23 | Fujitsu Ltd | Associated resistor module |
JPS56164516A (en) * | 1980-05-23 | 1981-12-17 | Tdk Electronics Co Ltd | Composite part |
Also Published As
Publication number | Publication date |
---|---|
JPH051100Y2 (en) | 1993-01-12 |
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