JPS6035398A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To perform a refreshing operation optional times without causing any disturbance to a CPU during the refreshing operation by controlling the frequency of refreshing operation externally and freely with a clock input from a refresh terminal and a refresh frequency input to an address terminal. CONSTITUTION:A refresh frequency input counting circuit 11 operates the internal timer with an activation signal 15 from a refresh control circuit 13 to measure a cycle (minimum cycle) time for the refreshing operation, and outputs an operation instruction signal 17 to a refresh address generating circuit 12 while counting down the refresh frequency at said time intervals, activating the refresh address generating circuit 12. At this time, a refresh control circuit 13 switches an address selector 10 and inputs its refresh address 20 to an address decoder 7 to refresh the line corresponding to the address and perform internal initialization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a dynamic semiconductor memory device that includes a terminal having a chip selection function and a terminal having a refresh control function.

[Prior art]

Conventionally, dynamic semiconductor memory devices that have a terminal with a refresh control function have at least two terminals, CE, CE2 (usually called RAS and CAS), which have a chip selection function, as shown in FIG. (hereinafter referred to as CB, CE2 terminals), a read/write control terminal R/W, and a terminal with a refresh control function called ILi”SH (under ) tFSR;
It's called f3 child. ).

CE] The CE1 clock input to the terminal becomes high level, and after the internal is initialized (precharged), the RF
The built-in refresh control circuit 6, refresh address generation circuit 5, and address selector 4 are activated by the clock signal input from the SH terminal, and by connecting the output of the refresh address generation circuit 5 and the address selector 4, normal operation is performed. Riff 1 using only Cel clock
The same operation as mesh is performed. In other words, one clock input to the 1 (FSH) terminal refreshes one row, and in order to refresh all the rows of the memory cell matrix 8, it takes as many times as the number of memory rows, e.g. , a 64 kilobit memory normally requires 128 clock inputs or &-i: 256 clock inputs.Also, the input to the RFS11 terminal must be kept low for a long time (several tens of 85 times or more). Some devices operate a built-in timer by holding the data, and use this timer to control the refresh interval and perform continuous refresh. Continuous medium heat treatment equipment (
There was also the problem that it was not suitable for refreshing in the CPIJ) cycle.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned problems.
To provide a dynamic semiconductor memory device which can be refreshed an arbitrary number of times without having to restart a CPU during refreshing.

[Structure of the invention]

A dynamic semiconductor memory device of the present invention includes a terminal having a chip selection function and a terminal having a refresh control function. It is activated by a clock input to a terminal with a ti control function, and is initialized internally every time one row of the memory cell matrix is refreshed, and when the specified number of refreshes is completed, a refresh completion signal is sent to the outside. The input signal from the address terminal is taken in as the total refresh count through the address selector by the control signal from the refresh control circuit and the refresh count is counted at the time interval required to refresh the refresh count, and the refresh count is determined in advance. When the specified number of times is reached, a refresh number end signal is output to the refresh control circuit, or by an output signal from the refresh number input old enemy circuit, the output signal from the refresh number input counting circuit, and a control signal from the refresh control circuit. The refresh address generation circuit generates a refresh address.

[Explanation of Examples]

Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

[No. 21] is a block diagram showing a bag portion according to an embodiment of the present invention.

In this embodiment, CEl has a chip selection function.

1tS with CI' terminal and refresh control function
In a dynamic semiconductor memory device equipped with an HF terminal, it is activated by a clock input to the R8l-■F terminal, and is initialized internally every time refresh for one row of the memory cell matrix 8 is completed, and the specified number of refreshes is performed. As soon as the refresh completion signal 1 is sent to the external
A refresh control circuit 13 outputs 4, and control signals 15, 1.6 from the refresh control circuit 13 take in the input signal from the address terminal Ai as the refresh count through the address selector 10, and perform the refresh count necessary to refresh the refresh count. When the refresh count reaches a predetermined count by counting at time intervals, the refresh count end signal 18 is sent to the refresh control 1.
Output to circuit 13 or refresh frequency input counting circuit 11
, the output signal 17 from the refresh frequency input counting circuit 11 and f! from the refresh control circuit 13. j'
The device includes a refresh address generation circuit 12 which generates a refresh address A using a control circuit (19) and a refresh address generation circuit 12. In FIG. 2, 7 is an address decoder.

9 is the I10 buffer s, DIN is the data input terminal, and D.

UT is a data output terminal, and R/~V are read/write terminals.

Here, the CE clock is the main clock that activates the chip and latches the row address.

Also, the CJ'i2 clock is connected to the input/output circuit (I in Figure 2).
This is the secondary clock that activates the 10 buffer 9) and latches the column address.

Next, referring to the flowchart shown in FIG. 3, we will explain the refresh operation by clock input to the RFSI (terminal) in this embodiment. After the initialization (precharging) of the RFSH
Input the clock to the terminal.

Step ■: The refresh control @1 circuit 13 is activated by the clock input to the RFSI (terminal), and this refresh control circuit 13 controls the address selector 10 by 10, and the input to the address terminal A1 (refreshes all cells of the memory). The number of bits corresponding to the number of rows required for (for example, 7 bits for 128 cycles) is not input to the address decoder 7, but is input to the refresh count input counting circuit 11 as the refresh count.

Step ■: The refresh count input counting circuit 11 operates the built-in timer in response to the activation signal 15 from the refresh control circuit 13, measures the cycle (minimum cycle) time required for refresh, and counts down the refresh count at this time interval. At the same time, the operation command signal 17 is output to the refresh address generation circuit 13 to activate the refresh address generation circuit 13. The refresh address generation circuit 12 generates a refresh address 0 address and counts up only when this operation command signal 17 and the control signal 19 from the refresh control circuit 13 are both input.

At this time, the refresh flilJ control circuit 13 controls the address selector IO to input this refresh address to the address decoder 7, thereby refreshing and internally initializing the row corresponding to this address.

Step ■: Further, the refresh count is counted down each time a refresh is performed, and the refresh count is 0.
It is determined whether the

When the number of times reaches 0, the process proceeds to the next step (2), and when it does not become 0, the process returns to the previous step (2).

When the refresh count 01 count becomes 0, the refresh count input counting circuit 11 outputs a refresh count end signal 18 to the refresh control circuit 13.

Step ■: The refresh control circuit 13 performs R1i'
Output a refresh end signal 14 called ED to the outside,
Internally, a series of refresh frequency input counting circuits 11,
Control of the refresh address generation circuit 12 is ended.

With the above steps, the refresh operation is completed.

As explained above, according to this embodiment, by only inputting one clock to the SFH terminal and inputting the number of refresh times to the address terminal, refresh is performed a pre-specified number of times without the need for external control. and internal initialization sequentially, and.

After the refresh is completed, a refresh end signal can be sent to the outside.

[Explanation of effects]

As described above in detail, the dynamic type semiconductor memory device of the present invention has clock input to the refresh terminal,
Since the number of refreshes can be freely controlled from the outside by inputting the number of refreshes to the address terminal, there is an advantage that the refresh can be performed an arbitrary number of times without decouping the CPU during refresh. Therefore, traditional hardware refresh control (
In addition to the number of refreshes), refresh control on software can be executed continuously without requiring control on hardware, and a tri-abbreviated memory system of peripheral circuits can be configured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of an example of a conventional dynamic semiconductor memory device, FIG. 2 is a block diagram showing a main part of an embodiment of the present invention, and FIG. 3 is a block diagram showing a main part of an example of a conventional dynamic semiconductor memory device. 1, which is a flowchart for explaining the operation, 1...CE, timing generation circuit, 2...
... CE2 timing generation thread, 3 ... Read/write control circuit, 4 ... Address selector, 5
...Refresh address generation point; - and 6...
... Refresh control Tsukuda 1 circuit, 7 ... Address decoder, 8 ... Memory cell matrix ---
”, 9...■/'0 buffer, 10...
・Address selector, 11... Riff 1/tush number input counting circuit t 12... Riff/nosh address generation circuit, 13-... Refresh feeding] circuit,
i 4~zO=-・(No. ii, A i, RFSH, C
I, i, , CE2.几／W+DIN+DO
UT “”” terminal.

Claims (1)

[Claims] In a dynamic semiconductor memory device comprising a terminal having a chip selection function and a terminal having a refresh control function, the refresh control function is activated by a clock input to the terminal having the refresh control function, and refresh for one row of the memory cell matrix is completed. There is a refresh control circuit that initializes internally each time a specified number of refreshes is completed and outputs a refresh end signal to the outside when the specified number of refreshes is completed, and an input signal from an address terminal is passed through an address select circuit using a control signal from the refresh control circuit. The number Fi is taken in as the number of refreshes, the number of refreshes is counted at the time interval necessary for refreshing, and when the number of refreshes reaches a predetermined number, a refresh number end signal is output to the refresh control circuit or the number of refreshes is input. A semiconductor memory device comprising: a counter; and a refresh address generating circuit that generates a refresh address based on an output from the refresh frequency input counting circuit and a control signal from the refresh control circuit.