JPS6034850B2 - Level adjustment circuit - Google Patents

Level adjustment circuit

Info

Publication number
JPS6034850B2
JPS6034850B2 JP11753477A JP11753477A JPS6034850B2 JP S6034850 B2 JPS6034850 B2 JP S6034850B2 JP 11753477 A JP11753477 A JP 11753477A JP 11753477 A JP11753477 A JP 11753477A JP S6034850 B2 JPS6034850 B2 JP S6034850B2
Authority
JP
Japan
Prior art keywords
variable resistor
input
circuit
slider
level adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11753477A
Other languages
Japanese (ja)
Other versions
JPS5451444A (en
Inventor
久夫 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP11753477A priority Critical patent/JPS6034850B2/en
Publication of JPS5451444A publication Critical patent/JPS5451444A/en
Publication of JPS6034850B2 publication Critical patent/JPS6034850B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/02Manually-operated control
    • H03G3/04Manually-operated control in untuned amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/24Frequency- independent attenuators

Landscapes

  • Attenuators (AREA)
  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 この発明は例えば録音端子付音量調整回路に好適するレ
ベル調整回路に係り、特にその分岐出力の負荷効果を改
善したものに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level adjustment circuit suitable for, for example, a volume adjustment circuit with a recording terminal, and particularly to a level adjustment circuit that improves the load effect of its branch output.

一般に音響機器等の信号処理系においては信号線路を二
分した一方の線路から他の回路に分岐した出力を導出す
ると共に他方の線路と基準電位点に接続した可変抵抗器
の超動子からしベル調整された出力を次段回路に導出す
るようなことが頻繁に行なわれている。
Generally, in signal processing systems such as audio equipment, a signal line is divided into two lines, and one line is used to derive a branched output to another circuit, and the other line is connected to a reference potential point. The regulated output is often delivered to the next stage circuit.

この場合、分岐出力のレベルが主線路のレベル調整によ
って変動されるようないわゆる負荷効果を生じては好ま
しくない。第1図はこのような代表例として、従来より
採用されていた録音端子付音量調整回路を示すものであ
る。すなわち、これは信号源eINが信号源抵抗Rgを
介して入力端子Nに入力される主線路Lにおいて、録音
機子RECに分岐出力すると共に音量調整用の可変抵抗
器VR,を介して所定のしべルに調整した主線路信号を
得るようにしたものである。なお、図中Rcは主線路に
おける可変抵抗器ち非蜂の回路の入力抵抗である。とこ
ろでこのような回路において録音端子RECから導出さ
れる出力電圧eREcは、となる。
In this case, it is undesirable to cause a so-called load effect in which the level of the branch output is varied by level adjustment of the main line. FIG. 1 shows a conventionally employed volume adjustment circuit with a recording terminal as a typical example of this type. That is, in the main line L where the signal source eIN is input to the input terminal N via the signal source resistor Rg, it is branched out to the recorder REC and is output to a predetermined value via the variable resistor VR for adjusting the volume. This is to obtain a main line signal adjusted to the signal level. Note that Rc in the figure is the input resistance of the variable resistor or non-circuit circuit in the main line. By the way, in such a circuit, the output voltage eREc derived from the recording terminal REC is as follows.

但し、これは可変抵抗器VR,の摺動子2が認意の位置
にあるときであり、式中のR,Nは入力端子mから矢印
方向に見たときの主線路の入力抵抗であり、且つR,2
,R.3はそれぞれ可変抵抗器VR,の摺動子2と上端
1間および同摺動子2と下端3間の抵抗である。また「
分岐出力電圧eREcは可変抵抗器VR,の摺動子2を
最大(上端1側)および最小(下端3側)とした場合に
は(e細C)肌N−支署;・e・N …べ3’とな
る。
However, this is when the slider 2 of the variable resistor VR is in the recognized position, and R and N in the formula are the input resistances of the main line when viewed from the input terminal m in the direction of the arrow. , and R,2
,R. 3 is a resistance between the slider 2 and the upper end 1 and between the slider 2 and the lower end 3 of the variable resistor VR, respectively. Also"
When the slider 2 of the variable resistor VR is set to the maximum (upper end 1 side) and minimum (lower end 3 side), the branch output voltage eREc is (e fine C) skin N - branch;・e・N... It becomes 3'.

但し、ここでRvは可変抵抗器VR,の抵抗であって、
■式の場合‘1}式においてRは=0,R23=Rvと
して且つ‘3}式の場合【11式においてR,2=Rv
,R23=0として与えられる。今、このようにして与
えられる分岐出力電圧eREcの負荷効果ならびに入力
抵抗R…の変化をみるために、Rg=20kQ,Rv=
100kQ(但し直線的特性)、Rc=50kQとして
を可変抵抗器VR,の摺動子1のとる回転角度の数点で
求めると、第3図a,bにそれぞれ破線で示したように
なる。
However, here Rv is the resistance of the variable resistor VR,
■In the case of formula '1}, R = 0, R23=Rv, and in the case of formula '3} [R, 2=Rv in formula 11]
, R23=0. Now, in order to see the load effect of the branch output voltage eREc given in this way and the change in the input resistance R..., Rg=20kQ, Rv=
If 100kQ (linear characteristic) and Rc = 50kQ are determined from several rotation angles taken by the slider 1 of the variable resistor VR, the result will be as shown by broken lines in FIGS. 3a and 3b, respectively.

すなわち、可変抵抗器VR,でレベル調整することによ
って分岐出力電圧eREcの対入力電圧e,N比は約2
.9Bの負荷効果つまり変動を受けるものであり、入力
抵抗R,Nも33日100kQ間で略7皿○弱も変化し
てしまうことがわかる。
That is, by adjusting the level with the variable resistor VR, the ratio of the branch output voltage eREc to the input voltage e,N is approximately 2.
.. It can be seen that the input resistances R and N change by about 7 degrees over a period of 33 days and 100 kQ.

このため、従来可変抵抗器の回転角によって録音レベル
や主線路の入力インピーダンスが変動しないように、信
号線インピーダンスを可及的に低くする目的でバッファ
アンプを介挿したり、あるいは可変抵抗器以降の回路の
入力インピーダンスを十分に高くする手段を講じたりし
ていた。
For this reason, conventionally, in order to prevent the recording level and main line input impedance from changing depending on the rotation angle of the variable resistor, a buffer amplifier was inserted in order to lower the signal line impedance as much as possible, or a buffer amplifier was inserted after the variable resistor. They took measures to make the input impedance of the circuit sufficiently high.

しかしながら、このような対策はコストアップにつなが
る複雑な回路を必要するものであり望ましいものではな
かった。そこで、この発明は以上のような点に鑑みてな
されたもので、簡単な回路構成で確実に分岐出力電圧の
負荷効果を改善し得、以つてコストダウンに寄与し得る
極めて良好なしベル調整回路を提供することを目的とし
ている。
However, such measures require complicated circuits that increase costs, and are not desirable. Therefore, the present invention has been made in view of the above points, and provides an extremely good zero-bell adjustment circuit that can reliably improve the load effect of branch output voltage with a simple circuit configuration and contribute to cost reduction. is intended to provide.

すなわち、この発明のレベル調整回路は従来の回路に対
し可変抵抗器の摺動子および最大側(入力側)端子間に
、該可変抵抗器以降に接続される回路の入力抵抗と略等
しい値の唯一本の抵抗器を接続するだけで、分岐出力電
圧および主線路の入力インピーダンスが可変抵抗器の摺
動子の位置につて変動するのを効果的に抑制し得るよう
にした点に特徴を有しているものである。以下図面を参
照してこの発明の一実施例につき詳細に説明する。
That is, the level adjustment circuit of the present invention has a value approximately equal to the input resistance of the circuit connected after the variable resistor between the slider of the variable resistor and the maximum side (input side) terminal, compared to the conventional circuit. The feature is that by connecting only one resistor, it is possible to effectively suppress variations in the branch output voltage and main line input impedance due to the position of the slider of the variable resistor. This is what we are doing. An embodiment of the present invention will be described in detail below with reference to the drawings.

すなわち第2図に示すようにRgなる信号源抵抗を有す
る信号源e,Nは一端が接地されると共に、池端が主線
路Lの入力端川に接続される。
That is, as shown in FIG. 2, one end of the signal sources e and N having a signal source resistance of Rg is grounded, and the end thereof is connected to the input end of the main line L.

そして、この入力端INの後で主線路Lは分岐されて録
音端子RECに接続されると共に、可変抵抗器VR,の
最大側MAX端子1に接続される。また、この可変抵抗
器VR,の最小側MIN端子3は接地され且つ摺動子2
がRcなる入力抵抗を有する次段回路NCに接続される
。ここで、可変抵抗器VR,の摺動子2および最大側M
AX端子1間には、該可変抵抗器VR,以降に接続され
る次段回路NCの入力抵抗Rcに略等しい値を有する抵
抗Rが接続される。なお、次段回路NCは一般に周波数
があまり高くない範囲では、その入力インピーダンスが
略々Rcなる抵抗成分で代表される。而して以上の構成
において、主線路Lから分岐されて録音端子RECから
導出される分岐出力電圧eREcはとなる。
After this input terminal IN, the main line L is branched off and connected to the recording terminal REC, and is also connected to the maximum side MAX terminal 1 of the variable resistor VR. Further, the minimum side MIN terminal 3 of this variable resistor VR is grounded and the slider 2
is connected to the next stage circuit NC having an input resistance Rc. Here, the slider 2 of the variable resistor VR and the maximum side M
Connected between the AX terminals 1 is a resistor R having a value substantially equal to the input resistance Rc of the next-stage circuit NC connected after the variable resistor VR. Note that the next stage circuit NC is generally represented by a resistance component whose input impedance is approximately Rc in a range where the frequency is not very high. In the above configuration, the branch output voltage eREc branched from the main line L and derived from the recording terminal REC is as follows.

但し、これは可変抵抗器VR,の摺動子2が任意の位置
にあるときであり、式中のR,Nは入力端子mから矢印
方向を見たときの主線路の入力抵抗であり、且つR,2
,R23はそれぞれ可変抵抗器VR,の摺動子2と最大
側MAX端子1間および摺動子と最小側MIN端子3間
の抵抗である。そして、かかる■式中でR=Rcである
からとなる。また、分岐出力電圧eREcは可変抵抗器
VR,の沼動子2を最大側MAX端子1および最小側M
瓜端子3とした場合にはとなり、棚式={91式の関係
にある。
However, this is when the slider 2 of the variable resistor VR is at an arbitrary position, and R and N in the formula are the input resistances of the main line when looking in the direction of the arrow from the input terminal m, and R,2
, R23 are resistances between the slider 2 and the maximum side MAX terminal 1 and between the slider and the minimum side MIN terminal 3 of the variable resistor VR, respectively. This is because R=Rc in the equation (2). In addition, the branch output voltage eREc is determined by connecting the variable resistor VR to the maximum side MAX terminal 1 and the minimum side M
When the melon terminal 3 is used, the relationship is as follows: shelf type = {91 formula.

但し、ここでRvは可変抵抗器VR,の抵抗であって、
【81式の場合‘7}式においてR,2=0,R23=
Rvとして且つ{9}式の場合の式においてR,2=R
v,R23=0として与えられる。ところで、このよう
にして与えられる分岐出力電圧eREcの負荷効果なら
びに入力抵抗R,Nの変化をみるために、前述したと同
様な条件すなわちRg=20kQ,Rv=100kQ(
但し直線的特性)、Rc=50kQとしてR…=(R。
However, here Rv is the resistance of the variable resistor VR,
[For formula 81, '7} In formula R, 2 = 0, R23 =
As Rv and in the equation {9}, R,2=R
v, R23=0. By the way, in order to see the load effect of the branch output voltage eREc given in this way and the changes in the input resistances R and N, the same conditions as described above, namely Rg = 20kQ, Rv = 100kQ (
However, when Rc=50kQ, R...=(R.

〆R,2)十(RC〆R23) ・・・・・・(11)
を可変抵抗器VR,の摺動子1のとる回転角度の数点で
求めると、第3図a,bにそれぞれ実線で示したように
なる。すなわち、可変抵抗器VR,でレベル調整するこ
とによって分岐出力電圧eREcの対入力電圧e…比は
約1.がBの負荷効果つまり変動を受けることになるが
、これは従来の変動に比して略半減し得る値であって、
実用上支障のない迄に可及的に抑制し得ることがわかる
〆R, 2) 10 (RC〆R23) ・・・・・・(11)
When calculated from several rotation angles taken by the slider 1 of the variable resistor VR, the results are as shown by the solid lines in FIGS. 3a and 3b, respectively. That is, by adjusting the level with the variable resistor VR, the ratio of the branch output voltage eREc to the input voltage e... is approximately 1. will be subject to the load effect of B, that is, fluctuation, but this is a value that can be reduced by approximately half compared to the conventional fluctuation,
It can be seen that this can be suppressed as much as possible without causing any practical problems.

また、入力抵抗RINの変動も33り50kQ間の約1
7kQに変化するに過ぎず、これは従来の変化に対して
略1′4と大幅に低減し得ることがわかる。そして、こ
のように入力抵抗R,Nの変動を可及的に抑制し得るの
で、信号源の浮遊容量等により、可変抵抗器VR,の位
置に応じて信号に与える周波数特性すなわちこの実施例
の場合は音質に与える悪影響を効果的に軽減することが
できる。
In addition, the input resistance RIN fluctuates by approximately 1 between 33 and 50kQ.
It can be seen that the change is only 7 kQ, and this can be significantly reduced to about 1'4 compared to the conventional change. Since the fluctuations in the input resistances R and N can be suppressed as much as possible in this way, the frequency characteristics given to the signal depending on the position of the variable resistor VR, due to the stray capacitance of the signal source, that is, the frequency characteristics of this embodiment. In this case, the negative impact on sound quality can be effectively reduced.

なお、この発明は上記した実施例のみに限定されること
なく、この発明の要旨を逸脱しない範囲で種々の変形を
実施し得るのは勿論である。従って以上のようなレベル
調整回路によれば、従来の回路に対し可変抵抗器の摺動
子および最大側(入力側)端子間に、該可変抵抗器じ兆
蜂に接続される回路の入力抵抗と略等しい値の唯一本の
抵抗器を接続するだけで、従来のようにコストアップに
つながる複雑な回路を必要とすることなく、分岐出力電
圧および主線路の入力インピーダンスが可変抵抗器の摺
動子の位置によって変動するのを効果的に抑制すること
ができる。以上詳述したようにこの発明によれば、簡単
な回路構成で確実に分岐出力電圧負荷効果を改善し得、
以つてコストダウンに寄与し得る極めて良好なしベル調
整回路を提供することが可能となる。
Note that the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention. Therefore, according to the level adjustment circuit as described above, unlike the conventional circuit, the input resistance of the circuit connected to the variable resistor is connected between the slider of the variable resistor and the maximum side (input side) terminal. By simply connecting only one resistor with a value approximately equal to that of the variable resistor, the branch output voltage and the input impedance of the main line can be adjusted by connecting a single resistor with a value approximately equal to that of the variable resistor. Fluctuations depending on the child's position can be effectively suppressed. As detailed above, according to the present invention, the branch output voltage load effect can be reliably improved with a simple circuit configuration.
This makes it possible to provide an extremely good bell adjustment circuit that can contribute to cost reduction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の録音端子付音量調節回路を示す結線図、
第2図はこの発明に係るレベル調整回路の一実施例とし
て録音端子付音量調節回路を示す結線図、第3図a,b
は従来との対比において示すこの発明による分岐出力電
圧および入力抵抗の変化特性曲線図である。 e,N・・・・・・信号源、Rg・・・・・・信号源抵
抗、IN・・・・・・入力端、REC・・・・・・録音
端子、VR.・・・・・・可変抵抗器、Rc・・・・・
・入力抵抗、NC・・・・・・次段回路。 第1図第2図 第3図
Figure 1 is a wiring diagram showing a conventional volume control circuit with a recording terminal.
Figure 2 is a wiring diagram showing a volume adjustment circuit with a recording terminal as an embodiment of the level adjustment circuit according to the present invention, and Figures 3a and b.
1 is a change characteristic curve diagram of branch output voltage and input resistance according to the present invention shown in comparison with the conventional one. e, N...signal source, Rg...signal source resistance, IN...input terminal, REC...recording terminal, VR.・・・・・・Variable resistor, Rc・・・・・・
・Input resistance, NC...Next stage circuit. Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1 信号線路を二分した一方の線路から他の回路に分岐
出力を導出すると共に他方の線路と基準電位点間に両端
を接続した可変抵抗器の摺動子から次段回路にレベル調
整出力を導出してなるレベル調整回路において、前記可
変抵抗器の一端および摺動子間に前記次段回路の入力抵
抗に略等しい値の抵抗を接続したことを特徴とするレベ
ル調整回路。
1. A signal line is divided into two, and a branch output is derived from one line to another circuit, and a level adjustment output is derived from the slider of a variable resistor whose both ends are connected between the other line and a reference potential point to the next stage circuit. 1. A level adjustment circuit comprising: a resistor having a value substantially equal to the input resistance of the next stage circuit is connected between one end of the variable resistor and the slider.
JP11753477A 1977-09-30 1977-09-30 Level adjustment circuit Expired JPS6034850B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11753477A JPS6034850B2 (en) 1977-09-30 1977-09-30 Level adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11753477A JPS6034850B2 (en) 1977-09-30 1977-09-30 Level adjustment circuit

Publications (2)

Publication Number Publication Date
JPS5451444A JPS5451444A (en) 1979-04-23
JPS6034850B2 true JPS6034850B2 (en) 1985-08-10

Family

ID=14714163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11753477A Expired JPS6034850B2 (en) 1977-09-30 1977-09-30 Level adjustment circuit

Country Status (1)

Country Link
JP (1) JPS6034850B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5871225U (en) * 1981-11-05 1983-05-14 八木アンテナ株式会社 Variable attenuator control circuit

Also Published As

Publication number Publication date
JPS5451444A (en) 1979-04-23

Similar Documents

Publication Publication Date Title
JP2830087B2 (en) Frequency characteristic correction circuit
JPS5873289A (en) Device for automatically and manually controlling high frequency peaking content of video signal
US4432097A (en) Tone control circuit
JPS6034850B2 (en) Level adjustment circuit
JPH0683111B2 (en) ▲ √f ▼ Automatic gain control amplifier
US5113144A (en) Feed-back type emphasis circuit
JPH04148388A (en) Differentiator for time constant variable
JP3151376B2 (en) Filter circuit
JPS6342594Y2 (en)
US5394113A (en) High impedance low-distortion linear amplifier
JPH0117854Y2 (en)
JPH0220170B2 (en)
JP3349550B2 (en) Filter circuit
JPS6133484B2 (en)
JPS5921546Y2 (en) variable filter circuit
JPS6319925Y2 (en)
JP2991727B2 (en) Active filter circuit
JPS6161286B2 (en)
JPH07183763A (en) Filter circuit
JPH0454714A (en) Power amplifier circuit
JP2531789B2 (en) White dark clip circuit
JPH06109780A (en) Comparator circuit
JPS6312615Y2 (en)
JPH08162902A (en) Waveform equalization device
JPS6161287B2 (en)