JPS6033469Y2 - Write control circuit for information storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a write control circuit for controlling the writing of information in an information storage device such as a magnetic disk drive, and particularly to a write control circuit having a write inhibit function.

In the conventional write control circuit, as shown in FIG. 1, either a manually controlled write inhibit circuit 11 or an automatically controlled write inhibit circuit 12 is selected by a jumper connection 13, and from this, a gate circuit 15 is connected through an invanitor 14. Connected.

In the manually controlled write inhibit circuit 11, for example, when the switch 16 is turned off, a high level is output from the terminal 17.
This is applied to jumper connection 13.

When this connection part 13 is connected to the manual control write inhibit circuit 11 side, the high level is inverted by the inverter 14 and applied to the gate 15, and the gate 15 is kept in a closed state.

A write command is given to the gate 15 from the terminal 18. Therefore, if a write command is given to the terminal 18 while the gate 15 is open, the write command is output from the gate 15 through the output terminal 19 as a valid write command. It can be output and written.

However, if the gate 15 is closed, even if a write command is given to the terminal 18, the write is prohibited.

In the automatic control write inhibit circuit 12, when a write inhibit command 26 is given as a positive pulse to the terminal 21, this sets the flip-flop 23 through the inverter 22, and the Q output of the flip-flop 23 becomes high level, that is, the automatic control is disabled. The output of the write inhibit circuit 12 becomes high level.

Therefore, if the jumper connection part 13 is connected to the automatic control write inhibit circuit 12 side, the automatic control write inhibit circuit 1
The high level of the output of No. 2 is inverted by the inverter 14 and applied to the gate 15, and the gate 15 is closed.

Therefore, after the write inhibit command 26 is given, even if a write command is given to the terminal 18, no writing is performed.

To release write protection in the automatic control write protection circuit 12, write write protection release command 2 of a negative pulse is sent to the terminal 24.
5 to flip-flop 23 to reset it.

The write inhibit command 26 and the write inhibit release command 25 are given, for example, from a higher-level device that controls the magnetic disk device.

In this way, a write prohibition command is issued manually or automatically to prevent writing to the conventional cartridge, for example, and even if a write command is issued by mistake, the terminal 1
9, a valid write control signal is prevented from being issued,
The information will be protected.

However, in this conventional write control circuit, the write inhibit command 26 may be incorrectly issued due to a failure, noise, etc. during the write operation.
When is input, the write operation is interrupted at that point.

In magnetic disk drives, writing and reading are generally performed in sector units, but most of the time when the write operation is interrupted is in the middle of a sector, so the data in that sector is not correct data.

Therefore, if the written data is read later, the data written at the time of the interruption will become incorrect information.

Also, even if a write command arrives in a state where a write inhibit command is entered, writing is prohibited, but if the write inhibit command is canceled by mistake while the write command is given, writing will start at the same time. The start is often in the middle of a sector, and there is a risk that data will be written from the middle and the data will not be stored correctly.

The purpose of this invention is to not immediately inhibit writing even if a write inhibit command is issued during writing, but to inhibit writing after the write operation is completed, and to prevent the write inhibit command from being issued while writing is inhibited and a write command is given. Even if a cancellation command is issued, the write protection will not be canceled and the written data will not be written from the middle, ensuring data protection and preventing the risk of writing incorrect data. The objective is to provide a write control circuit that does not require a write control circuit.

According to this invention, a write command and a write inhibit command are supplied to a priority circuit, the earlier command is given priority, and the gate circuit is controlled by the output of this priority circuit, and only the write command that has passed through this gate circuit is valid. This is a write command.

For example, in FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals, and in this invention a priority circuit 31 is provided.

For example, the output side of the jumper connection 13 is the Nant gate 32.
and one input side of the OR gate 33.

Further, the terminal 18 to which a write command is applied is connected to the other input side of the OR gate 33 and is also connected to the other input side of the Nandt gate 32 through an inverter 34.

The output side of the output of the Nant gate 32 is the flip-flop 3.
The output side of the OR gate 33 is connected to the reset input side of the flip-flop 35.

The Q output of the flip-flop 35 is supplied to the gate 15 as the output of the priority circuit 31.

In such a configuration, for example, a write command is given to the terminal 18 as shown in FIG. Suppose that a write inhibit command as shown in is given.

In other words, at time 1Jt1, the write inhibit command is issued to the priority circuit 3.
1, the output of that Nant gate 32 is the third
It falls to a low level as shown in FIG. 3C, so flip-flop 35 is set and its Q output falls as shown in FIG. 3E.

Gate 15 is therefore closed. As shown in the third diagram, the output of the OR gate 33 rises at the time due to the write inhibit command.

Even if a write command is generated at the terminal 18 after the time t2 at time t2 as shown in FIG.
5 cannot be passed and writing is prohibited.

From time t2, the output of the Nandt gate 32 rises as shown in FIG. 3C.

When the write command is in progress, the write command is canceled at s3 as shown in FIG. 3B, and even if this falls, the write prohibition command is input to the priority circuit 31 earlier than the write command, so the write prohibition takes priority. Therefore, the flip-flop 35 is not reset and no writing is performed.

When the write command disappears at time s4 and becomes a low level, the output of the OR gate 33 becomes a low level as shown in Figure 3, the flip-flop 35 is reset, and the gate 15 is opened as shown in Figure 3E.

When a write command is input to the clock as shown in FIG. 3A in a state where no write inhibit command has been generated, the output of the flip-flop 35 remains at a high level, so the gate 15 is open. The write command passes through the gate 15 as shown in FIG. 3F, and writing is performed.

As shown at time t6 in FIG. 3A, a write command is generated in a state where no write inhibit command is issued, and even if this command passes through the gate 15, while writing is being performed, time t6 in FIG.
When the write inhibit command is input as shown in FIG. is not inhibited and a write command appears at terminal 19.

Subsequently, at time t8, the write command is released, a write inhibit command is generated at that time, the output of the re-and gate 32 becomes a low level as shown in FIG. 3C, and the Q output of the flip-flop 35 becomes a low level, causing the gate 15 closes.

If the write prohibition command is canceled at the specified time, the OR gate 33
The output becomes low level, the flip-flop 35 is reset, and the gate 15 is opened.

As described above, in the write control circuit according to this invention, whichever of the write command and the write inhibit command is entered first in the priority circuit 31 is given priority.For example, at time t2 in FIG. 3, the write inhibit command is given first. In the case where the write prohibition command is entered, priority is given to write prohibition, and even if a write command is entered after that and the write prohibition command is canceled at time t3, no write is performed.

Therefore, there is no risk that data will be written from the middle, and there is no risk that erroneous data will be written.

Conversely, if the write command is earlier than the write inhibit command, the priority circuit 31 gives priority to the write state.

Therefore, even if a write prohibition command is input in this state, write prohibition is not performed, and write prohibition occurs only after the write command is completed.

Therefore, even if a write prohibition command is generated during writing, the data will not be prohibited midway, and there is no possibility that write prohibition will be performed after the data has been completely written and the data will be erroneously recorded.

Moreover, writing can be controlled by a write prohibition command.

It should be noted that such a priority circuit is not limited to the example shown in the figure, and various types that operate in the same manner can be used.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional write control circuit, Figure 2 is a block diagram showing a conventional write control circuit.
The figure is a block diagram showing an example of a write control circuit according to this invention, and FIG. 3 is a time chart showing an example of the operation of the circuit shown in FIG. 2. 11... Manual control write inhibit circuit, 12...
...Automatic control write-protection circuit, 13...
jumper connection, 15... write control gate;
18...Write command input terminal, 19...
- Valid write output terminal, 31...Priority circuit.

Claims (1)

[Scope of utility model registration request] A priority circuit that gives priority to whichever of the write inhibit command or the write command arrives first, outputs a gate close signal when the write inhibit command has priority, and outputs a gate open signal when the write command has priority; A write control circuit for an information storage device, comprising a gate which is controlled to open and close by an output of the circuit, into which the write command is input, and which outputs the output write command as a valid output.