JPS6032831B2 - electronic clock - Google Patents

electronic clock

Info

Publication number
JPS6032831B2
JPS6032831B2 JP1689878A JP1689878A JPS6032831B2 JP S6032831 B2 JPS6032831 B2 JP S6032831B2 JP 1689878 A JP1689878 A JP 1689878A JP 1689878 A JP1689878 A JP 1689878A JP S6032831 B2 JPS6032831 B2 JP S6032831B2
Authority
JP
Japan
Prior art keywords
voltage
section
channel mos
mos transistor
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1689878A
Other languages
Japanese (ja)
Other versions
JPS54109875A (en
Inventor
靖彦 西久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP1689878A priority Critical patent/JPS6032831B2/en
Publication of JPS54109875A publication Critical patent/JPS54109875A/en
Publication of JPS6032831B2 publication Critical patent/JPS6032831B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G19/00Electric power supply circuits specially adapted for use in electronic time-pieces
    • G04G19/02Conversion or regulation of current or voltage
    • G04G19/06Regulation

Description

【発明の詳細な説明】 本発明は、発振部、分岡部、表示駆動装置及び表示装置
を有し、且つ供尊高△電源系が電源電圧(例えば電池電
圧)と電圧変換部によって電源電圧を低下させた低電圧
部との2電源系からなる、コンブリメンタリーMOSト
ランジスタ(以下CMOSTと略す)を用いた水晶発振
式電子時計に関するもので、電圧変換部を基準電圧部と
基準電圧を入力して、低電圧部である負荷に一定な低蝿
圧を供9篇させるための電流増幅部より構成することに
よって、安定に低電圧を得て、動作上必要な最低電圧で
回路を動作させ、電子時計の消費電力を減少せしめんと
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention has an oscillating section, a dividing section, a display driving device, and a display device, and a power supply system that converts the power supply voltage by a power supply voltage (for example, battery voltage) and a voltage conversion section. This relates to a crystal oscillation type electronic watch that uses a combinary MOS transistor (hereinafter abbreviated as CMOST), which consists of a two-power supply system with a reduced low voltage section, and a voltage converter section that inputs a reference voltage section and a reference voltage. By constructing a current amplification section to supply a constant low voltage to the load, which is a low voltage section, a stable low voltage can be obtained, and the circuit can be operated at the minimum voltage necessary for operation. The aim is to reduce the power consumption of electronic watches.

本発明に用いている電子時計のブロックダイアグラムを
第1図に、電圧変換部の説明を第2図に、鰭圧変換部の
一実施例の回路図を第3図に示した。
A block diagram of the electronic timepiece used in the present invention is shown in FIG. 1, an explanation of the voltage converter is shown in FIG. 2, and a circuit diagram of one embodiment of the fin pressure converter is shown in FIG.

第1図において、発振部1、分間部2、表示駆動装置3
、表示装置4、電圧変換部5、電源7であり、電源7の
■電圧端子をVoD、e電圧端子をVssとし、電源電
圧は、電圧変換部5を介して、低電圧VssLを得て、
破線内の電子回路8には、Vooを共通として、Vss
及びVssLの2電源が供給されている。CMOSTに
よる電子回路は、一般的に電池電圧で動作させる場合、
IV程度以上で完全な動作を保証している。したがって
、エネルギーの必要な表示駆動装置3などを除いて、他
の電子回路には、必要最低限の電圧が印加されれば良い
わけで、本発明は、電圧変換部4を介して、1.6V程
度の電池から効率良く、IV程度の安定な低電圧を供給
し、消費電力の減少を実現している。ちなみにCMOS
Tの消費電力Pは次式‘1}で示されるのでP=C。
In FIG. 1, an oscillating section 1, a minute section 2, a display driving device 3,
, a display device 4, a voltage converter 5, and a power supply 7, the voltage terminal (2) of the power supply 7 is set to VoD, the e voltage terminal is set to Vss, and the power supply voltage is obtained by obtaining a low voltage VssL via the voltage converter 5,
The electronic circuit 8 within the broken line has Voo in common and Vss
Two power supplies, VssL and VssL, are supplied. Generally, when an electronic circuit using CMOST is operated on battery voltage,
Perfect operation is guaranteed at IV level or higher. Therefore, except for the display driving device 3 which requires energy, it is sufficient to apply the minimum necessary voltage to other electronic circuits, and the present invention provides 1. It efficiently supplies a stable low voltage of about IV from a battery of about 6V, reducing power consumption. By the way, CMOS
Since the power consumption P of T is shown by the following formula '1}, P=C.

VSS2 ナ ……(11Co:寄生
容量Vss:電源電圧 「:動作周波数 IV動作させると、1.飢動作の40%のエネルギーで
済むことなる。
VSS2 na...(11Co: Parasitic capacitance Vss: Power supply voltage ": Operating frequency IV When operated, 1. 40% of the energy of starvation operation is required.

以下、電圧変換部5について、図面に従って詳細に説明
する。第2図において、破線内が電圧変換部5であり、
それは基準電圧部51と基準電圧Vsを入力として、負
荷に一定な低電圧VssLを供V給する電流増幅部52
より構成され、VssLとVDo間に負荷である但電圧
部6が接続され、VssLとV。。間に負荷である但電
圧部6が接続されている。具体的な一実施例である第3
図において、基準電圧部51は2個のPMOST5 1
1,5 1 3と2個のNMOSTによる抵抗512
,514とよりなる。第3図において抵抗として、NM
OSTを用いているが、P型不純物の薄い領域、即ちP
ウェルと同時に拡散してできる、拡散抵抗を用いても可
能である。第1図のPMOST51 1のリースSはV
ooに、ゲートG及びドレィンDは共通接続され、.中
間基準爵位V3oの端子となり、Vsoは第1の抵抗5
12を介してVssに接続され、さらにVsoを第2の
PMOST513のリースSに接続し、第2のPMOS
TのゲートG及びドレインDは共通接続されて基準電圧
Vs端子とし、第2の抵抗514を介してVssに接続
されている。まず中間基準電位Vsoは、抵抗NMOS
T51211抵抗NMOST51 4の条件で次式のよ
うに求めることができる。ID8=年(vS。
Hereinafter, the voltage converter 5 will be explained in detail according to the drawings. In FIG. 2, the area inside the broken line is the voltage converter 5,
It has a reference voltage section 51 and a current amplification section 52 which receives a reference voltage Vs as input and supplies a constant low voltage VssL to the load.
However, a voltage section 6, which is a load, is connected between VssL and VDo, and VssL and VDo. . However, a voltage section 6, which is a load, is connected between them. The third example is a specific example.
In the figure, the reference voltage section 51 includes two PMOSTs 5 1
1,5 1 3 and 2 NMOST resistors 512
, 514. In Figure 3, as resistance, NM
Although OST is used, a thin region of P-type impurity, that is, P
It is also possible to use a diffused resistor that can be diffused simultaneously with the well. Lease S of PMOST511 in Fig. 1 is V
oo, the gate G and drain D are commonly connected, . It becomes the terminal of intermediate standard rank V3o, and Vso is the first resistor 5.
12 to Vss, and further connects Vso to the lease S of the second PMOST 513, and
The gate G and drain D of T are commonly connected to serve as a reference voltage Vs terminal, and are connected to Vss via a second resistor 514. First, the intermediate reference potential Vso is the resistor NMOS
It can be calculated as shown in the following equation under the condition of T51211 resistance NMOST514. ID8=Year (vS.

‐vP5・・)2 ・肌‘2)10S=学(vSS‐
VN58)2 ..・..・【3’los:Voo〜
Vss間電流85,.:PMOSL,.の増幅率 8512:NMOST512の増幅率 VP5,,:PMOST511のしきい電圧VN5,2
:NMOST512のしきい電圧‘2’‘3’式よりV
soを求めるとB511》85・2ならば VsoニVP5,. ……
■となり、中間基準電圧Vsoは、PチャンネルMOS
T51 1のしきい電圧VP5,.となる。
-vP5...)2 ・Hada'2)10S=Study (vSS-
VN58)2. ..・.. ..・[3'los:Voo~
Current between Vss 85, . :PMOSL,. Amplification factor 8512: Amplification factor VP5 of NMOST512, : Threshold voltage VN5,2 of PMOST511
: Threshold voltage of NMOST512 V from formula '2' and '3'
So, if B511》85.2, then Vso NiVP5, . ……
■The intermediate reference voltage Vso is P-channel MOS
T51 1 threshold voltage VP5, . becomes.

全く同様にして、基準鰭圧Vsを求めると、Vsは次式
で示されるVs三VP5,.十VP5,3
“”“‘51VP5.3:PMOST513
のしきし、電圧したがって基準電圧Vsは2個のPMO
STのしきし、電圧の和となり、電源電圧がVP5,.
十VP5,3に低下するまで、Vsは三VP5,.十V
P5・3となる。例えばVP5,.=VP5,3=−0
.55Vとすれば、VsはVs=−1.6〜一1.1V
の範囲で、ほぼ一1.1Vとなる。またこのとき抵抗5
12,513の値を10〜10mWこすれば、その時の
損失電力は非常にわずかですむ。次に電流増幅部52に
ついて説明する。
When the reference fin pressure Vs is found in exactly the same way, Vs is expressed by the following equation: Vs3VP5, . 10 VP5,3
"""'51VP5.3: PMOST513
Therefore, the reference voltage Vs is equal to the voltage of the two PMOs.
The threshold of ST becomes the sum of the voltages, and the power supply voltage becomes VP5, .
Vs decreases to 3 VP5, . . . until it drops to 10 VP5,3. 10V
It becomes P5.3. For example, VP5, . =VP5,3=-0
.. If it is 55V, Vs = -1.6 to -1.1V
In the range of , it is approximately -1.1V. Also at this time, resistance 5
If the value of 12,513 is applied by 10 to 10 mW, the power loss will be very small. Next, the current amplifying section 52 will be explained.

電流増幅部52のPチャネルMOST52 1のゲート
Gの入力電圧は、基準電圧Vsである。・負荷でる低電
圧部6に比較して、PMOST521のインピーダンス
を十分小さく設計しておけば、電流増幅部52はリース
フオロアー型であるのでリースSとVoo間の電圧Vs
sLは次式で示されるVSSLニV3一VP概・
”””‘6)V脚,:PMOST521
のしきい鰭圧したがって‘51‘61式より、低電圧部
6へ供v給される亀圧VssLはVssL=VP5,.
十VP5,3−VP52, ”””‘61とな
る。
The input voltage of the gate G of the P-channel MOST 52 1 of the current amplifying section 52 is the reference voltage Vs. - If the impedance of the PMOST 521 is designed to be sufficiently small compared to the low voltage section 6 that is a load, the voltage Vs between the lease S and Voo will be reduced because the current amplifying section 52 is a lease follower type.
sL is expressed by the following formula:
``'''''6) V legs, :PMOST521
Accordingly, from formula '51' and '61, the tortoise pressure VssL supplied to the low voltage section 6 is VssL=VP5, .
10 VP5, 3-VP52, ``'''''61.

例えばVP斑,=一0.1Vとすれば、VssLは亀源
電圧Vss=一1.6V〜−1.1Vの範囲で、ほぼ一
0.1Vに安定化される。部分的なMOSTのしきい電
圧の変化は、イオン注入菱直によりチャネルドープをし
ても良いし、チャネル長およびチヤネル幅を変えても良
い。本実施例の場合、電流増幅部52のPMOST52
1のしきし、電圧VP52,は、チャネル長を小さくす
ることによって、しさし・電圧を小さくする方法が最も
簡単である。基準電圧部の基準電圧は、本発明の実施例
では2個のPMOSTのしきい電圧の和となっているが
、同様に複数個のPMOSTのしきし、電圧の和もとり
えることは、いうまでもない。上記説明したように本発
明の電圧変換部を用いればわずかの電力損失で、電源電
圧を安定に低電圧に変換でき、電子時計の消費電力の軽
減に非常な効果をもたらし、特にMHZオーダーの高周
波システムは有効な手段である。
For example, if VP unevenness = -0.1V, VssL is stabilized at approximately -10.1V in the range of source voltage Vss = -1.6V to -1.1V. To partially change the threshold voltage of the MOST, channel doping may be performed by ion implantation or channel length and channel width may be changed. In the case of this embodiment, the PMOST 52 of the current amplification section 52
The easiest way to reduce the threshold voltage VP52 of 1 is to reduce the threshold voltage by reducing the channel length. In the embodiment of the present invention, the reference voltage of the reference voltage section is the sum of the threshold voltages of two PMOSTs, but it goes without saying that it can also be the sum of the threshold voltages of a plurality of PMOSTs. Nor. As explained above, if the voltage converter of the present invention is used, the power supply voltage can be stably converted to a low voltage with little power loss, which is extremely effective in reducing the power consumption of electronic watches, especially for high frequencies on the MHZ order. The system is an effective tool.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に用いる2電源系からなる水晶発振式電
子時計のブロックダイアグラム、第2図は電圧変換部の
説明図、第3図は本発明の電圧変換部の具体的な一実施
例を示す回路図。 1・・・・・・発振部、2・・・・・・分周部、3・・
・・・・表示駆動装置、4・・・・・・表示装置、5・
・・・・・電圧変換部、6・・・・・・低電圧部、7・
・・・・・電源(例えば電池)、51・・・・・・基準
電圧部、52・・・・・・電流増幅部、51 1・・・
・・・PMOST、512・…・・抵抗(NMOST)
、521・・・・・・PMOST、51 3・・・・・
・PMOST、5 1 4・・・・・・抵抗(NMOS
T)第1図 第2図 第3図
Fig. 1 is a block diagram of a crystal oscillation electronic timepiece consisting of two power supply systems used in the present invention, Fig. 2 is an explanatory diagram of the voltage converter, and Fig. 3 is a specific example of the voltage converter of the present invention. A circuit diagram showing. 1... Oscillation section, 2... Frequency division section, 3...
...Display drive device, 4...Display device, 5.
... Voltage conversion section, 6 ... Low voltage section, 7.
...Power source (for example, battery), 51...Reference voltage section, 52...Current amplification section, 51 1...
...PMOST, 512...Resistance (NMOST)
, 521...PMOST, 51 3...
・PMOST, 5 1 4... Resistor (NMOS
T) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 1 発振部、分周部、表示駆動装置及び表示装置を有し
、且つ供給電源系が電源電圧系と電圧変換部によつて電
源電圧を低下させた低電圧系との2電源系からなる、コ
ンプリメンタリ−MOSトランジスタを用いた水晶発振
式電子時計において、電圧変換部が基準電圧部と基準電
圧を入力して、低電圧部である負荷に一定な低電圧を供
給させるための電流増幅部とからなり、基準電圧部は基
準電圧としてPチヤネルMOSトランジスタのしきい電
圧の和を用い、且つ電流増幅部は基準電圧を入力として
PチヤネルMOSトランジスタのリースフオロアー型出
力回路を用いて、負荷に定電圧を供給することを特徴と
する電子時計。 2 基準電圧部は第1、第1のPチヤネルMOSトラン
ジスタと第1、第2の抵抗とからなり、第1のPチヤネ
ルMOSトランジスタのリースは■電圧端子に、ゲート
及びドレインは共通接続されて、拡散あるいはMOSト
ランジスタによる第1の抵抗を介して■電圧端子に接続
され、さらに第1のPチヤネルMOSトランジスタのド
レインを第2のPチヤネルMOSトランジスタのリース
に接続し、第2のPチヤネルMOSトランジスタのゲー
ト及びドレインは共通接続されて、拡散あるいはMOS
トランジスタによる第2の抵抗を介して■電圧端子に接
続することによつて■電圧端子と第2のPチヤネルMO
Sトランジスタのドレイン間の基準電圧が一定電圧以上
で第1及び第2PチヤネルMOSトランジスタのしきい
電圧の和になるよう構成したことを特徴する特許請求の
範囲第1項記載の電子時計。 3 電流増幅部はPチヤネルMOSトランジスタのゲー
ト・■電圧端子間に基準電圧を入力し、ドレインは■電
圧端子に接続し、リースは負荷である低電圧を介して■
電圧端子に接続して、負荷には基準電圧より電流増幅部
のPチヤネルMOSトランジスタのしきい電圧だけ低下
した電圧が加わるように構成し、且つ該PチヤネルMO
Sトランジスタのオン抵抗が低電圧部の負荷インピーダ
ンスの1/10以下であり、さらにしきい電圧が他の論
理部のしきい電圧に比較して小さくしたことを特徴とす
る特許請求の範囲第1項記載の電子時計。
[Scope of Claims] 1. A power supply system that includes an oscillation section, a frequency division section, a display driving device, and a display device, and that the supply power system is a power supply voltage system and a low voltage system in which the power supply voltage is lowered by a voltage conversion section. In a crystal oscillation electronic watch that uses complementary MOS transistors and has two power supply systems, the voltage conversion section inputs the reference voltage section and the reference voltage to supply a constant low voltage to the load, which is the low voltage section. The reference voltage section uses the sum of the threshold voltages of the P-channel MOS transistors as a reference voltage, and the current amplification section uses the reference voltage as an input to generate a lease-follower type output circuit of the P-channel MOS transistors. An electronic clock characterized in that it supplies a constant voltage to a load using an electronic clock. 2. The reference voltage section consists of first and second P-channel MOS transistors and first and second resistors, and the lease of the first P-channel MOS transistor is connected to the voltage terminal, and the gate and drain are commonly connected. , is connected to the voltage terminal via a first resistor formed by diffusion or a MOS transistor, further connects the drain of the first P-channel MOS transistor to the lease of the second P-channel MOS transistor, and connects the drain of the first P-channel MOS transistor to the lease of the second P-channel MOS transistor. The gates and drains of the transistors are connected in common to form a diffusion or MOS transistor.
By connecting to the voltage terminal through a second resistor by a transistor, the voltage terminal and the second P-channel MO
2. The electronic timepiece according to claim 1, wherein the reference voltage between the drains of the S transistors is the sum of the threshold voltages of the first and second P channel MOS transistors when the reference voltage is equal to or higher than a certain voltage. 3 The current amplification section inputs a reference voltage between the gate and ■voltage terminal of the P channel MOS transistor, the drain is connected to the ■voltage terminal, and the lease is connected to ■through the low voltage that is the load.
The voltage terminal is connected to the voltage terminal so that a voltage lower than the reference voltage by the threshold voltage of the P-channel MOS transistor of the current amplifying section is applied to the load, and the P-channel MOS transistor is connected to the voltage terminal.
Claim 1, characterized in that the on-resistance of the S transistor is 1/10 or less of the load impedance of the low voltage section, and the threshold voltage is lower than the threshold voltages of other logic sections. Electronic clock as described in section.
JP1689878A 1978-02-16 1978-02-16 electronic clock Expired JPS6032831B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1689878A JPS6032831B2 (en) 1978-02-16 1978-02-16 electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1689878A JPS6032831B2 (en) 1978-02-16 1978-02-16 electronic clock

Publications (2)

Publication Number Publication Date
JPS54109875A JPS54109875A (en) 1979-08-28
JPS6032831B2 true JPS6032831B2 (en) 1985-07-30

Family

ID=11928956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1689878A Expired JPS6032831B2 (en) 1978-02-16 1978-02-16 electronic clock

Country Status (1)

Country Link
JP (1) JPS6032831B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586606A (en) * 1981-07-03 1983-01-14 Seiko Instr & Electronics Ltd Generating circuit for low electric power reference pulse

Also Published As

Publication number Publication date
JPS54109875A (en) 1979-08-28

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