JPS603225A - Switching circuit - Google Patents

Abstract

PURPOSE:To prevent an unnecessary transient current from being flowed to the 2nd transistor (TR) having a stray capacitance by connecting a resistor and a capacitor in parallel between a base of the 1st TR and an input terminal of a pulse signal and increasing the time constant of a base circuit so as to delay the response speed of an output pulse. CONSTITUTION:The 1st TR1 controlling the pulse signal, the 2nd TR6 controlling a load current, a control signal 9 controlling the TR6, input terminals P1, P2, a load output terminal 3 and a load L are provided, the resistor R1 and the capacitor C are connected in parallel between the input terminal P1 and the TR1 and a resistor R4 is connected between the input terminal P1 and an emitter 4 of the TR1. In this constitution, when a pulse is given to the input terminal P1 and a prescribed time has elapsed, a current flowing to the resistor R1 becomes a prescribed value and the potential of a base 3 of the TR1 becomes constant. Then a turn-on time T2 is decided by the time constant comprising the resistors R1, R4 and the capacitor C so as to delay the response speed of a collector output pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching circuit for driving a thruster pulp in a gas jet system of an artificial satellite. :y y ty t is connected, and the response speed of the output pulse generated when the first transistor is turned on is delayed by a gate circuit activated by the turning-on operation of the first transistor. It provides a circuit.

A conventional circuit of this type is shown in FIG. In Figure 1, 11+ is the first transistor that controls the pulse signal, (2j is the power supply, Lf is the load, and R1 is the t potential difference between the base (3) and emitter (4) of the first transistor il+. The resistor (5) is the resistor that gives the first transistor (1
), (6) is a second transistor that controls the load current, (9) is a control signal that controls the second transistor (6), Pl and P2 are input terminals to which pulse signals are input, B2 is grounded. B3 is a load output terminal. Fig. 2 shows an equivalent circuit of the second transistor (6) shown in Fig. 1, (9) is the same as that shown in Fig. 1, (7) is the collector of the second transistor (6), Emitter of transistor (6) of 181kji2, 8
is the equivalent switch of the second transistor (6).

k is the stray capacitance of the second transistor (6). Third
The figure is an operating waveform diagram of each circuit in Figure 1 when switch 8 in Figure 2 is closed, (AI) is the voltage waveform of the base (3), (Bl) is the base current waveform, (CI) is collector river, 6iC waveform, 11 is the pulse width of the pulse signal input by valving the input terminal P1, 'r2 is the turn-on time of the first transistor (dish), and T3 is the first transistor II). Indicates the delay time when turning off.

The operation will be described in detail below. In FIG.

The base 3) and emitter (
When there is no pulse during 4), the first transistor is in an off state. Now, when a negative pulse with a pulse width Tt shown in (A1) of Fig. 3 is applied to the base %3),
Current flows through the base (3) as shown in (B1) in Figure 3, and the current flows through the first transistor (1) as shown in (C1) in Figure 3.
A current flows through the collector (5) of. In this case, a sufficiently large negative pulse will cause the first transistor 100 to pass through the current waveform of the collector (5)! -! 1
311(7)(C1). (A1) in Figure 3
After a period of Norms width T1 shown in , the first transistor (
1) G1 returns to the original state and turns off, but since the current density in the base t31 region is high, the collector (5)
The current 752 continues to flow, and the pulse width widens by 1jJ3Ts during the delay, as shown in (C1) of FIG. Figure 4 shows the operating waveforms of the various circuits in Figure 1 when the switch S in Figure 2 is open, (A2) is the -pressure waveform of the base (3),
(B2) Current waveform of hepace (3), (C2) kX
The current waveform of collector 15+ is shown.

The operation will be described in detail below. Now at (A2) in Figure 4-
When the negative pulse with the indicated pulse width T1 is transferred to the base +31, the first transistor (1) in FIG. Current flows.

Originally, the second transistor (6) in FIG. 1 was turned off,
In other words, since switch 8 in FIG. 2 is open and 9 is open, even if the base voltage (A2) shown in FIG. 4 is supplied, the current shown in (B2)s (C2) should not flow. At the moment when a negative pulse is applied to the base (3) of the first transistor (1) in FIG. The emitter (8) of the second transistor (6)
), a current flows through the collector (5) of the first transistor tl+. This problem occurs because the load (Ll) in Figure 1 intermittently sends the propellant of the satellite's gas jet system to the thruster.In the case of a solenoid, unnecessary pulses are generated when the thruster is not operating normally. There was no drawback that it would have a serious impact on VC').

This invention was made in order to improve such conventional drawbacks, and a resistor and a capacitor are connected in parallel to the input terminal of the pulse signal and the base IWj of the first transistor,
A resistor is connected between the input terminal and the emitter of the first transistor, and when the first transistor is in the on state V, the response speed of the output pulse appearing at the load is delayed, thereby reducing the second transistor having stray capacitance. The purpose is to prevent unnecessary transient current from flowing.

An embodiment of the present invention is shown in FIG. 5 below.

The configuration of is explained. In FIG. 5, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted.

In Fig. 5, C is a capacitor, R1~RAf@1st~
This is the fourth resistance. The operation will be described in detail below.

In FIG. 5, the moment a pulse is applied to the input terminal P1 with respect to the input terminal P2, current begins to flow through the first resistor R1, but after a certain period of time, the amount of current flowing through the first resistor R1 increases to a constant value. The potential of the base of the first transistor +11 +31 becomes constant. The turn-on time depends on the first resistor R1゜2Jg41)a and the time constant of the capacitor C, and the larger the capacitance of the capacitor C is.

Turn-on time will be longer. FIG. 6 shows the relationship between the pressure distribution of the emitter (4) of the first transistor (1) and 6 hours when the capacitance t of the ecapacitor C is set to be sufficiently large. In FIG. 6, T2 is the first transistor (1
), the turn-on time of the first transistor +11
The saturation voltage of is approximately equal to the voltage of the pulse applied to input terminal P2.

As described above, the present invention solves the drawback of the conventional transistor and switching circuit that a collector output pulse appears immediately when the first transistor turns on. By connecting a resistor and a capacitor in parallel between the input terminals of the pulse signal, the number of pulses of the pace circuit can be increased, and the response speed of the collector output pulse of the first transistor can be delayed. Note that the present invention has the advantage that the load current can be controlled regardless of whether the second transistor is of the PNP type or the NPIJ type.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a conventional transistor switching circuit, Fig. 2 is a diagram showing an equivalent circuit of a second transistor, and Fig. 3 is a diagram showing an example of a switching circuit of a conventional transistor.
Operation waveform diagram of the valley circuit. FIG. 4 is an operating waveform diagram of what is shown in FIG. 1 when the switch 8tl in FIG. 2 is open, FIG. FIG. In the figure, 11i is the first transistor, (2) is the power supply, and (3
) is the pace, (4) is the emitter, (5) is the collector, (
6) is the second transistor, +701 is the collector of the second transistor, (8) is the emitter of the second transistor, (9) is m8188, T1 is the pulse [, T2 is the turn-on time. T3 is a delay time, and R1 to R4 are first to fourth resistors. k is stray capacitance, C is capacitor, and B is switch. Pl and P2 are input terminals, P5 is a load output terminal, and L is a load. In the drawings, the same or corresponding parts are designated by the same reference numerals. To the main agent Masuo Iwa Figure 1, ゛ Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] an input terminal into which a pulse signal is input; a first transistor that controls the pulse signal input through this input terminal; and an input terminal connected in parallel between the base of the first transistor and the input terminal. a first resistor and a capacitor, one end of which is connected to the base of the first transistor;
A second resistor whose other end is grounded, and the above 8r41
a third resistor whose one end is connected to the collector of the transistor and whose other end is grounded; and a third resistor whose one end is connected to the emitter of the first transistor and whose other end is connected to the input terminal. a second transistor that controls the output current output from the emitter of the first transistor, and a load provided between the emitter of the first transistor and the collector of the second transistor. and a power supply whose positive terminal is connected to the emitter of the second transistor and whose negative terminal is grounded.