JPS6031300B2 - Channel selection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In the present invention, the tuning voltage to be applied to a tuner using a variable capacitance diode as a tuning element is set in advance by a plurality of variable resistors, and the variable resistors are switched to operate. By doing so, the present invention provides a channel selection and switching device that has a new function that has not been seen in the past regarding a channel selection device that is configured to perform channel switching.

Recently, many tuners have been used in which a reversible capacitance diode is used as a tuning element, and channel switching is performed by switching the tuning voltage applied to the diode.

Figure 1 shows the main parts of such a tuner, where 1 is the VMo tuner, 2 is the U old F tuner, and VH tuner.
The F tuner includes a variable capacitance diode 3 and coils 4 and 5 as tuning elements, and a switching diode 6 for band switching between a VHF high band and a VHF low band. 7 is a terminal to which a power supply BV for operating the VHF tuner 1 is applied; 8 is a terminal to which a tuning voltage BT for channel switching is applied; 9 is a terminal to which a band switching voltage BS is applied; It is an output terminal.

Further, the UHF tuner 2 includes a variable capacitance diode 11 and a resonant line 12 as a tuning element.

13 is a terminal to which the power supply BU for operating the UHF tuner 2 is applied, and 14 is a channel selection voltage B common to the VHF tuner 1.
The terminal to which T is applied, 16, is the m output terminal.

In addition, only a part of the tuning circuit is shown in the figure, and all other circuit parts are omitted.

Next, an example of the basic configuration of a device for performing channel selection and band switching by applying a channel selection voltage to such a tuner will be described with reference to FIG.

Here, 16 is a tuning voltage setting circuit that presets the tuning voltage BT added to the variable capacitance diode of the tuner, and is provided with a plurality of variable resistors 17a to 17, each of which has a tuning voltage BT. The desired channel selection voltage BT is set so as to be obtained, and the one selected from among them is taken out to the terminal 19 via the diodes 18a to 18, and the impedance is converted by a transistor or the like (not shown). is added to each variable capacitance diode 3, 11 of the VHF tuner and UHF tuner 2. This is a channel switching circuit that switches which of the variable resistors 17a to 17 of Mako Futagawa to operate, and here uses a binary counter 21 and a decoder 22.

That is, a pulse generating circuit 23, a binary counter 21 that counts the pulses, a binary-1 mirror falcon decoder 22 that selectively generates an output according to its binary output, and the counter 21 and The control circuit 24 controls the operation of the pulse generation circuit 23. 1 for decoder 22
Each of the output terminals a to p of the mochigo is equipped with an output switching transistor, and only one of these transistors is selectively turned on according to the binary output output from the counter 21, and the output terminals a to p are connected to each other. A low level output is generated at one of the 12 output terminals a to saw-connected variable resistor 1.
Among the transistors 7a to 17, current is caused to flow through only those connected to the output terminals of the transistors that are turned on, and the transistors are operated. When switching channels, one of the plurality of normally open switches 26a to 26 provided on the channel board 25, for example switch 26c, is closed.

At that time, if the channel at the position of the switch 26c is not selected, the output of the output terminal c of the decoder 22 to which the switch 26c is connected is at a high level.
The output is applied to the input terminal CH of the control circuit 24 via the switch 26c, and the output from the output terminal OC causes the pulse generation circuit 23 to start generating pulses, and the generated clock pulse CL is applied to the counter via the terminal UCL. Added to 21. This causes the counter 21 to start counting, and the conductivity of the transistors in the divider 22 changes accordingly. Then, when the transistor of the output terminal c to which the switch 26c is connected becomes conductive, the input to the input terminal CH of the control circuit 24 becomes low level, so the operation of the pulse generation circuit 23 is stopped, and from then on, the switch of another channel is The channel selection state is maintained until the channel is selected. If the frequency of the clock pulses generated by this pulse generation circuit 23 is set sufficiently high, for example, at about Fox HZ or higher, the above-mentioned channel switching can be completed in a short time as if a switch is closed. . 27U and 27D are switches that are opened and closed by operation signals such as ultrasonic waves or light when performing next channel selection by remote control or manual operation.
When 7U is operated, the control circuit 24 outputs the counter 2.
A count-up signal is applied to the counter 21 to select the channel one level above, and when the switch 270 is operated, a count-down signal is applied from the control circuit 24 to the counter 21 to select the channel one level below.

Next, 28 is a band switching circuit that switches the band of the tuner according to the channel switching performed as described above, and includes band setting switches 29a to 29 provided for each channel. , and a switching circuit 30 for the sliding door.

Each of the switches 29a to 29 has a contact L for the VHF low band, a contact T for the VHF high band, and a common contact for each of the three bands, and each of the common contacts has a resistor. It is connected to the output end of the channel-sliding circuit 20 via. 31V is a terminal that supplies operating power supply BV to VHF tuner 1, 31U is a terminal that similarly supplies operating power source U to old F tuner 2, and 31S is for band switching in VHF tuner 1. This is a terminal that supplies power source BS for coil switching.

Switch where VHF low band is set, for example 29
When channel a is selected, "A" in the table below will be displayed.
In this state, the VHF low band is selected.

Further, when a channel, for example, 29d, is selected by the switch to which the VHF high band is set, the state becomes "ro" and the VHF high band is selected. Furthermore, U
When a switch to which the HF band is set, for example, channel 29h, is selected, the state becomes "c" and the UHF band is selected. In this way, band switching is performed. Reference numeral 32 designates a channel display circuit, which displays the currently selected channel through display lamps 33a to 33 connected to each of the output terminals a to a of the channel switching circuit 20.

Reference numeral 34 denotes a defeat circuit, which uses a defeat signal outputted from the output terminal DEF of the control circuit 24 during channel switching to stop the display of the channel display circuit 32 during this period, and uses the output from the output terminal 35 to stop the display for the tuner. This is for stopping the operation of the AFC circuit.

FIG. 3 shows an example of a specific circuit of the channel switching circuit 20 in the channel selection device shown in FIG. This circuit has a special face in 1972-6.
1515, so it will be omitted here. The present invention is a channel selection switching device characterized in that it has two sets of channel switching devices and allows a user to switch between channels in a television receiver with a single operation.

A television receiver has two sets of channel selection circuits that can select channels independently, and in a device that allows viewing of two sets of independent CRTs or two sets of screens on one CRT, It has been desired to instantly switch the selected channel by pressing the - button.

When two sets of tuning switching devices using electronic tuners as shown in FIG. 2 are provided, conventionally, as shown in FIG.
A two-circuit cut-off switch is provided for each paddy paddy exchange switch Sa.
It has been considered to interlock ~Sp' and Sa'~Sp' with a relay or the like to switch the connection with the channel selection preset volume, thereby switching the two sets of channel selection. Conventionally, when receiving 12 stations, the selector switch was set to 2.
There are disadvantages in that four pieces are required and 24 wirings are required, resulting in a complicated device. The present invention eliminates this drawback of the conventional system and makes it possible to electronically change the selected channel instantly.

An embodiment of the present invention will be described below based on the drawings.

In FIG. 5, there are two sets of channel switching circuits 20 and 20', and channel selection can be performed independently of each other by directly selecting channel boards 25, 25' or sequentially selecting channels 27U, 2.
Possible with 7D and 27U', 270. If the channel switching circuit 20 currently selects channel c (CHc) and the channel switching circuit 20' selects channel b (CHh), by closing the switch 36, the selected channels are exchanged with each other, and the channel switching circuit 20' or Let us consider the operation of each part when CHb is selected and the channel switching circuit 20' selects CHc. When the switch 36 is closed, clock pulses from the clock pulse generators 41 and 41' are applied to the DN terminals of the channel switching circuits 20 and 20', and the selected channels are changed from CHc and CHb to CH, respectively.
The clock pulse generators 41 and 41' are moved until the ratio a is selected, and when the ratio C is selected, the respective clock pulse generators 41 and 41' are stopped. Also, the clock pulses generated from the clock pulse generators 41 and 41' are simultaneously input to the 4-bit reversible counter 4o.
, 40', and the generated clock pulses are counted in the UP direction. That is, the counter 40 counts 2 and the counter outputs Q, , Q2, Q3, Q4 are 001.
0, the counter 40' counts 1, and the counter outputs Q, Q2, Q3, and Q4 represent 0001. Next, the channel switching circuits 20 and 20'
When a is selected, the clock pulse generators 41, 41 are activated again.
' generates a clock pulse, and the reversible counters 40, 40
Clock pulses are generated by the number of pulses previously counted by ', that is, until the counter outputs Q, , Q2, Q3, and Q4 return to 0. The clock pulses of the clock pulse generator 41 are applied to the UP terminal of the channel switching circuit 20', that is, two clock pulses are applied, and the C
Hc is selected. Also, the clock pulse from the clock pulse generator 41' is applied to the UP terminal of the channel switching circuit 20, that is, one clock pulse is applied to the UP terminal of the channel switching circuit 20.
CHb is selected and channel swapping is completed.
FIG. 6 shows a timing diagram of each part of FIG. 5, and the above operation will be explained in detail based on this diagram as follows.

39, 39'...The flip-flop circuit inverts with a negative pulse, and the output becomes Hj.

48, 49... It is a monomulti circuit composed of transistors 48, 49, and the transistor 48 is normally conductive.

40, 40'... 4-bit reversible counter,
When the UP and DOWN terminal keys go low, input pulses are counted at the falling edge of the pulse.

20, 20'... UP, Do with channel switching circuit
At the rising edge of a negative polarity pulse at the wn terminal, the selected channel moves by -.

41, 41'... Clock pulse generator, UP,
When the Down terminal goes low, a clock pulse is generated.

...When the switch 36 is closed, a positive pulse is generated at the collector of the transistor 37 by the charging current of the capacitor connected to the switch 36, and the count of the reversible counters 40 and 40' is reset to 0000. do. In addition, a negative pulse is generated at the collector of the transistor 38 and applied to the S terminals of the flip-flops 39 and 39', the Q terminal is set to High, and the Q terminal is set to Low, so that the clock pulse generators 41 and 41' The UP terminal becomes a mountain, a clock pulse is generated, and the NAND gate 4
2, 42', 43, 43' are stamped. Q terminal is H
Since it is a J-rail, NAND gates 42 and 42' open,
The signals are applied to the DN terminals of the four-channel switching circuits 20 and 20', respectively, and the selected channel moves in the direction of CHa. ...CHa of the channel switching circuit 20' is selected, the R terminal of the flip-flop 39' becomes Low, the flip-flop 39' is inverted, and the Q terminal becomes High.
The gh and Q terminals become the peak w, and the clock pulse generator 41
The UP terminal of ' returns to the Hj track, and the generator 41' stops. On the other hand, in the channel switching circuit 20, CHb is selected. t3...The c terminal of the clock pulse generator 41 becomes High. t4...The C terminal of the clock pulse generator 41 fails, CHa is selected in the channel switching circuit 20, and the R terminal of the flip-flop 39 is selected.
The terminal becomes a peak w, the flip-flop is inverted, the Q terminal becomes High, the Q terminal becomes a peak w, the UP terminal of the clock pulse generator 41 returns to the Hi state, and the generator 41 stops. Then, the input terminals 1 and 2 of the NAND gate 46 are high.
Because of the heat generated, the output terminal 3 changes from Hi to W, and the monomulti circuit consisting of transistors 48 and 49 is inverted, and a positive pulse determined by the time constant of capacitor 53 and resistor 54 is sent to the collector of transistor 48. occurs in Therefore, input terminals 1 and 2 of NAND gates 45 and 45' are high.
Because of the i-heat, the output terminal 3 goes low, and the DOWN terminals of the clock pulse generators 41, 41' go low, generating clock pulses. t5...The c terminals of the clock pulse generators 41, 41' become Low, and the outputs Q, , Q2, Q3, Q4 of the reversible counter 40' become 000.
Returns to 0. Here, the output terminal 3 of the NAND gate 43
Although a narrow pulse of positive polarity is generated as shown by the * mark, it is removed by the CR filter of the UP terminal of the channel switching circuit 20, and the channel does not shift. The clock pulse generator 41' then stops. On the other hand, the output terminal 3 of the NAND gate 43' changes from Low to High, and the channel of the channel switching circuit 20' moves from CHa to CHb.
t6...The C terminal of the clock pulse generator 41 changes from the peak W to the Hi state. t7...The C terminal of the clock pulse generator 41 changes from High to W,
A narrow positive pulse is generated at the output terminal 3 of the NAND gate 43' as shown by the * mark, but the UP of the channel switching circuit is
It is removed by the CR filter at the terminal and the channel does not move. The clock pulse generator 41 returns the outputs Q, , Q2, Q, and Q4 of the reversible counter 40 to 0000, and performs NAND.
Output terminal 3 of gate 45 goes high and clock pulse generator 41 stops. t8...The monomulti circuit composed of transistors 48 and 49 is inverted,
The collector of transistor 48 goes low, and NAND
The input terminal 2 of the gates 43, 43' becomes the peak w, and the output terminal 3 becomes High from the peak w, and the channel switching circuit 20
is from CHa to C shame, and the channel cut-off circuit 20' is CH
The channel moves from b to CHc, and the channel switching is completed. When switching channels when one or both of the channel switching circuits 20 and 20' selects CHa, for example, the channel switching circuit 2
0 has selected CHa, when the switch 36 is closed, a clock pulse is generated, and the channel switching circuit 20 moves from CHa to CHp, and from CHp to CHo, CHn.
→Turn once to CHa. In this case, the clock pulse is 1
When the needle stick occurs, the reversible counter 40 returns to 0000 again, and the input terminal 1 of the NAND gate 45 does not become High.Therefore, the gate does not matter and the output terminal 3 of the NAND gate 45 does not go high, so a clock pulse is generated. The device 41 will not oscillate again. For this reason, CHp is effective lol
Then, the SKn terminal becomes Low, the internal clock generator of the channel switching circuit 20 oscillates, and the channel changes to C.
When it moves from Hp to CHo and returns to CHa, the clock pulse generator 41 generates 13 pulses, the output of the reversible counter 40 becomes 1111, the NAND gate 46 opens, and the clock pulse generator 41 oscillates again. It becomes possible. During channel replacement, the output terminal of the OR gate 47 becomes High, and the transistors 52, 52'
Even if conduction occurs and CHo, CHn, CHm become unstable, S
The Kp terminal does not go low. This is because when the SKp terminal becomes Low, the internal clock pulse of the channel switching circuit 20 and the clock pulse applied to the UP or DN terminal are applied twice, resulting in malfunction.
Note that when CHp goes low, the clock pulse generator 41 is turned off during one internal clock pulse. It is sufficiently narrower than the Tsuku pulse and will not malfunction. In the circuit shown in FIG. 5, the channel is reset to CHa when changing channels, but any station from CHa to CH may be used. As described above, according to the present invention, in a television receiver having two sets of channel selection conversion devices, it is possible to easily exchange the selected channels with each other with a single operation by the user, although the mechanism is simple. This has the advantage of eliminating the need for many switching switches and complicated wiring as in the past.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the main parts of a tuner, Fig. 2 is a basic block diagram of a conventional channel switching circuit, Fig. 3 is its specific circuit diagram, and Fig. 4 shows two sets of channel switching devices. FIG. 5 is a configuration diagram showing an embodiment of the present invention, and FIG. 6 is a waveform diagram of each part thereof. 20, 20'... Channel switching circuit, 25, 25
'...Tuition selection switch board, 27U, 27D, 27U'
, 27D'... Sequential tuning switch, 36...
...Switch, 39, 39'...Flip-flop,
40, 40'...4-bit reversible counter, 41
, 41' clock pulse generator. Figure 1 Figure 2 Figure 4 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] 1 The channel selection voltage applied to a tuner using a variable capacitance diode as a tuning element is set in advance using a plurality of variable resistors, and channel switching is performed by switching and operating the variable resistors. In a television receiver equipped with two sets of channel selection switching devices, which are equipped with two sets of clock pulse generators and reversible counters, when a control signal is applied by a switch or a remote control such as light or sound waves, the 1 clock pulse generator to the first clock pulse generator.
A clock pulse is applied to the sequential tuning terminal of the tuning switching device and the first reversible counter, and a clock pulse is applied from the second clock pulse generator to the sequential tuning terminal of the second tuning switching device and the second reversible counter. is applied, the number of channels moved to a specific channel by the first and second channel selection switching devices is counted by the first and second reversible counters, and the clock pulse generator is applied again by the first and second clock pulse generators. The counted number of clock pulses are generated respectively, and the first clock pulse generator generates the second clock pulse.
from the second clock pulse generator to the sequential tuning terminals of the first tuning switching device to select between the first and second tuning switching devices. A channel selection device characterized by changing channels.