JPS6029781A - Interface circuit inspection system for monochromatic video signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a monochrome video signal interface circuit testing method, and is particularly suitable for testing a monochrome video signal interface circuit, for example, in the interface circuit testing of a personal computer. This invention relates to an interface circuit testing method for monochrome video signals.

[Background of the invention]

First, FIG. 1 shows a schematic block diagram of a testing apparatus ρ used in a conventional monochrome video signal interface circuit testing method, and the following description will be made with reference to this block diagram.

Normally, for example, an interface circuit test for a monochrome video signal output from a personal computer is performed using a floppy disk 1. Monochrome display 3.
A keyboard 4 is connected to the personal computer 2 to be inspected.

When the key to start the test is pressed on the keyboard 4, the test program is input from the floppy disk 1 to the personal computer 2 to be tested, the test is about to begin, and the test pattern is displayed on the monochrome display 3. This pattern is visually inspected by an operator 4o to see if there is any erroneous display, and a pass/fail judgment of the interface circuit is made.

However, this visual inspection method takes time, and it is difficult for the human eye to detect small bits missing or out of focus, which can lead to operator fatigue.
The work efficiency was poor.

Therefore, there is a need for a high-speed, highly reliable inspection method that automates these processes.

[Purpose of the invention]

The present invention eliminates the drawbacks of the prior art described above, and in response to the above requirements, provides an ink interface for monochrome video signals related to an automatic testing method for testing monochrome video signal interface circuits of personal computers at high speed and with high precision. Its purpose is to provide a circuit testing method.

[Summary of the invention]

The monochrome video signal interface circuit testing method according to the present invention converts the monochrome video signal into a TTL video signal, and checks the phase shift between the TTL video signal and the basic clock of 16 MHz dot frequency (1 screen display dot 60 ns). Timing correction is performed by a timing circuit including a delay circuit, and as a result, the TT
The inspection is made possible by sampling approximately at the center of 1 dot 5 Qns of the L video signal.

In addition, the following is added.

The interface circuit inspection method for monochrome video signals according to the present invention is an alternative to the visual inspection method by an operator, and includes a comparator for converting a video signal into a TTL video signal, a counter for counting a basic clock, and a delay circuit for adjusting sampling timing. This is an automatic inspection method using a microcomputer that processes data and controls delay circuits.

The major problem is that the video signal is as fast as 60nS per dot, and the phase shift between the 16MHz dot frequency basic clock and the video signal varies depending on the individual workpiece.This phase shift can be corrected by using a delay circuit. When adjusting and data sampling, 1 dot 60
The circuit configuration is such that sampling is performed approximately at the center of nS, so that sampling can be performed without abnormality even when there is a jumper or the like.

The detection position is set by a microcomputer, the clock counter and raster counter extract a matching signal, and the detection position is freely set.

It was made so that it could be taken out.

[Embodiments of the invention]

An embodiment of the monochrome video signal interface circuit testing method according to the present invention will be described with reference to FIGS. 2 to 4.

Here, FIG. 2 is a block diagram of a testing device used in an embodiment of the monochrome video signal interface circuit testing method of the present invention, and FIG. 3 is a timing chart thereof.
FIG. 4 is a flowchart of the initial setting.

In the figure, 2 is a personal computer to be tested, 5 is a comparator, 6 is a shift register, 7 is a microcomputer, 8, 15
．． 20 is a D flip-flop, 9° 16 is an RS flip-flop, 10 and 17 are ANI) circuits, 11 and 18 are counters, 12 and 19 are registers, 13 is a tapped delay line, 14 is a multiplexer, 21 is a clock counter, 22 is a raster counter, and 23 is a NAND circuit.

Also, 24 is a video signal, 25 is an 'I' T L video signal, 26 is an H8ynC signal, 27 is a 16M flow signal (delay), and 32 is an I (SynS signal (16M
clock synchronization, delay), 33 is a counter gate, 3
4 is the counter clock, 35 is the column setting value, 36 is the rask setting value, 37 is the VSync signal, 38 is the VSync
Signal (delay) and 39 indicate DMA (transfer by direct memory access control) tl, respectively.

Therefore, the D flip-flops 8 and 15, the S flip-flops 9 and 16, the AND circuit 10° 17, the counters 11 and 18, the registers 12 and 19, the tapped delay line 13, the multiplexer 14, etc. are delay circuits. This constitutes a timing circuit including:

The present embodiment relates to an interface circuit testing method for a monochrome video signal of a personal computer.

In Fig. 2, as an initial setting, first set the horizontal synchronization at the first dot in the first horizontal period, and measure the time from the horizontal synchronization signal to the first dot using a counter for each PC to be tested. 1st from the rise of the signal
Measure the time to the dot.

There are two reasons for this; one is that each computer to be tested has different characteristics, so initial settings must be made each time.
One is to prepare for automatic inspection, and the other is the video signal and 16MHz dot frequency (one dot displayed on the screen) for 60ns.
) 16MH2 (referred to as 16M).

) Corrects the phase shift of the synchronization signal, resulting in 1 dot) 5 Q
This is because data sampling is performed approximately at the center of ns.

Next, the circuit configuration and initial settings of the inspection device will be explained together.

'That is, first, the video signal 24 output from the personal computer 2 under test is converted into a TTL video signal 25 by the comparator 5.
and sends the data to the shift register 6.

Next, the )(Sync (horizontal synchronization) signal 26' is input to the rD fringe flop 8 to generate the H8sync signal (16M clock synchronization) 28 synchronized with the 16M clock signal 27, and this )(Sync signal (16M clock synchronization) 28 The pulse width from to the rising edge of the TTL video signal 25 (
Counter game 1-29) tRs flip frog 9 is operated, its counter gate 29 and 16M clock signal 27
and 'tAND circuit 10 to output the counter clock 30.
is detected, the counter 11 counts the signal (a, count number n in FIG. 4), and the register 12 temporarily stores it.

Following this, the microcomputer 7 controls the multiplexer 14 by using a tapped delay line 13 with a maximum of 5 QnS and an interval of 5 ns.
A clock signal (delay) 31 is obtained.

That is, as shown at the beginning of FIG. 4, a 16M clock signal (delay) 31 is obtained by performing delay processing in 5 ns increments by sequentially switching the tap L.

Next, in order to take out the I (SynC signal (16M clock synchronization, delay)) 32 synchronized with this 16M clock signal (delay) 31, a D flip-flop 15 is provided, and similarly to the circuit described above, the H8:yne signal ( 16M
Clock synchronization, from the start-up of Din-English 32, TT
The pulse width (counter gate 33) up to the rising edge of the L video signal 25 is created by the RS fritz flop 16,
The counter gate 33' and the 16M clock signal (delay) 3'1 are pulled into the AND circuit 17, and the counter clock 34 is detected.

Then, the signal is counted by a counter 18 (c, count number m in FIG. 4) and stored in a register 19.

After that, the microcomputer 7 compares the data in the previous register 12 and the register 19 (Figure 4, 2).
The delay amount is increased until the latter count number m becomes one count less than the former count number n (route N1 in FIG. 4).

When this operation is performed and the count decreases by 1, the increase in the delay amount is stopped and the condition prepared in advance (for example, 1
Since the count decreased by 1 when the delay was delayed by 0 ns, the multiplexer 14 was controlled by the microcomputer software to control the amount of delay.
, TTL video signal 25 screen display 1 dot approximately 60ns
Try to get the timing to be approximately in the center of the This is shown in FIG. 3C.

In addition, in Fig. 4 E, (10+25 ns delay) means when the number of taps t≦5 (the delay amount up to 2 in Fig. 4 is 5 or less, that is, from 5 ns to 25 ns),
An additional 5 taps, or 25n'Se delay is shown.

This makes it possible to sample data for each dot, and the timing structure is such that even if there is jitter in the video signal, it can be detected with ample margin.

When sampling data, there is a method of increasing the sampling speed, but if the basic clock is 16M
H2, and when dealing with higher frequencies T T
This was not possible with an L circuit, and the method described above became necessary.

Next, when the above-mentioned initial settings are completed, which position should be detected will be explained.

That is, as shown in FIG. 2, the software controls the microcomputer 7 to set the column setting value 35. Set the raster setting value 3G, and in the case of column position detection, use the clock counter 21 to 16M clocks (delay) 31
The configuration is such that a reset is performed using the HS y "C signal (16M clock synchronization, delay) 32, and a preset column position is detected.

Furthermore, raster position detection is performed using the raster counter 22 at f(S
ync signal (16M clock synchronization, delay) 32 counts, VSync (vertical synchronization) signal (delay)
The configuration is such that a reset is applied at step 38, and a preset raster position is detected.

Note that the VSync signal (delay) 38 is a VSync signal (delay) synchronized with the 16M clock signal (delay) 31.
Signal 37'f: To obtain 1] flip-flop 20
This is what was obtained by inputting it into .

This column, raster detection value and 16M clock signal (delay) 31 are input to the NAND circuit 23, clocks are applied to the shift register 6 and DMA 39 for high-speed data transfer, and the detection data is taken into the microcomputer 7.

Then, the detection data and the microcomputer 7
Pass/fail judgment is made by comparing with reference values stored in the memory of

In this way, the signal waveform can be inspected at a high speed of 1 dot (iQns), and there is a phase difference between the video signal and the 16 MHz synchronization signal, making it difficult to get the timing right. This system was used to enable data sampling to be taken approximately at the center of one dot (60I]S, and a microcomputer was used to control these processes, making a high-speed, highly reliable automatic inspection method possible. .

Therefore, the above embodiment relates to an interface circuit testing method for a monochrome video signal of Kunokon, but the present invention is a general-purpose method for testing an interface circuit for a monochrome video signal other than the above. It is something.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to automate the interface circuit inspection of monochrome video signals.
This invention can overcome the drawbacks of conventional visual inspection and enable a highly reliable and high-speed inspection method, and can be said to be an invention that has excellent practical effects.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a testing device used in a conventional monochrome video signal interface circuit testing method, and FIG. 2 is a schematic block diagram of a testing device used in an embodiment of the monochrome video signal interface circuit testing method of the present invention. FIG. 3 is a block diagram of the inspection equipment, and FIG. 4 is a timing chart thereof.
It is a flowchart figure of the initial setting. 2...PC to be tested, 5...Kono Kushiri,
6...Shift register, 7...Microcomputer, 8゜15.20...D flip-flop, 9,16
...RS flip-flop, 10, 17...AND
Circuit, 11.18... Counter, 12.19... Register, 13... Delay line with tap, 14...
・Multiplexer, 21...Clock counter, 22
... Raster counter, 23 ... NAND circuit, 24
...Video signal, 25-TTL video signal, 26-A
5ync signal, 27-16M clock signal, 2B-H8
ync signal (16M clock synchronization), 29... Counter gate, 30... Counter clock, 31...16
M clock signal (delay), 32...H8y n
C signal (16M clock synchronization, delay), 33...
Counter gate, 34... Counter clock, 35.
...Kasim setting value, 36...Raster setting value, 37...
・VS sync signal, 38...■5ynC signal (delay), 39...1) M A 0 Agent Patent attorney Kosaku Fukuda (and 1 other person) 1 seed 2 eyes 3 mouth, UU dent 11 1112J41

Claims (1)

[Claims] 1. Converting a monochrome video signal to a TTL video signal,
A timing circuit including a delay circuit corrects the phase difference between the TTL video signal and the basic clock with a 16 MHz dot frequency (1 dot displayed on the screen, 60 nS). 1. A monochrome video signal interface circuit testing method, characterized in that sampling is possible at approximately the center of 60 nS of a TTL video signal, including signals out of phase with the TTL video signal. 2. In the device described in claim 1, timing correction is performed, a detection position of the screen is set by a microconbeater, and a coincidence signal is extracted by a rip counter, a raster counter, etc. An interface circuit testing method for monochrome video signals in which the detection position can be freely set and the extracted data is compared with a reference value prepared in advance by software to determine pass/fail.