JPS6029044A - Digital/analog converter - Google Patents

Digital/analog converter

Info

Publication number
JPS6029044A
JPS6029044A JP11907683A JP11907683A JPS6029044A JP S6029044 A JPS6029044 A JP S6029044A JP 11907683 A JP11907683 A JP 11907683A JP 11907683 A JP11907683 A JP 11907683A JP S6029044 A JPS6029044 A JP S6029044A
Authority
JP
Japan
Prior art keywords
emitter
base
digital
potential difference
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11907683A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yasutake
安武 信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11907683A priority Critical patent/JPS6029044A/en
Publication of JPS6029044A publication Critical patent/JPS6029044A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/78Simultaneous conversion using ladder network
    • H03M1/785Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To adjust dispersion of potential difference between base resistance of a transister TR and emitter, and even current value of each current source, thereby making it possible to be used for high bit by connecting base resistance between constant voltage generation measures and multiple transisters TRs. CONSTITUTION:For a D/A converter, multiple transisters Tr11-Tr16 and constant voltage generation operation amplifier OP are provided. To the emitter side of these multiple Tr11-Tr16, R-2R ladder resistance RR11 is connected, and output terminals Iout11-Iout12 are connected to the collector side of these transisters through switches S11-S14. Base resistance Rb is connected between the output side of this operation amplifier OP and base of respective Tr11- Tr16. Resitance Rb adjusts dispersion of potential difference between bases of Tr11-Tr16 and emitter, and entire current values in respective current source are evened, thereby making it possible to be used not only for low bit but also for high bit.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明はデジタル信号をアナログ信号に変換′″l−る
デジタルアナログコンバータに関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a digital-to-analog converter for converting digital signals into analog signals.

(2)技術の背景 最近、例えば情報の処理や伝送には符号化されたデジタ
ル信号が品質的に安定した結果が得られ7ることがら広
く用いられている。ところがこのようなデジタル信号よ
り得られた結果はそのままでは使用できないためこれを
必要によりアナログ信号に変換するようにしており、こ
こにデジタルアナログコンバータが用いられる。
(2) Background of the Technology Recently, encoded digital signals have been widely used for processing and transmitting information, for example, because they provide stable results in terms of quality. However, since the results obtained from such digital signals cannot be used as they are, they are converted into analog signals as necessary, and a digital-to-analog converter is used here.

(3)従来技術と問題点 しかして、従来この種のデジタルアナログコンバータで
例えば4ビツト用のものとして第1図に示すようにトラ
ンジスタTr+〜Traのベースを共通接続し、またエ
ミッタ側に抵抗Reを接続するとともにコレクタ側にス
イッチ81〜S4を介してR−2Rラダー抵抗RRを接
続したものがある。ここで■ゆは出力端子である。
(3) Prior art and problems However, conventionally, in this type of digital-to-analog converter, for example, for 4 bits, the bases of transistors Tr+ to Tra are commonly connected as shown in FIG. 1, and a resistor Re is connected to the emitter side. There is one in which an R-2R ladder resistor RR is connected to the collector side via switches 81 to S4. Here ■yu is the output terminal.

上記のものは上記スイッチ81〜S4を4ビツトの2進
化符号によってオン、オフすることにより出力端子I。
The above output terminal I is turned on and off by turning on and off the switches 81 to S4 using a 4-bit binary code.

Vrに対応するアナログ出力を発生するようにしている
An analog output corresponding to Vr is generated.

ところで、トランジスタTrI−Tr4によって構成さ
れる電流源は各トランジスタ共通のベース電圧VIIE
F、ベース・エミッタ間電圧Vbe。
By the way, the current source constituted by transistors TrI-Tr4 has a base voltage VIIE common to each transistor.
F, base-emitter voltage Vbe;

電源電圧Vとすると電流lは VRFF −Vbe −V ■ −□− e で定まる。しかし、実際トランジスタTr+〜Triの
ベース・エミッタ間の電位差は0.7〜0.8Vである
ものの、ある範囲でバラツキを有するので各電流源での
電流値Iが等しくなくなる。
When the power supply voltage is V, the current l is determined by VRFF -Vbe -V ■ -□-e. However, although the potential difference between the base and emitter of transistors Tr+ to Tri is actually 0.7 to 0.8 V, it varies within a certain range, so the current values I in each current source are not equal.

そこでエミッタ側の抵抗Reの値をトリミングすること
により各電流源での電流■を等しくするようにしている
Therefore, by trimming the value of the resistor Re on the emitter side, the currents {circle around (1)} in each current source are made equal.

ところで、このようにトランジスタのコレクタ側にR〜
2Rラダー抵抗RRを有するものは出力インピーダンス
がR2Rラダー抵抗にで決定されるため出力インピーダ
ンスを大きくすることができず高精度のデジタルアナロ
グコンバータを得ることができなかった。
By the way, as shown above, R~ is connected to the collector side of the transistor.
In the case of a converter having a 2R ladder resistor RR, the output impedance is determined by the R2R ladder resistor, so the output impedance cannot be increased and a highly accurate digital-to-analog converter cannot be obtained.

このため従来出力インピーダンスを大きくしたものとし
て第2図に示すようにトランジスタTr1〜Traのベ
ースを共通接続するとともにエミッタ側に2−2Rラダ
ー抵抗RRを接続し、またトランジスタTrz〜Trb
のコレクタ側にスイッチ31〜S4を介して出力端子■
0IJT I +I OUT 2を接続したものがある
。ここで、OPは差動増幅器で、トランジスタT r 
+ 、抵抗RBとともに定電圧回路をなし、上記トラン
ジスタTr+〜Tr6のベースに定電圧を供給するよう
にしている。また、トランジスタTrsはコレクタ側を
接地している。
Therefore, as shown in Fig. 2, the conventional output impedance was increased by connecting the bases of transistors Tr1 to Tra in common, and connecting a 2-2R ladder resistor RR to the emitter side, and also connecting transistors Trz to Trb.
Output terminal ■ via switches 31 to S4 on the collector side of
There is one that connects 0IJT I +I OUT 2. Here, OP is a differential amplifier, and transistor T r
+ and resistor RB form a constant voltage circuit, and supply a constant voltage to the bases of the transistors Tr+ to Tr6. Further, the collector side of the transistor Trs is grounded.

しかして、上記のものによれば出力インピーダンスはR
−2Rラダー抵抗RRによって左右されないので大きな
ものに設定できる。
According to the above, the output impedance is R
Since it is not influenced by -2R ladder resistance RR, it can be set to a large value.

ところが、これもトランジスタTr+−Trsのベース
・エミッタ間の電位差にバラツキがあるため各電流源で
の電流に相違を生ずる。そこで、エミッタ側の抵抗つま
りR−2Rラダー抵抗RRをトリミングすることが考え
られるがこのように自己のエミッタ側抵抗をトリミング
するとR−2Rラダー抵抗の関係がくずれこの時の電位
降下ルアナログコンバータではせいぜい8ビツトまでの
低位のものにしか用いることができなかった。
However, since there is variation in the potential difference between the base and emitter of the transistors Tr+ and Trs, a difference occurs in the current in each current source. Therefore, it is possible to trim the emitter side resistance, that is, the R-2R ladder resistance RR, but if you trim the own emitter side resistance in this way, the relationship between the R-2R ladder resistance will be broken, and the potential drop at this time will be lower in the analog converter. It could only be used for low-level data up to 8 bits at most.

(4)発明の目的 本発明は上記従来の欠点を除去するためなされたもので
、各電流源のトランジスタのベース・エミッタ間の電位
差のバラツキを簡単に調整し得、高位ビットのものへの
使用を可能にしたデジタルアナログコンバータを提供す
ることを目的とする。
(4) Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks of the conventional technology, and can easily adjust the variation in the potential difference between the base and emitter of the transistor of each current source, and can be used for high-order bits. The purpose is to provide a digital-to-analog converter that makes it possible.

(5)発明の構成 本発明の特徴とするところは複数のトランジスタと、該
複数のトランジスタのエミ・ツタ側に接続されたR−2
Rラダー抵抗と、定電圧を発生する手段と、該定電圧を
発生する手段と前記トランジスタのベースの間に接続さ
れ前記トランジスタのベースエミッタ間の電位差のバラ
ツキを調整するベース抵抗とを具備したことを特徴とす
るデジタ゛ルアJ−ログコンバータにアル。
(5) Structure of the Invention The present invention is characterized by a plurality of transistors and an R-2 connected to the emitter and ivy sides of the plurality of transistors.
comprising an R ladder resistor, means for generating a constant voltage, and a base resistor connected between the means for generating the constant voltage and the base of the transistor to adjust variations in potential difference between the base and emitter of the transistor. A digital lure J-log converter featuring the following features:

(6)発明の実施例 以下、本発明の一実施例を第3図に従い説明する。(6) Examples of the invention An embodiment of the present invention will be described below with reference to FIG.

この実施例ではこの発明を4ビツト用のデジタルアナロ
グコンバータに通用した例を示している。
This embodiment shows an example in which the present invention is applied to a 4-bit digital-to-analog converter.

第3図においてTr++〜Tre6はトランジスタで、
これらトランジスタTr++〜Tr+sのエミッタ側に
R−2Rラダー抵抗RR++を接続している。またトラ
ンジスタTr+ 2〜T r Isのコレクタ側にスイ
ッチS++〜Se<を介して出力端子1゜UTI I+
 rotrrl 2を接続している。
In FIG. 3, Tr++ to Tre6 are transistors,
An R-2R ladder resistor RR++ is connected to the emitter side of these transistors Tr++ to Tr+s. In addition, an output terminal 1°UTI I+ is connected to the collector side of the transistors Tr+ 2 to Tr Is via switches S++ to Se<.
rotrrl 2 is connected.

一方、OP++は差動増幅器で、正側入力端子を接地し
、また負側入力端子をトランジスタTr+1のコレクタ
に接続するとともに抵抗R++を介コレクタは接地して
いる。
On the other hand, OP++ is a differential amplifier whose positive input terminal is grounded, and whose negative input terminal is connected to the collector of the transistor Tr+1, and whose collector is grounded through a resistor R++.

ところで、第3図の回路においても従来と同様にトラン
ジスタ’p r ++〜Tr+sのベース・エミッタ間
での電位差のバラツキが考えられるが、・ ここではベ
ース抵抗R1,をトリミングして各トランジスタTr1
1〜T r + aのベースに流れる電流Iしとベース
抵抗Rトにより生じる電位差Iト 。
By the way, in the circuit shown in FIG. 3, there may be variations in the potential difference between the bases and emitters of the transistors 'pr++ to Tr+s as in the conventional case, but here, the base resistor R1 is trimmed and each transistor Tr1 is
1 to T r + The potential difference I generated by the current I flowing to the base of a and the base resistance R.

R1)により各トランジスタTr++〜Tr+aのベー
ス・エミッタ間の電位差のバラツキを打ち消すように調
整し各トランジスタTr++〜Tr16のエミッタ電位
Veが等しくなるようにする。この場合トランジスタT
r++〜Tr+ 6のベース・エミッタ間の電位差のバ
ラツキがベース側の抵抗RI+により個別に調整される
ようになるので、電流源相互間での影響をなくすことが
できる。 従ってこのようにすればトランジスタTr+
+〜Tr16を有する各電流源での電流値を全て等しく
できるので、この状態でスイッチSll”S14を4ビ
ツトの2進化符号でオンオフすることによりこれに対応
するアナログ出力を高精度に得られる。
R1) is adjusted so as to cancel out the variation in the potential difference between the base and emitter of each transistor Tr++ to Tr+a, so that the emitter potential Ve of each transistor Tr++ to Tr16 becomes equal. In this case transistor T
Since the variations in potential difference between the bases and emitters of r++ to Tr+ 6 are individually adjusted by the base-side resistor RI+, the influence between the current sources can be eliminated. Therefore, if you do this, the transistor Tr+
Since the current values in the current sources having + to Tr16 can all be made equal, in this state, by turning on and off the switch Sll''S14 with a 4-bit binary code, a corresponding analog output can be obtained with high precision.

(7)発明の効果 本発明によるデジタルアナログコンバータは、トランジ
スタTr++〜Tr+sのベース・エミッタ間の電位差
のバラツキを簡単に調整できるので各電流源での電流値
を全て等しく揃えることができ、これにより低位ビット
用は勿論高位ビット用としても使用を可能にできる。
(7) Effects of the Invention The digital-to-analog converter according to the present invention can easily adjust the variation in the potential difference between the base and emitter of the transistors Tr++ to Tr+s, so that the current values in each current source can all be made equal. It can be used not only for low-order bits but also for high-order bits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のデジタルアナログコンバータの一実施例
を示す回路図、第2図は同コンバータの他の実施例を示
す回路図、第3図は本発明の一実施例を示す回路図であ
る。 Tr++〜Tr+a・・・トランジスタRRII・・・
R−2Rラダー抵抗 S++〜S+a ・ ・ ・スイッチ Rh ・・・ベース抵抗 0P11・・・オペアンプ 第1図 第2図 ■ 第3図 (JV
FIG. 1 is a circuit diagram showing one embodiment of a conventional digital-to-analog converter, FIG. 2 is a circuit diagram showing another embodiment of the same converter, and FIG. 3 is a circuit diagram showing one embodiment of the present invention. . Tr++~Tr+a...Transistor RRII...
R-2R ladder resistance S++~S+a ・ ・ ・Switch Rh ・・Base resistance 0P11・・Operation amplifier Fig. 1 Fig. 2 ■ Fig. 3 (JV

Claims (1)

【特許請求の範囲】[Claims] 複数のトランジスタと、該複数のトランジヌ、夕のエミ
ッタ側に接続されたR−2Rラダー抵抗と、定電圧を発
生する手段と、該定電圧を発生する手段と前記トランジ
スタのベースの間に接続され前記トランジスタのベース
エミッタ間の電位差のノマラッキを調整するベース抵抗
とを具備したことを特徴とするデジタルアナログコンバ
−タ。
a plurality of transistors, an R-2R ladder resistor connected to the emitter side of the plurality of transistors, a means for generating a constant voltage, and a resistor connected between the means for generating the constant voltage and the base of the transistor. A digital-to-analog converter comprising a base resistor for adjusting a normalization of a potential difference between the base and emitter of the transistor.
JP11907683A 1983-06-30 1983-06-30 Digital/analog converter Pending JPS6029044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11907683A JPS6029044A (en) 1983-06-30 1983-06-30 Digital/analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11907683A JPS6029044A (en) 1983-06-30 1983-06-30 Digital/analog converter

Publications (1)

Publication Number Publication Date
JPS6029044A true JPS6029044A (en) 1985-02-14

Family

ID=14752281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11907683A Pending JPS6029044A (en) 1983-06-30 1983-06-30 Digital/analog converter

Country Status (1)

Country Link
JP (1) JPS6029044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233330A (en) * 1990-06-11 1992-08-21 Internatl Business Mach Corp <Ibm> Bicmos digital/analog converter for disk drive digital recording channel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04233330A (en) * 1990-06-11 1992-08-21 Internatl Business Mach Corp <Ibm> Bicmos digital/analog converter for disk drive digital recording channel

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