JPS6028382A - Control circuit for video camera - Google Patents

Control circuit for video camera

Info

Publication number
JPS6028382A
JPS6028382A JP58135860A JP13586083A JPS6028382A JP S6028382 A JPS6028382 A JP S6028382A JP 58135860 A JP58135860 A JP 58135860A JP 13586083 A JP13586083 A JP 13586083A JP S6028382 A JPS6028382 A JP S6028382A
Authority
JP
Japan
Prior art keywords
circuit
signal
high light
screen
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58135860A
Other languages
Japanese (ja)
Other versions
JPH0584106B2 (en
Inventor
Toshio Murakami
敏夫 村上
Himio Nakagawa
一三夫 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58135860A priority Critical patent/JPS6028382A/en
Publication of JPS6028382A publication Critical patent/JPS6028382A/en
Publication of JPH0584106B2 publication Critical patent/JPH0584106B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70Circuitry for compensating brightness variation in the scene

Abstract

PURPOSE:To suppress an abnormal phenomenon such as blooming or comet tail to a degree not remarkable by adding a voltage detecting a high light signal exceeding a prescribed level to a conventional control signal so as to apply the control also to a signal of an abnomal high light portion. CONSTITUTION:An output signal of a gate circuit 9 is detected by a peak detection circuit 10 and an average value detecting circuit 11, and an output signal of a high light signal detecting circuit 16 is detected by a peak detecting circuit 17 respectively and they are outputted to an output of an adder circuit 20 as a control voltage. In case of the content of image pickup where the contrast ratio among various objects in a pickup screen is almost uniform over the entire screen or a video signal is a prescribed high light detection level Vth or below, an iris circuit and an AGC circuit are controlled by a control voltage only obtained based on the video signal at the screen center portion extracted by a gate circuit 9. If an abnormal high light is generated at the surrounding of the screen, the circuits are controlled for a prescribe rate also with a voltage detecting the high light signal being the Vth or over, and an optimum picture is obtained by suppressing comet tail or blooming.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はビデオカメラの信号処理回路に関し特に自動絞
り(オートアイリス)回路、自動利得制御(AGC)回
路の制御電圧を発生させる検波回路に関するものである
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a signal processing circuit for a video camera, and particularly to a detection circuit that generates control voltages for an automatic iris circuit and an automatic gain control (AGC) circuit. .

〔発明の背景〕[Background of the invention]

従来、ビデオカメラでは回路のダイナミックレンジに対
して、入射光、あるいは信号量を適性化するためオート
アイリス回路、 AGC回路を設けているのが一般であ
る。上記各回路を制御する電圧は映像(輝度)信号を検
出し、整流平滑(検波)して得ているが、必要に応じて
映像内容に応じた、平均値的な検波電圧を得て画像の平
均的な明ゆるさに制御する、高輝度に対応した尖頭値的
な検波電圧を得て高輝度部が適性化されるように制御す
る、あるいはその両者に混合電圧を得るなどしている。
Conventionally, video cameras are generally equipped with an auto-iris circuit or an AGC circuit in order to optimize the amount of incident light or signal for the dynamic range of the circuit. The voltages that control each of the above circuits are obtained by detecting the video (luminance) signal and rectifying and smoothing (detecting) it, but if necessary, an average detected voltage can be obtained depending on the video content to improve the image quality. The brightness is controlled to an average brightness, the peak detection voltage corresponding to high brightness is obtained to optimize the high brightness area, or a mixed voltage is obtained for both.

第1図は従来G−回路構成例を示すが、以下第1図、第
2図を用いて従来例を説明する。第1図において、1は
レンズ装置で、2はアイリス機構である。3は撮像素子
で映像信号が出力されプリアンプ4に工って増幅された
後、信号処理回路5によってクランプ、ベディスクル成
分付加、ブランキング、など種々信号処理が施こされる
。しがる後AGC回路6によって信号レベルが適性化さ
れ端子7に出力される。それ以降、図示していないが、
別途、種々カメラ信号処理を行なう。端子7に得た映像
信号のうち、画面のほぼ中央部に相当する信号をゲート
回路9の端子8に印加するゲートパルスによって抽出し
、該抽出した信号を尖頭(ピーク)値検波回路10.平
均値検波回路11によりそれぞれ検波し、加算回路12
によって所望の比率で加算してアイリス用、 AGC用
の制御電圧を得ている。検波して得た制御電圧は増幅回
路13にて増幅されAGC、アイリス切換え回路14に
印加される。この切換え回路14はまず入射光量が比較
的少ない時は、入射光量が大きくなるとともに最大利得
状態から利得減衰する様な制御電圧をAGC回路乙に与
え、所定の利得制御を終えた後、さらにレンズへの入射
光量が大きくなると、それとともに次にアイリス機構2
を開放状態から除々に閉じるように制御する制御電圧を
アイリス駆動回路15に与えて撮像素子3に入射される
光量を制御する。上記説明の如くして端子7に得られる
映像信号のレベルを、入射光量の広範囲にわたって所定
値になるように制御している。
FIG. 1 shows an example of a conventional G-circuit configuration, and the conventional example will be explained below using FIGS. 1 and 2. In FIG. 1, 1 is a lens device and 2 is an iris mechanism. Reference numeral 3 denotes an image pickup device that outputs a video signal, which is amplified by a preamplifier 4, and then subjected to various signal processing such as clamping, addition of a pedicle component, and blanking by a signal processing circuit 5. After that, the AGC circuit 6 optimizes the signal level and outputs it to the terminal 7. After that, although not shown,
Separately, various camera signal processing is performed. Of the video signals obtained at the terminal 7, a signal corresponding to approximately the center of the screen is extracted by a gate pulse applied to the terminal 8 of the gate circuit 9, and the extracted signal is sent to the peak value detection circuit 10. The average value detection circuit 11 detects each wave, and the addition circuit 12
The control voltages for the iris and AGC are obtained by adding them at a desired ratio. The control voltage obtained by the detection is amplified by the amplifier circuit 13 and applied to the AGC and iris switching circuit 14. When the amount of incident light is relatively small, this switching circuit 14 first applies a control voltage to the AGC circuit B such that the gain attenuates from the maximum gain state as the amount of incident light increases, and after completing the predetermined gain control, As the amount of light incident on the iris mechanism 2 increases, the iris mechanism 2
The amount of light incident on the image sensor 3 is controlled by applying a control voltage to the iris drive circuit 15 so as to gradually close the iris from an open state. As explained above, the level of the video signal obtained at the terminal 7 is controlled to a predetermined value over a wide range of the amount of incident light.

ゲート回路9の役割を以下に説明する。一般にビデオカ
メラの撮影者は撮影したいと思う被写体を画面の中央部
に位置する様に、例えば人を撮影したい場合、第2図に
示すように人の顔が画面の中央部に位置するようにカメ
ラ操作するが、通常は撮像画面内の種々被写体間のコン
トラスト比が一様な場合が多いので、撮影画面全領域に
わたる映像信号を検出して、アイリス及びAGCf制御
しても何ら不自然はない。ところが第2図に示すように
人物の背景、例えば画面上部Aに空が撮影されたり、あ
るいは逆光状況の場合、あるいは室内において、人物背
後に叶い光灯などの光源が直接撮影されたりするなど、
撮影したい被写体に対するコントラスト比が比較的大き
な撮影状況も多々発生する。この様な撮影状況の場合、
従来の制御の方法では、第3図(α)に示すように映像
レベルの支配的な上記背景の絵柄(,4)に該当する振
幅を適性化する様に映像信号レベルを制御してしまい、
本来撮影したい被写体が(B)部に示すように、定格レ
ベルに対して点(暗)く、しずんでしまい、撮影画像が
極めて不自然となる。ここでゲート回路9を設けて第2
図の破線で示すように画面の中央部Bの映像信号を検出
すれば第3図<h)のB′に示されるように上記状況下
においても撮影しようとする被写体に対する映像信号が
適性化される。この場合、定格レベルを越える背景の高
輝度部(A′)は端子7以降九設けられるカメラ信号処
理回路の白ピーククリップ処理にエリ定格の120〜1
50チ程度クリップされる。高輝度部をクリップするこ
とはビデオカメラにおいて通常の信号処理手段であり、
もともと高輝度(白い画像)でもあるので、撮影画像に
さほどの不自然は感じない。そのため、上記したように
ゲート回路9は撮影目的に対してがなりの効果を発揮す
る。ところが第3図(C)の0部に示す様に撮影したい
被写体り部とのコントラスト比が異常に大きい場合、撮
像素子にハイライト部でビーム電流不足が生じ、コメツ
トテールと呼ばれる。カメラパンしたときの白い尾ひき
現象や、プルーミング現象を生じ、画像に劣化をきたす
The role of the gate circuit 9 will be explained below. In general, video camera photographers position the subject they want to photograph in the center of the screen. For example, if they want to photograph a person, they position the person's face in the center of the screen as shown in Figure 2. When operating a camera, the contrast ratio between various objects within the imaging screen is often uniform, so there is nothing unnatural about detecting video signals over the entire area of the imaging screen and controlling the iris and AGCf. . However, as shown in Figure 2, when the background of a person, for example the sky is photographed in the upper part of the screen A, or in a backlit situation, or when a light source such as a lamp is photographed directly behind the person indoors, etc.
Photographing situations often occur in which the contrast ratio of the object to be photographed is relatively large. In such shooting situations,
In the conventional control method, the video signal level is controlled so as to optimize the amplitude corresponding to the background pattern (, 4) that is dominant at the video level, as shown in FIG. 3 (α).
As shown in part (B), the object that is originally intended to be photographed becomes dark and dull compared to the rated level, and the photographed image becomes extremely unnatural. Here, a gate circuit 9 is provided to provide a second gate circuit.
If the video signal in the center B of the screen is detected as shown by the broken line in the figure, the video signal will be optimized for the subject to be photographed even under the above situation, as shown in B' in Figure 3<h). Ru. In this case, the high brightness part (A') of the background that exceeds the rated level is processed by the white peak clipping process of the camera signal processing circuit provided nine times after terminal 7.
Clipped by about 50 inches. Clipping high-brightness areas is a normal signal processing method in video cameras.
Since the brightness is originally high (white image), the captured image does not seem very unnatural. Therefore, as described above, the gate circuit 9 is very effective for photographing purposes. However, as shown in section 0 of FIG. 3(C), when the contrast ratio with the subject to be photographed is abnormally large, a beam current shortage occurs in the highlight section of the image sensor, which is called a comet tail. This causes a white trailing phenomenon and a pluming phenomenon when the camera is panned, resulting in image deterioration.

そしてこの画質劣化の程度は、よりノ・イライトになる
程大きい。この対策としてはハイライト部にもビーム電
流を自動的に追従させ、常にビーム電流不足の状態が起
らないように制御するABO(Aatornatic 
beam Optimiztr )と称する回路により
対処することも可能であるが、回路の基模1回路設計は
それほど容易でなく、かなりの配慮と費用を投じなけれ
ばならない。そのため、安価な家庭用ビデオカメラにお
いては採用ができない。また、ABO回路を採用したと
しても実際に存在するコントラスト比から考えて上記現
象を完全に抑圧することは不可能である。
The degree of this image quality deterioration increases as the image becomes brighter and brighter. As a countermeasure to this problem, the beam current automatically follows the highlighted area, and the ABO (Aatornatic
Although it is possible to solve this problem by using a circuit called a beam optimization circuit, it is not so easy to design a basic circuit, and a considerable amount of consideration and expense must be invested. Therefore, it cannot be used in inexpensive home video cameras. Further, even if an ABO circuit is adopted, it is impossible to completely suppress the above phenomenon considering the actually existing contrast ratio.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上記した従来技術の欠点を改善し、さら
にコメツトテール、ブルーミングなどの発生しにくい、
アイリス制御、あるいはAGC制御の制御装置を提供す
ることである。
The purpose of the present invention is to improve the above-mentioned drawbacks of the prior art, and furthermore, to reduce the occurrence of comet tails, blooming, etc.
It is an object of the present invention to provide a control device for iris control or AGC control.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明はコメツトテール、プ
ルーミングが大きくなりすぎて異常な画質劣化を来す程
のハイライト信号に対して所定のレベル(第3図(C)
のVth)を越える信号゛のビー〉値を検出し、この検
出信号を上記従来の検波制御電圧に適量加算したものを
アイリスAGC制御電圧とするものである。すなわち画
面周辺(第2図の破線の外)の異常に大きなノ・イライ
ト信号に対しても所定のレベルVthを越えた絵柄につ
℃・ては、アイリス、AGCの制御動作を多少性なうよ
うにして、第3図@)に示すように0部、D′部処示す
如く、ハイライト部Cに対しては異常に大きなコメット
テーブル、ブルーミングが生じない程度に、撮影したい
画像部D′に対しては黒く(暗く)なりすぎない程度に
映像信号のレベルを適切に制御して良好な撮影直像ヲ得
るものである。この所定のレベルVthは定格レベルよ
り大きい適当な値を設定するが、例えば、定格レベルの
2倍程度に選ぶと都合が良い。
In order to achieve the above object, the present invention provides a predetermined level (Fig. 3(C)
The iris AGC control voltage is obtained by detecting the value of the signal (Vth) that exceeds the above-mentioned conventional detection control voltage. In other words, even with abnormally large light signals around the screen (outside the broken line in Figure 2), the control operations of the iris and AGC are somewhat affected for pictures that exceed a predetermined level Vth. In this way, as shown in Fig. 3 @), the image area D' to be photographed is adjusted to the extent that an abnormally large comet table and blooming do not occur for the highlight area C, as shown in the 0 area and D' area processing. In contrast, the level of the video signal is appropriately controlled to the extent that the image does not become too black (dark), thereby obtaining a good photographed direct image. This predetermined level Vth is set to an appropriate value larger than the rated level, but it is convenient to select it to be about twice the rated level, for example.

〔発明の実施例〕[Embodiments of the invention]

以下本発明による検波回路の構成の一実施例を第4図を
用いて説明する。
An embodiment of the configuration of a detection circuit according to the present invention will be described below with reference to FIG.

本図において第1図と同符号の回路ブロックは同じ機能
、同一動作を示す。第4図においてAGC回路回路用力
端子7に得られた映像信号は後段に続く白ピーククリッ
プ回路、r補正回路など種々のカメラ信号処理回路19
に導ゆれるとともえ、画面の中央部の信号を検出する、
(あるいは画面の中央部外の信号は所定のレベルでクリ
ップするなどの重みづけをしてもよい)ゲート回路9と
、前記所定のレベルをこえる信号のみを検出するハイラ
イト信号検出回路16に印加されて、それぞれの信号が
検出される。ゲート回路9の出力信号はピーク検波回路
10.平均値検波回路11によって、ハイライト信号検
出回路16の出力信号はピーク検波回路17に工って、
それぞれピーク検波、平均値検波され、加算回路12.
18で適切な比率で加算混合され、加算回路20の出力
に制御電圧として出力される。本回路構成によれば、撮
影画面内の種々被写体間のコントラスト比が全画面内に
わたって、tまぼ一様、あるいは映像信号が所定のハイ
ライト検出レベル(Vth )以下となる撮影内容の場
合は、ゲート回路9によって抽出された画面中央部の映
像信号をもとにして得た制御電圧によってのみアイリス
回路、 AGC回路が制御されて、はとんどの撮影状況
下の映像信号レベルが適性化される。ここで、前記した
ように画面の周辺部に異常なハイライトが発生した場合
は、適値処設定しタレヘル(Vth )例えば定格レベ
ルの2倍程度のレベル以上のハイライト信号全検出して
得た電圧によっても所定の割合制御されることになり、
コメツトテール、ブルーミンクを抑圧し最適な画像を得
ることができる。なお上記説明はゲート回路9を設けた
場合であるが、ゲート回路9をはふいても本発明の効果
はある程度得られる。
In this figure, circuit blocks with the same symbols as in FIG. 1 indicate the same functions and operations. In FIG. 4, the video signal obtained at the AGC circuit power terminal 7 is sent to various camera signal processing circuits 19 such as a white peak clip circuit and an r correction circuit following the subsequent stage.
Detects the signal in the center of the screen,
(Alternatively, signals outside the center of the screen may be weighted by clipping them at a predetermined level.) The voltage is applied to the gate circuit 9 and the highlight signal detection circuit 16 that detects only signals exceeding the predetermined level. and the respective signals are detected. The output signal of the gate circuit 9 is sent to the peak detection circuit 10. The average value detection circuit 11 passes the output signal of the highlight signal detection circuit 16 to the peak detection circuit 17.
Peak detection and average value detection are performed, respectively, and addition circuit 12.
18, the signals are added and mixed at an appropriate ratio and output as a control voltage to the output of the adder circuit 20. According to this circuit configuration, when the contrast ratio between various objects in the shooting screen is almost uniform over the entire screen, or when the video signal is below a predetermined highlight detection level (Vth), The iris circuit and AGC circuit are controlled only by the control voltage obtained based on the video signal at the center of the screen extracted by the gate circuit 9, and the video signal level is optimized under most shooting conditions. Ru. Here, if abnormal highlights occur in the periphery of the screen as described above, set an appropriate value for Vth and detect all highlight signals with a level higher than twice the rated level. It is also controlled at a predetermined rate by the applied voltage.
Optimal images can be obtained by suppressing comettail and blooming mink. Although the above explanation deals with the case where the gate circuit 9 is provided, the effects of the present invention can be obtained to some extent even if the gate circuit 9 is omitted.

次に本発明の具体的な一回路例を第5図に示す。本図で
破線で示した9、11,20,10,17゜16の各ブ
ロックが第4図の同符号で示される部分に相当する。ト
ランジスタQ1 、Q2 、Q3 、Q4ダイオードD
1.抵抗R1,’R2によってゲート回路が構成される
。トランジスタQ2のベースに正極性のゲートパルスが
印加され画面の中央部に相当する期間高(H)レベルと
なる。すなわちHレベルノトキトランジスタQ1のベー
スバイアス電圧ERに対してII>E、とムリトランジ
スタQ2カONシて、その結果トランジスタQ3がOF
Fする。
Next, a specific example of a circuit according to the present invention is shown in FIG. Blocks 9, 11, 20, 10, and 17°16 indicated by broken lines in this figure correspond to the parts indicated by the same reference numerals in FIG. Transistors Q1, Q2, Q3, Q4 Diode D
1. A gate circuit is constituted by resistors R1 and 'R2. A positive gate pulse is applied to the base of the transistor Q2, and the transistor Q2 is at a high (H) level for a period corresponding to the center of the screen. In other words, II>E with respect to the base bias voltage ER of the high-level transistor Q1, and the transistor Q2 is turned on, and as a result, the transistor Q3 is turned off.
F.

したがってIレベル期間はトランジスタQ4のベースに
入力された映像信号がそのまま抵抗R2の両端忙発生す
る。次に画面の中央部の外に相当する期間は端子8は低
(L)レベルが印加されるのでE、 ) Lとなりトラ
ンジスタQ1がONシQ2がOFFする。したがって、
レベルシフト用ダイオードD1によってレベルシフトさ
れ1ランジスタQ3のベース九は電圧ERが印加される
。ここで端子8に得られる映像信号のレベルがE、I−
EB(黒レベル)より大きい場合はトランジスタQ4が
OFF (、、それ以上の信号レベルはクリップされて
、ER−EB以下の比較的小振幅レベル信号については
そのままのレベルの映像信号が抵抗R2の両端に発生す
る。すなわちERのレベルの設定によって任意の重みづ
けを行なうことができる。抵抗R2の両端に発生した映
像信号はトランジスタQ5のベースに印加されトランジ
スタQ5抵抗R5、R7、容量C1によって平滑化され
平均値検波電圧が01の両端に発生する。さらに抵抗R
2の両端に発生した映像信号はトランジスタQ6のベー
スにも印加され、トランジスタQ 61容量C2によっ
て、トランジスタQ6のベースに印加される信号のピー
ク値に追従するピーク値検波電圧が容量C2の両端に発
生する。一方、端子7に得られた映像信号は抵抗R5,
R6によって所定のレベルに分割設定された後、トラン
ジスタQ7のベースにも印加されQ7.C2によって同
様にピーク検波される。すなわち抵抗R5,R6の分割
比により、任意に定めるレベル以上のハイライト信号を
検出、検波することができる。そして抵抗R4の設定に
より上記各検波電圧を任意の比率で加算することができ
本発明の特徴を持つ制御電圧を端子21に得ることが出
来る。本実施例がらもわかる様に本発明の要部であるハ
イライト信号検出部はトランジスタQ7.抵抗R5,R
6のみで実現でき極めて簡易である。々お、ゲート回路
9のゲート電圧印加端子8にはパラボラ波形電圧などを
印加して重みづけを行なってもよいことはもちろんであ
る。
Therefore, during the I level period, the video signal input to the base of the transistor Q4 is directly applied to both ends of the resistor R2. Next, during a period corresponding to the outside of the center of the screen, a low (L) level is applied to the terminal 8, so that the transistor Q1 is turned on and the transistor Q2 is turned off. therefore,
The level is shifted by the level shift diode D1, and the voltage ER is applied to the base 9 of the transistor Q3. Here, the level of the video signal obtained at terminal 8 is E, I-
If the signal level is higher than EB (black level), transistor Q4 is turned off. In other words, arbitrary weighting can be performed by setting the level of ER.The video signal generated across the resistor R2 is applied to the base of the transistor Q5, and is smoothed by the transistor Q5, the resistors R5 and R7, and the capacitor C1. and an average detected voltage is generated across the resistor R.
The video signal generated at both ends of the transistor Q6 is also applied to the base of the transistor Q6, and the peak value detection voltage that follows the peak value of the signal applied to the base of the transistor Q6 is applied to both ends of the capacitor C2 by the transistor Q61 capacitor C2. Occur. On the other hand, the video signal obtained at terminal 7 is transmitted through resistor R5.
After being divided and set to a predetermined level by R6, it is also applied to the base of transistor Q7 and Q7. Similarly, peak detection is performed by C2. That is, depending on the division ratio of the resistors R5 and R6, a highlight signal higher than an arbitrarily determined level can be detected. By setting the resistor R4, each of the detected voltages described above can be added at an arbitrary ratio, and a control voltage having the characteristics of the present invention can be obtained at the terminal 21. As can be seen from this embodiment, the highlight signal detection section, which is the main part of the present invention, is the transistor Q7. Resistance R5, R
It can be realized with only 6 and is extremely simple. Of course, weighting may be performed by applying a parabolic waveform voltage to the gate voltage application terminal 8 of the gate circuit 9.

〔発明の効果〕〔Effect of the invention〕

上記説明したように、本発明によれば、背景に大きなハ
イライト信号が発生する様な比較的特殊な撮影状況下で
も所定のレベルを越えたハイライト信号を検出、検波し
た電圧を従来の制御信号に加算するだけで、適量ハイラ
イト部分の信号についても制御できることになり、プル
ーミング、コメツトテールなどの異常な現象が気になら
ない程度に抑圧でき、画面全体の質が大きく向上する。
As explained above, according to the present invention, a highlight signal exceeding a predetermined level is detected even under relatively special shooting conditions where a large highlight signal is generated in the background, and the detected voltage is controlled using conventional control. By simply adding it to the signal, it is possible to control the signal in the highlighted area by an appropriate amount, suppressing abnormal phenomena such as pluming and comet tails to an unnoticeable level, and greatly improving the overall quality of the screen.

また、本発明の採用によりABO回路の削除、あるいは
ABO回路の能力を軽減してもよいなど経済効果がある
ととも蹟、ABO回路の併用によれば、さらに大きな画
質向上効果を有することができる。
In addition, by adopting the present invention, there are economical effects such as eliminating the ABO circuit or reducing the capacity of the ABO circuit, and if the ABO circuit is used in combination, an even greater effect of improving image quality can be obtained. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のビデオカメラのアイリス。 AGC制御系を示すブロック図、第2図は撮影画像の一
例を示す説明図、第3図はアイリス制御。 AGC制御の動作を説明するための波形図、第4図は本
発明によるアイリス、 AGC検波回路の一実施例を示
すブロック図、第5図は本発明の一実施例の要部の一具
体回路を示す回路図である。 1:レンズ系 2ニアイリス機構 6:撮像素子 4:プリアンプ 5:信号処理回路 6:AGC回路 8ニゲ一ト信号印加端子 9:ゲート回路 10:ピーク値検波回路 11:平均値検波回路 12:加算回路 16:増幅回路 14 : A’GC、アイリス制御電圧切換回路15ニ
アイリス駆動回路 16:ハイライト信号検出回路 17:ピーク検波回路 20:加算回路 19:カメラ信号処理回路 Jbl 図 11 第 2図 Δ 第 3図
Figure 1 shows the iris of a conventional video camera. A block diagram showing the AGC control system, FIG. 2 is an explanatory diagram showing an example of a photographed image, and FIG. 3 shows iris control. A waveform diagram for explaining the operation of AGC control, FIG. 4 is a block diagram showing an embodiment of the iris and AGC detection circuit according to the present invention, and FIG. 5 is a specific circuit of a main part of an embodiment of the present invention. FIG. 1: Lens system 2 Near iris mechanism 6: Imaging device 4: Preamplifier 5: Signal processing circuit 6: AGC circuit 8 Negative signal application terminal 9: Gate circuit 10: Peak value detection circuit 11: Average value detection circuit 12: Addition circuit 16: Amplification circuit 14: A'GC, iris control voltage switching circuit 15 near Iris drive circuit 16: Highlight signal detection circuit 17: Peak detection circuit 20: Addition circuit 19: Camera signal processing circuit Jbl Fig. 11 Fig. 2 Δ 3rd figure

Claims (1)

【特許請求の範囲】 1、 映像信号の大きさに応じて、光学系のアイリス、
あるいは映像信号処理回路の利得を自動的に制御する手
段を有するビデオカメラにおいて、映像信号のレベルを
検出する第1の検出手段と、上記映像信号の所定レベル
を越えた高輝度成分を検出する第2の検出手段とこの二
つの手段によって得た信号を加算してアイリスおよび処
理回路の利得の少なくとも一方を制御する。c5にした
ことを特徴とするビデオカメラ用制御回路。 2、特許請求の範囲第1項記載のビデオカメラ用制御回
路において、上記映像信号のレベルを検出する第1の検
出手段は、撮像画面のほぼ中央部の映像信号を検出する
ようにしたことを特徴とするビデオカメラ用制御回路。
[Claims] 1. Depending on the size of the video signal, the iris of the optical system;
Alternatively, in a video camera having means for automatically controlling the gain of a video signal processing circuit, the first detection means detects the level of the video signal, and the first detection means detects a high brightness component exceeding a predetermined level of the video signal. The second detection means and the signals obtained by these two means are added to control at least one of the iris and the gain of the processing circuit. A control circuit for a video camera characterized by using C5. 2. In the video camera control circuit according to claim 1, the first detection means for detecting the level of the video signal detects the video signal at approximately the center of the imaging screen. Features a video camera control circuit.
JP58135860A 1983-07-27 1983-07-27 Control circuit for video camera Granted JPS6028382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58135860A JPS6028382A (en) 1983-07-27 1983-07-27 Control circuit for video camera

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58135860A JPS6028382A (en) 1983-07-27 1983-07-27 Control circuit for video camera

Publications (2)

Publication Number Publication Date
JPS6028382A true JPS6028382A (en) 1985-02-13
JPH0584106B2 JPH0584106B2 (en) 1993-11-30

Family

ID=15161453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58135860A Granted JPS6028382A (en) 1983-07-27 1983-07-27 Control circuit for video camera

Country Status (1)

Country Link
JP (1) JPS6028382A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214584A (en) * 1985-07-12 1987-01-23 Canon Inc Image pickup device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54110019A (en) * 1978-02-16 1979-08-29 Hiroyuki Takahashi Air punch
JPS56119820A (en) * 1980-02-27 1981-09-19 Canon Inc Photometric system
JPS5897969A (en) * 1981-12-05 1983-06-10 Sony Corp Control signal generating circuit of video camera

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54110019A (en) * 1978-02-16 1979-08-29 Hiroyuki Takahashi Air punch
JPS56119820A (en) * 1980-02-27 1981-09-19 Canon Inc Photometric system
JPS5897969A (en) * 1981-12-05 1983-06-10 Sony Corp Control signal generating circuit of video camera

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6214584A (en) * 1985-07-12 1987-01-23 Canon Inc Image pickup device

Also Published As

Publication number Publication date
JPH0584106B2 (en) 1993-11-30

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