JPS6028233A - Monitor device for etching - Google Patents

Monitor device for etching

Info

Publication number
JPS6028233A
JPS6028233A JP13582883A JP13582883A JPS6028233A JP S6028233 A JPS6028233 A JP S6028233A JP 13582883 A JP13582883 A JP 13582883A JP 13582883 A JP13582883 A JP 13582883A JP S6028233 A JPS6028233 A JP S6028233A
Authority
JP
Japan
Prior art keywords
wafer
etching
image sensor
window glass
image signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13582883A
Other languages
Japanese (ja)
Inventor
Takashi Kamimura
隆 上村
Teru Fujii
藤井 輝
Toru Otsubo
徹 大坪
Minoru Noguchi
稔 野口
Susumu Aiuchi
進 相内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13582883A priority Critical patent/JPS6028233A/en
Publication of JPS6028233A publication Critical patent/JPS6028233A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve yield by identifying the states of reflection of each point on a wafer changing as an etching progresses as picture signals by an image sensor, scanning each point on the wafer in succession and monitoring the state of etching in the wafer from the changes of the picture signals. CONSTITUTION:Upper and lower electrodes 3 and 2 are arranged in an etching chamber 1, both side walls thereof each have window glass 4a, 4b, and voltage from a high-frequency power supply 5 is applied to these electrodes. A wafer 6 is placed on the electrode 2, CCl4 gas is introduced into the chamber 1, and the surface of the wafer 6 is etched. Beams from a laser 7 are projected to the surface of the wafer 6 through a mirror 9 controlled by a lens 8 and a drive 10 and the window glass 4a at that time, and reflected beams from the surface of the wafer are projected to a monitor device 100 through the window glass 4b, a deflection foucs optical system 11 and an image sensor 12. Accordingly, the differences of etching at the initial stage and in mid course are compared with each other.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はドライエツチングに係シ、特にウェハ内のエツ
チングの進行状況をインプロセスでモニタ(監視)する
ことを可能にした、エツチングのモニタ装置に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to dry etching, and more particularly to an etching monitoring device that enables in-process monitoring of the progress of etching within a wafer. It is something.

〔発明の背景〕[Background of the invention]

従来エツチングのメカニズム、と夛わけ放電中のプラズ
マの分布状態を定量的に把握することは難しく、末だに
解明されていない点が多い。
Conventionally, it has been difficult to quantitatively understand the etching mechanism and the distribution of plasma during multiple discharges, and there are still many points that have not been elucidated.

エツチング中のウェノ・内均−性分布測定が上・記問題
課題究明の一つの解を与えるものと考え、検討してきた
We have been considering the measurement of internal uniformity distribution during etching as providing one solution to the investigation of the above-mentioned problems.

エツチングによるウェノ・内均−性分布の測定はエツチ
ング後、ウェノ・をエツチング室の外に取シ出し、ホト
レジスト除去処理をした後、ウェハ(7)エツチングさ
れた場所の段差を干渉顕微鏡で測定していた。この方法
は正確にしかもウェハ内の任意の位置について詳細に測
定出来るが、エツチング中のプラズマの分布状態に対応
するウェノ・上の各点のエツチング進行状況、すなわち
ウェノ・内の均一性分布測定をインプロセスで(エツチ
ング進行過程の中で)モニタすることが出来なかった。
To measure the internal uniformity distribution of the wafer by etching, after etching, take the wafer out of the etching chamber, remove the photoresist, and then measure the level difference in the etched area of the wafer (7) using an interference microscope. was. This method can accurately and in detail measure any position within the wafer, but it also measures the etching progress at each point on the wafer, which corresponds to the distribution of plasma during etching, that is, the uniformity distribution within the wafer. It was not possible to monitor it in-process (during the etching process).

従ってエツチング中のウェハ内のエツチング進行状況の
モニタリングをインプロセスでしかも簡便な方法で行い
たい要求が出現した。
Therefore, a demand has arisen for monitoring the etching progress within a wafer during etching in-process and in a simple manner.

これに対し、エツチング中のウェノ・を直接光学的手段
でモニタしてbく方法が有望であシ、網目構造のエツチ
ング上部電極を通して目視観察する方法や、エツチング
上部電極の中央部を〈シぬいて真上からテレビカメラで
エツチング中のウェハを観察することを検討したが、エ
ツチング上部電極に構造上の変化を追加するとプラズマ
の放電状況が変わシ、均一に一プラズマが立たなかった
り、またエツチングガスの流れ方が均一でなかったシし
てエツチングのウェハ内均−性分布が悪くなる欠点が出
現した。またエツチング中のウェハ表面を光学的に観察
する際に、ウェハに照射する照明光とウェノ・表面から
の反射光とがプラズマの放電光によシ、散乱され影響を
受けることが実験で判明したので、プラズマの放電光の
影響を受けない光源、照明系の選定が必要となってきた
On the other hand, there are promising methods in which the etching process is directly monitored by optical means. We considered observing the wafer during etching with a TV camera from directly above, but adding structural changes to the upper etching electrode would change the plasma discharge situation, resulting in problems such as the plasma not being generated evenly or the wafer being etched again. Since the gas flow was not uniform, a drawback appeared in that the etching uniformity distribution within the wafer deteriorated. Furthermore, when optically observing the wafer surface during etching, it was found through experiments that the illumination light irradiating the wafer and the light reflected from the wafer surface were scattered and affected by plasma discharge light. Therefore, it has become necessary to select a light source and illumination system that are not affected by plasma discharge light.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した従来技術の欠点をなくし、エ
ツチング中、ウェハ上の各点で時々刻々変化するエツチ
ング進行状況を映像信号でとらえ、ウェハ内のエツチン
グ均一性分布をインプロセスモニタすることが出来るよ
うになしたエツチングモニタ装置を提供するにある。
An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to monitor the etching uniformity distribution within the wafer in-process by capturing the etching progress status that changes from time to time at each point on the wafer using video signals during etching. To provide an etching monitor device capable of performing the following steps.

〔発明の概要〕[Summary of the invention]

本発明は上記した目的達成のため、エツチングの進行に
ともなって変化するウェノ・上の各点の反射状態をイメ
ージセンサで画像信号としてとらえ、必要によってはエ
ツチング中ウェハを回転させることによシ、ウェハ上の
各点を遂次走査し、画像信号の変化からウェハ内のエツ
チング均一性分布の様子をエツチング進行過程でインプ
ロセスモニタしようというものである。
In order to achieve the above-mentioned object, the present invention uses an image sensor to capture the reflection state of each point on the wafer, which changes as the etching progresses, as an image signal, and if necessary, rotates the wafer during etching. Each point on the wafer is sequentially scanned, and the etching uniformity distribution within the wafer is monitored in-process during the etching process from changes in image signals.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1図ないし第5図によ多説
明する。第1図は本発明の実施例による構成図である。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. FIG. 1 is a configuration diagram according to an embodiment of the present invention.

1はエツチング室、2は下部電極、6は上部電極、4g
、4bは窓ガラス5は高周波電源、6はウェノ・、7は
レーザー。
1 is the etching chamber, 2 is the lower electrode, 6 is the upper electrode, 4g
, 4b is a window glass 5 is a high frequency power supply, 6 is a weno, 7 is a laser.

8はレンズ、9はミラー、10はミラー駆動装置、11
は偏向焦点光学系、12はイメージセンサ、100はモ
ニタ装置である。ここで偏向焦点光学系11はウェハ6
の表面パターン像をイメージセンサ12に結像させる光
学系である。
8 is a lens, 9 is a mirror, 10 is a mirror drive device, 11
12 is an image sensor, and 100 is a monitor device. Here, the deflection focusing optical system 11 is connected to the wafer 6.
This is an optical system that forms a surface pattern image on the image sensor 12.

第2図は下部電極2の上に任意の向きに置かれたウェハ
6を真上から見た平面図であl)、6aはダイシング用
ストライプライン、6bは回路パターン部分また6Cは
ウェノ1の中心を通りレーザー7よシ照射されるレーザ
ー光の走査方向を示す。また81〜S12はレーザー照
射走査線6Cとストライプライン6aとの交点を示す。
FIG. 2 is a plan view of the wafer 6 placed on the lower electrode 2 in an arbitrary direction (l), in which 6a is the stripe line for dicing, 6b is the circuit pattern part, and 6C is the wafer 1. It shows the scanning direction of the laser beam that passes through the center and is irradiated by the laser 7. Further, 81 to S12 indicate intersections between the laser irradiation scanning line 6C and the stripe line 6a.

第3図はウェハ6の断面の一部を示す図である。51は
基板材SLであり、52は下地材8 ichであシ15
3は被エツチング材料Mであシ、54はホトレジスト膜
である。ホトレジスト膜54がマスクとな、9、A15
3をエツチングする。Aはエツチング開始前の状態を表
わし、Bはエツチングの途中、CはM53のエツチング
が完了し、下地材Sigh52ヲエッチングしている状
態である。
FIG. 3 is a diagram showing a part of a cross section of the wafer 6. As shown in FIG. 51 is the substrate material SL, and 52 is the base material 8 ich.
3 is a material M to be etched, and 54 is a photoresist film. The photoresist film 54 is a mask, 9, A15
Etch 3. A shows the state before the start of etching, B shows the state in the middle of etching, and C shows the state where the etching of M53 has been completed and the base material Sigh52 is being etched.

第4図はモニタ装置100の内部構成図を示しておシ、
14はA/D変換器、13はイメージセンサ12を駆動
し、A/D変換器14の変換開始のタイミングを与える
タイミング回路、15は記憶回路、16はA/D変換器
14と逆の特性を持つD/A変換器、17は信号表示装
置である。
FIG. 4 shows an internal configuration diagram of the monitor device 100.
14 is an A/D converter, 13 is a timing circuit that drives the image sensor 12 and gives timing for starting conversion of the A/D converter 14, 15 is a memory circuit, and 16 is a characteristic opposite to that of the A/D converter 14. 17 is a signal display device.

第5図は、エツチングの進行に伴って変化するイメージ
センサ12から出力される映像信号を示したものであυ
、a + b r Cは第6図におけるエツチング過程
A、B、Cにそれぞれ対応する。
FIG. 5 shows the video signal output from the image sensor 12 that changes as etching progresses.
, a + b r C correspond to etching processes A, B, and C in FIG. 6, respectively.

次に第1図ないし第5図によって本発明の動作を詳細に
説明する。
Next, the operation of the present invention will be explained in detail with reference to FIGS. 1 to 5.

エツチング室1は、図示されていないガス供給装置から
エツチングガス(例えばCC’4 t 5Dcc。
The etching chamber 1 is supplied with an etching gas (for example, CC'4 t 5Dcc) from a gas supply device (not shown).

/min )が供給され、図示されていない排気装置で
一定の圧力(例えば9pa )に保たれて込る。
/min) and maintained at a constant pressure (for example, 9 pa) by an exhaust device (not shown).

高周波電源5より例えば15−56MI(z * 40
 ow比出力高周波電極を下部電極2と上部電極3との
間に印加するとプラズマ放電を生じ、ウェハ6の表面が
エツチングされていく。これがドライエツチングであり
公知の事実である。
For example, 15-56 MI (z * 40
When the OW specific output high frequency electrode is applied between the lower electrode 2 and the upper electrode 3, plasma discharge is generated and the surface of the wafer 6 is etched. This is dry etching and is a well-known fact.

上記エツチングと並行して、エツチング室1の外に設け
たレーザー7よシ発せられたレーザー光ヲレンズ8を通
してミラー9で反射させ、エツチング室1にとシつけた
窓ガラス4aを通してエツチング中のウェハ6の表面の
中心を照射する。この除ミラー駆動装置10によりミラ
ー9を所要の周期でふらせ、第2図の60のようにレー
ザー光をウェハ表面でウェハ中心を通る直線上を一次元
的に走査する。
In parallel with the above-mentioned etching, a laser beam emitted from a laser 7 installed outside the etching chamber 1 is reflected by a mirror 9 through a lens 8, and the wafer 6 being etched is passed through a window glass 4a attached to the etching chamber 1. irradiate the center of the surface. The mirror removing drive device 10 causes the mirror 9 to swing at a required period, and the laser beam is scanned one-dimensionally on the wafer surface on a straight line passing through the center of the wafer, as shown at 60 in FIG.

ウェハ6の表面に照射されたレーザー光の反射光は、前
述と逆の経路で窓ガラス4もを通過し、偏向焦点光学系
11全通してイメージセンサ12に到達する。偏向焦点
光学系11°は焦点距離の違う像を結像させる機能を持
ち、ウェハ6の表面パターン像をイメージセンサ12に
結像させる。
The reflected light of the laser beam irradiated onto the surface of the wafer 6 also passes through the window glass 4 in the opposite path to that described above, passes through the entire deflection and focus optical system 11, and reaches the image sensor 12. The deflection focusing optical system 11° has a function of forming images having different focal lengths, and forms an image of the surface pattern of the wafer 6 on the image sensor 12.

イメージセンサ12は、タイミング回路13からのクロ
ック信号を受け、前記レーザー光の走査で得られるエツ
チング中のウェノ・6の表面パターンの画像信号(第5
図a r b + e )を信号表示装置17に出力す
る。
The image sensor 12 receives a clock signal from the timing circuit 13 and receives an image signal (fifth
a r b + e) is output to the signal display device 17.

エツチングは進行に伴い、ウェノ・表面は第3図A−+
B−)Cのようにホトレジスト54でマスクされてI/
−1ない部分のAI+53が工、ツチングされていく。
As the etching progresses, the surface of the wafer is shown in Figure 3 A-+.
B-) I/I is masked with photoresist 54 as shown in C.
-AI +53 of the part without 1 is being worked and added.

ウェハ6上のダイシング用ストライプライン6aは、ホ
トレジスト膜54でマスクされていない部分であるため
、エツチング過程で被エツチング材料AJ53がエツチ
ングされ、下地材SiOが露出し、表面の反射率の変化
が著しい。
Since the stripe line 6a for dicing on the wafer 6 is a portion not masked by the photoresist film 54, the material to be etched AJ53 is etched during the etching process, the base material SiO is exposed, and the reflectance of the surface changes significantly. .

これに対しストライプライン6aで囲まれた回路ハター
ン部分6bはホトレジスト膜54が40係程度の割合で
マスクされているので、エツチングしても表面の反射率
変化は少ない。
On the other hand, since the circuit pattern portion 6b surrounded by the stripe line 6a is masked with the photoresist film 54 at a ratio of about 40, even if it is etched, there is little change in the reflectance of the surface.

従ってウェハ6上のレーザー照射走査線6Cとウェハの
ストライプライン6aとの交点51eS 2 +・・・
S12においては、エツチング進行第6図A−)B−+
Cに伴って、その画像信号は第5図a→l) −+ C
のように変化し、回路パターン部分6bは、エツチング
進行状況のウェノ・上の場所の違いによシ第5図a−+
b−+Cのようにレベル変動する。
Therefore, the intersection point 51eS 2 + between the laser irradiation scanning line 6C on the wafer 6 and the wafer stripe line 6a...
In S12, the etching progress in Fig. 6 A-)B-+
Along with C, the image signal is as shown in Fig. 5 a→l) −+ C
The circuit pattern portion 6b changes as shown in Fig. 5a-+ depending on the location on the etching progress.
The level fluctuates like b-+C.

一方、前述画像信号のエツチング過程での変化上前後す
るが、エツチング放電開始時点でのウェハ6の表面パタ
ーンの画像信号をタイミング回路13からのタイミング
信号のタイミングでA/D変換器14でディジタル値に
変換し、A/D変換器からの変換終了信号のタイミング
で前記ディジタル値を記憶回路15に入力し、記憶する
。更に、このディジタル値をA/D変換器14と逆の特
性をもつD/A変換器16で画像信号にもどし信号表示
装置17に、エツチング放電開始時点でのウェハ6の表
面パターンの画像信号(第5図aの波形)を出力し続け
る。
On the other hand, the image signal of the surface pattern of the wafer 6 at the time of starting the etching discharge is converted into a digital value by the A/D converter 14 at the timing of the timing signal from the timing circuit 13, although it varies depending on the change in the image signal during the etching process. The digital value is input to the storage circuit 15 and stored at the timing of the conversion end signal from the A/D converter. Furthermore, this digital value is returned to an image signal by a D/A converter 16 having characteristics opposite to those of the A/D converter 14, and a signal display device 17 displays an image signal ( The waveform shown in FIG. 5a) continues to be output.

上記2つの画像信号すなわち、エツチング放電開始時点
でのウェハ表面の画像信号(第5図a)と、エツチング
過程での画像信号(第5図a r b + cと変化し
ていく)を常時信号表示装置17に表示して観察してい
くことによシ、エツチングの進行状況をインプロセスで
モニタすることができる。
The above two image signals, namely, the image signal of the wafer surface at the start of the etching discharge (Fig. 5 a) and the image signal during the etching process (which changes as shown in Fig. 5 a r b + c) are constantly output as signals. By displaying and observing on the display device 17, the progress of etching can be monitored in-process.

たとえば、第5図Cのエツチング時点では、ウェハ中央
部の波高値が、ウェハ周辺部の波高値よシ低いのでエツ
チングの進行が周辺の方が速−というようにウェハ内の
エツチング進行状況をエツチングしながら把握していく
ことができる。
For example, at the time of etching in FIG. 5C, the peak value at the center of the wafer is lower than the peak value at the periphery of the wafer, so etching progresses faster at the periphery. You can understand it while doing so.

今はウェハ上の1走査分の画像信号のみ議論したが、必
要に応じてウェハを回転させ、ウェハ上の照射走査線6
cを動かし、ウェハの回転き同期して画像信号をとシ出
せは、ウェハ上の任意の位置のエツチング進行状況を得
ることができ、ウェハ内の均一性分布をインプロセスで
モニタ可能となる。
Although we have only discussed image signals for one scan on the wafer, if necessary, the wafer can be rotated and the irradiation scan line on the wafer can be
By moving c and outputting an image signal in synchronization with the rotation of the wafer, it is possible to obtain the progress of etching at any position on the wafer, making it possible to monitor the uniformity distribution within the wafer in-process.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれはエツチング中のウ
ェハ内のエツチング進行状況をインプロセスでモニタす
ることができるので、エツチングの均一性の分布をエツ
チング中に測定することか可能となシ、放電中のプラズ
マ分布状態を把握できるという効果がある。
As explained above, according to the present invention, the progress of etching within a wafer during etching can be monitored in-process, so it is possible to measure the distribution of etching uniformity during etching. This has the effect of being able to grasp the plasma distribution state during discharge.

放電中のプラズマ分布状態がわかれば、エツチングガス
流量、エツチング圧力、高周波電源の出力を制御してよ
り安定寿エツチング状態を作シ出すことが可能となシ、
ウェハの製品歩留向上へ多大の効果を生み出す。
If the plasma distribution state during discharge is known, it will be possible to create a more stable etching life state by controlling the etching gas flow rate, etching pressure, and output of the high-frequency power supply.
This has a significant effect on improving wafer product yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による構成図、第2図はウェ
ハの平面図と走査方向を示す形状図第3図はウェハの断
面の一部を示す図でエツチング進行に伴う変化の説明図
、第4図はモニタ装置の内部構成図、第5図はエツチン
グの進行に伴うウェハ表面のパターン像の変化を表わす
画像信号の波形図である。 1・・パエッチング室、6・・・ウェハ、7・・・レー
ザー、 9・・・ミラー、10・・・ミラー駆動装置、
11・・・偏向焦点光学系、12・・・イメージセンサ
、13・・・タイミング回路、14・・・A/D変換器
、 15・・・記憶回路、16・・・D/A変換器、 
17・・・信号表示装置。 代理人弁理士 高 橋 明 夫S 第 1図 」 第2図 第3図 (E3) (C)
FIG. 1 is a configuration diagram according to an embodiment of the present invention. FIG. 2 is a plan view of the wafer and its shape showing the scanning direction. FIG. 3 is a diagram showing a part of the cross section of the wafer, which explains changes as etching progresses. 4 is an internal configuration diagram of the monitor device, and FIG. 5 is a waveform diagram of an image signal representing changes in the pattern image on the wafer surface as etching progresses. 1...Paper etching chamber, 6...Wafer, 7...Laser, 9...Mirror, 10...Mirror drive device,
DESCRIPTION OF SYMBOLS 11... Deflection focus optical system, 12... Image sensor, 13... Timing circuit, 14... A/D converter, 15... Memory circuit, 16... D/A converter,
17...Signal display device. Representative Patent Attorney Akio Takahashi S Figure 1 Figure 2 Figure 3 (E3) (C)

Claims (1)

【特許請求の範囲】[Claims] 1、 エツチング中のウェハを所定の方向よシ入射させ
た光で一次元に走査し続け、入射方向と反対の方向に得
られる反射光を偏向焦点光学系を通してイメージセンサ
に導き、得られるウニ・・表面パターンの画像信号を表
示する装置において、エツチング放電開始時のウェハ表
面パターンの画像信号を常時出力する一方、エツチング
中、エツチング進行状況に対応するウェハ表面パターン
の画像信号をも出力し、前記2つの画像信号を絶えず比
較できるように表示することを特徴とするエツチングの
モニタ装置。
1. The wafer being etched is continuously scanned one-dimensionally with light incident in a predetermined direction, and the reflected light obtained in the opposite direction to the incident direction is guided to an image sensor through a deflection focusing optical system. - In a device that displays an image signal of a surface pattern, it constantly outputs an image signal of the wafer surface pattern at the start of etching discharge, and also outputs an image signal of the wafer surface pattern corresponding to the etching progress status during etching, and An etching monitor device characterized by displaying two image signals so that they can be constantly compared.
JP13582883A 1983-07-27 1983-07-27 Monitor device for etching Pending JPS6028233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13582883A JPS6028233A (en) 1983-07-27 1983-07-27 Monitor device for etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13582883A JPS6028233A (en) 1983-07-27 1983-07-27 Monitor device for etching

Publications (1)

Publication Number Publication Date
JPS6028233A true JPS6028233A (en) 1985-02-13

Family

ID=15160734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13582883A Pending JPS6028233A (en) 1983-07-27 1983-07-27 Monitor device for etching

Country Status (1)

Country Link
JP (1) JPS6028233A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283933A (en) * 1988-05-11 1989-11-15 Tokyo Electron Ltd Etching apparatus
JPH01283934A (en) * 1988-05-11 1989-11-15 Tokyo Electron Ltd Etching apparatus
JP2018014538A (en) * 2011-11-14 2018-01-25 エスピーティーエス テクノロジーズ リミティド Etching device and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283933A (en) * 1988-05-11 1989-11-15 Tokyo Electron Ltd Etching apparatus
JPH01283934A (en) * 1988-05-11 1989-11-15 Tokyo Electron Ltd Etching apparatus
JP2018014538A (en) * 2011-11-14 2018-01-25 エスピーティーエス テクノロジーズ リミティド Etching device and method

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