JPS602815B2 - clock regeneration circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention enables high-speed and high-speed transmission not only in stable propagation conditions, but also in poor propagation environments where the reception level fluctuates drastically due to fading, etc., such as multiple access systems in satellite communications, mobile communications, etc. The present invention relates to a clock recovery circuit that is efficient and suitable for LSI implementation of a demodulator used in highly reliable digital communication systems that require accurate clock synchronization.

In the receiving device of a digital communication system, the receiving side reproduction clock used to identify and judge the output signal of the detection circuit at the best S/N point and reproduce the data is a single tuned circuit or a phase synchronized circuit (PMse LMkedL skin p: PLL). It is customary to extract and reproduce the clock component by removing unnecessary components as much as possible from the output signal of the detection circuit, etc., by means such as the above.

By the way, when it is necessary to receive signals from multiple partner stations, such as in a multiple access system, there are two problems: i) the distances to each partner station are different; ii) the distance changes during communication in mobile communications, etc. Since the partner station changes with each call, the clock phase of the received signal from each station is not constant, and it is necessary for the receiving side to generate a reproduced clock by following changes in the clock phase of each station.

In addition, diversity reception methods such as antenna switching are often adopted to improve the reliability of communication, but in such cases, multiple reception signals with low correlation are selected and combined, so reception is performed frequently. It is necessary for the clock recovery circuit to follow the changes in the clock phase that occur. However,
In slave clock regeneration circuits such as single tuned circuits and PLL,
The frequency bandwidth is narrowed in order to remove unnecessary components such as thermal noise contained in the clock component of the received signal and reproduce a high S/N clock, but as is well known, the transient response to band width and phase changes is Since time is inversely proportional, if the bandwidth is narrowed, the transient response time will increase, leading to an increase in dead time in demodulation data and a decrease in line efficiency.

In addition, a method has been proposed in which the average clock timing is detected and a recovered clock is generated for the TDMA method, but even in this case, synchronization may occur due to reception level fluctuations such as fading, and "reception input When the clock is switched, there are problems such as requiring a response time equal to the phase average time.In other words, conventional clock regeneration circuits have a long transient response time, making it difficult to improve line efficiency in multiple access systems and diversity reception systems. However, in order to eliminate these drawbacks, the present invention has the following drawbacks: that it is difficult to increase the clock timing information, and that there is no countermeasure against loss of synchronization during fading. To provide two clocks: output a high S/N regenerated clock according to the timing information obtained from the averaging interval that gives correct clock timing according to the timing distribution and reception level information;
During synchronization, every time a clock timing sample is given, it operates to have a narrower band wave characteristic, resulting in extremely fast synchronization pull-in characteristics and reliable high S/N clock regeneration with little synchronization loss. This will be explained in detail below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which 1 is a signal input terminal, 2 is a reproduced clock output terminal, 3 is an oscillator, 4 is a frequency divider, 5 is a phase difference averaging circuit, 6 is a change detection circuit, 7 is an average interval judgment circuit, 8 is a write judgment circuit, 9 is a memory circuit, 1 is a phase shift circuit, turtle 1 is a control circuit, a is an input signal, and b is a pulse indicating a logic change. signal, c is the reception level signal, d is the oscillator output, e is the first phase difference display signal, f is the second phase difference display signal, g is the reference signal with a frequency approximately equal to the clock frequency of the signal, and h is the average The phase difference, i is the output signal of the storage circuit 9, j is the reproduced clock output, k is the phase difference average section selection signal, 1 is the write inhibit signal, m is the storage circuit control signal, and n is the phase difference average time instruction signal. The operation of this embodiment is as follows.

The oscillator 3 generates a signal having a frequency that is a fixed number multiple of the clock frequency of the received signal, and this signal is applied to the frequency divider 4 and the control circuit 1.

Here, the value of a certain number of times is determined based on the phase accuracy of the reproduced clock required for each system, and the larger the value, the better the accuracy, but the larger the circuit. Generally, if this is chosen to be 2n times (n is a natural number), the circuit configuration will be simplified. The frequency divider No. 4 divides the oscillator output signal d into a fixed number and outputs a reference signal g having a frequency approximately equal to the clock frequency of the received signal to the phase shift circuit 10, and also divides the oscillator output signal d into a fixed number. and a second phase difference display signal f indicating a phase difference that is different from the first phase difference display signal e by a certain phase difference to the phase difference averaging circuit 5. Output.

For example, if a constant number is selected as 2n, the frequency divider 4 can be easily configured with a 2n counter having n-bit parallel outputs.
By using two phase difference display signals in this way,
of the received signal in two different sections. The phase difference between the reference signal and the reference signal can be accumulated. For example, if the intervals are different from each other by 180 degrees, "just invert the most significant bit of the first phase difference display signal, that is, N
A second signal can be created with one OT gate. The change detection circuit extracts the logic change timing corresponding to the clock component of the received signal input a, and outputs it as a pulse signal b to the phase difference averaging circuit 5, the average interval determination circuit 7, and the write determination circuit 8.

The phase difference averaging circuit 5 samples each phase difference display signal e, f according to this timing, and calculates the average value as an average phase difference h.
Output sequentially as . The average interval determination circuit 7 determines whether the sampled first phase difference display signal e is within a specified interval near oo and 360o with respect to the reference signal g, and calculates the number of phase difference samples within this interval. Count. Then, the counted number of samples is compared with the total number of samples, and if the ratio is greater than a certain value, the average phase difference obtained using the second phase difference display signal f is determined as the correct average phase difference. The phase difference averaging circuit 5 is instructed to select by the phase difference averaging section selection signal k. Conversely, if the ratio value is less than a certain value, an instruction is given to select the average phase difference determined using the first phase difference display signal e. The reason why the average phase difference between the clock components of the reference signal and the received signal can be accurately determined by this method will be described later with reference to FIG. The memory circuit 9 receives memory circuit control signals m such as address signals, write signals, and read signals given from the control circuit 11.
The average phase difference is stored and output according to the following.

The phase shift circuit 10 shifts the phase of the reference signal g by the memory output i of the memory circuit 9, and outputs a reproduced clock synchronized with the clock component of the received signal. The control circuit 11 starts, ends, and resets the operation of the phase difference averaging circuit 5, the average interval judgment circuit 7, and the write judgment circuit 8 according to the predetermined phase difference averaging time, the number of multiple connection stations, etc. from the output of the oscillator 3. , address, write, read signals, etc. to the memory circuit 9 are generated and output. The control circuit 11 also bypasses the storage circuit at the time of synchronization pull-in, updates and reproduces the output signal i indicating the average phase difference when one phase difference sample is input. The phase of block i is also updated at the same time. The manner in which clock synchronization is performed at high speed using this method will be described later with reference to FIG. If the reception level is stable through the above operations, the reproduced clock can be output correctly. On the other hand, the received level fluctuates greatly due to fading, etc., and the correct demodulated signal is not always applied to this circuit in many cases. Therefore, in the circuit of the present invention, as a countermeasure, when the reception level signal c is given from the receiver, it is compared with the parent level in the write judgment circuit 8, and when the reception level is lower than the specified level, the obtained average phase difference is A write inhibit signal 1 is output to the storage circuit 9 so that the data is not stored. At this time, the average phase difference obtained at one or more previous phase difference averaging times is held in the storage circuit 9, so that synchronization due to fading does not occur. In reality, the clock timing fluctuates much more slowly than the fading pitch, so the above method can sufficiently avoid out-of-synchronization. Further, even when no reception level is given, a write inhibit signal is generated using the write determination circuit 8.
The write determination circuit 8 equally divides the phase difference from oo to 360o into appropriate sections, counts the number of phase difference samples that have entered each section, calculates the phase difference distribution, and determines the phase difference distribution if the reception level has decreased. The write inhibit signal 1 is generated by utilizing the fact that the phase difference distribution is close to a uniform distribution. As described above, this configuration example can correctly output a recovered clock not only in a stable propagation state but also in a poor propagation state such as fading.

In addition, even in a system that uses burst signals such as TDMA, clock synchronization can be established from the first burst, and the clock timing from each station is stored in the storage circuit 9 according to the address signal from the control circuit 11, and subsequent bursts are stored in the storage circuit 9. When receiving, a recovered clock is output using the clock timing obtained from one or more previous bursts.

Next, the synchronization pull-in characteristic of this circuit will be explained using FIG.

In the figure, the dashed-dotted line indicates the phase of the clock component of the received signal (the true phase after removing the influence of noise, etc.), and the thin solid line indicates the phase of the reproduced clock. However, the phase of the signal clock is quantized to the same degree of accuracy as the reproduced clock for comparison.
At time t=0, clock synchronization is not applied, but since the phase difference samples are averaged each time they are input, a narrow-band castle wave effect appears over time, removing disturbance components such as noise, and changing the signal clock. You can see how the synchronization is achieved. Assuming that the phase difference average time is Δt, the reproduced clock is output at the average clock timing obtained between 0 and Δt in the time period Δt to 2Δt. In the figure, the signal clock phase changes frequently, but in reality the change is gradual, so there is almost no phase error in the reproduced clock. In multiple access systems and switching diversity, clock synchronization is performed as shown in the figure after connection or switching. Furthermore, since the TDMA system uses a burst signal having a length of about Δt, it is sufficient to store the average clock timing until the next burst. Next, the received signal shown in FIG.

The reason why the average phase difference can be correctly determined in this configuration example will be explained using the distribution of the phase difference between the optical component and the reference signal. In Fig. 3, a is the phase difference distribution in the normal case, and section #1
, #2 (average phase difference sections that differ from each other by 180 degrees) are consecutively included in most of the sample sections, so correct average phase differences can be found in both sections. b indicates the case where the average phase difference is around 0 (or 2 points), the phase difference samples are concentrated around 0 (or 2 points), and the correct average phase difference is found in section #2, but in section #1 Since the distribution is divided, when the average is calculated, an erroneous average phase difference appears near m. In such a case, many samples are counted by the average interval judgment circuit 7 in Figure 1, and a selection signal k is output to select the average phase difference found in interval #2, so that the correct average position can be determined. A phase difference is obtained. c shows the case where the reception level is low and the phase difference is distributed almost uniformly.It is the phase difference distribution when the reception level decreases due to fading etc. and the signal is buried in noise, and it becomes an almost uniform distribution. However, the correct average phase difference cannot be determined. In this case, the write determination circuit 8 determines that the distribution is uniform and prohibits writing to the memory circuit 9, so that the reproduced clock is output according to the average phase difference obtained at an earlier average time. . As explained above, according to this configuration example, a correct reproduced clock can be output in any case of phase difference distribution.
4 and 5 are configuration examples of the phase difference averaging circuit 5 and the averaging section selection circuit 7 in the embodiment of the present invention shown in FIG. 2 phase difference display signal input terminal, 23 is a sample timing signal input terminal, 24 is a phase difference average section selection signal input terminal, 25 is a phase difference average time instruction signal input terminal, 26 is an average phase difference output terminal, 27, 28 are phase difference accumulators #1, #2, and
29 is an accumulation result selection circuit, 30 is a division circuit, 31 is an average phase difference correction circuit, 32 is a counter, A and B are first and second phase difference display signals, respectively, C is a sample timing signal, and D is a Phase difference average section selection signal, E and F are cumulative results #1 and #2, respectively, G is the selected cumulative result, day is the temporary average phase difference, 1 is the average phase difference, J is the total number of samples, K 41 is a phase difference display signal input terminal, 42 is a sample timing signal input terminal, 43 is a phase difference average section selection signal output terminal, 44 is a window circuit, 45 is a counter, and 46 is a comparison circuit. , 47 is a counter, M is a phase difference display signal, N is a determination result signal, 0 is a sample timing signal, P is a signal indicating that there is a phase difference sample within a specified section, Q is the number of samples within a specified section, R is the total number of samples, and S is the phase difference average section selection signal.

The operation of the configuration example of the phase difference averaging circuit shown in FIG. 4 will be described below.

Each accumulator 27, 28 receives a sample timing signal C(
(corresponding to signal b in FIG. 1), the first and second phase difference display signals A and B are accumulated.

That is, phase difference samples are accumulated in phase difference averaging sections #1 and #2. One of the accumulation results E and F is selected by the accumulation result selection circuit 29 in accordance with the phase difference average section selection signal D to produce an accumulation result G, and the accumulation result G is input to the divider 3. The total number of samples J determined by the counter 32 is also input to the divider 3, and by removing the accumulated result G, the provisional average phase difference date is output. The provisional average phase difference date is subjected to correction corresponding to the average interval in an average phase difference correction circuit 31, and thereby an average phase difference of 1 is output. That is, according to this configuration example, the phase difference sample is 1
It is possible to output an updated average phase difference 1 each time a phase difference 1 is input. Next, the operation of the example configuration of the average interval selection circuit shown in FIG. 5 will be explained. The window circuit 44 determines whether the phase difference display signal M is within a designated section (in this case, an interval near 00 or 360 degrees) and outputs a determination result signal N.

By performing a logical product of the determination result signal N and the sample timing signal ◯, if there is a phase difference sample within the specified section, a signal P is output, and the signal P is counted by the counter 45. The output Q of the counter 45 indicates the number of samples within the specified interval. The number of samples in the specified interval Q is compared with the total number of samples R obtained by the counter 47 in the comparator circuit 46, and if the value of the ratio is equal to or greater than a specified value, a phase difference is generated that instructs to select the average interval #2. An average section selection signal S is output. This configuration example operates to determine whether the number of phase difference samples within a specified interval is greater than or equal to a specified value with respect to the total number of samples. In this case, only the required number (number of divided sections) of this configuration example can be used.As is clear from the above explanation, the clock recovery circuit of the present invention can be configured only with digital circuits. , so it is suitable for mountain 1 conversion.

Further, the operation of each circuit can be easily replaced with a microcomputer program, and the entire circuit can be integrated very easily. As explained above, the clock regeneration circuit of the present invention has a good synchronization pull-in characteristic, so that the dead time from the start of signal reception until the demodulated data becomes valid is extremely short. It can be used even when the clock phase of the received signal changes frequently, such as when using digital communication using burst-like signals or when switching diversity is used, and after synchronization, the clock component of the received signal is Since the average phase of the regenerated clock is calculated and the phase of the regenerated clock is updated, high reliability and S/N can be expected from the regenerated clock, and the previous average phase is maintained when the reception level drops or the reliability of the average phase decreases. , extremely high synchronization stability (no loss of synchronization) can be expected, and since the average phase is calculated in two different intervals and the average phase is brought into the interval that shows the correct average phase, the recovered clock phase is It has unique effects such as high reliability, the entire circuit is digital, and most of it can be converted into software using a microcomputer, so it can be realized with simple hardware and is extremely suitable for integration. It is possible to miniaturize digital communication systems such as multiple access systems and therefore have very high line efficiency.

It has the advantage that it can be configured with a lightweight device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram showing how this circuit synchronizes with the clock phase of a signal, and Fig. 3 shows various phase difference distributions and each phase difference average section. FIG. 4 is a block diagram of an exemplary configuration of a phase difference averaging circuit, and FIG. 5 is a block diagram of an exemplary configuration of an average interval determining circuit. 1... Signal input terminal, 2... Regenerated clock output terminal, 3... Oscillator, 4... Frequency divider, 5... Phase difference averaging circuit. , 6... Change detection circuit, 7... Average interval judgment circuit, 8...
Write determination circuit, 9... Memory circuit, 10...
...Phase shift circuit, a...Input signal, b...
...Pulse signal indicating a logic change, c...Reception level signal, d...Oscillator output, e...4 first phase difference display signal, f......th two phase difference display signals, g... a reference signal with a frequency approximately equal to the clock frequency of the signal, h... average phase difference, i... output signal of the memory circuit 9, j... …・Regenerated clock output “
k...Phase difference average section selection signal, 1...Write inhibit signal, m...Storage circuit control signal, n...Phase difference average time instruction signal, 21...First Phase difference display signal input terminal, 22... Second phase difference display signal input terminal, 23... Sample timing signal input terminal, 24... Phase difference average section selection signal input terminal. , 25
...Phase difference average time indication signal input resistor, 26.
...Average phase difference output terminal, 27...Phase difference accumulator #1, 28...Phase difference accumulator #2, 29...
... Accumulation result selection circuit, 30... Division circuit,
31... Average phase difference correction circuit, 32... Counter, A... First phase difference display signal, B... Second phase difference display signal, 0... ...Sample timing signal, D...Phase difference average section selection signal, E...
...Accumulation result #1, F...Accumulation result #2,
G: Selected cumulative result, Day: Temporary average phase difference, 1: Average phase difference, J: Total number of samples, K: Place Phase difference average time instruction signal, 41...
... Phase difference display signal input terminal, 42 ... Sample timing signal input terminal, 43 ... Phase difference average section selection signal output terminal, 44 ... Window circuit, 4
5... Counter, 46... Comparison circuit, 47...
・Counter, M... Phase difference display signal, N...
...Judgment result signal, 0...Sample timing signal, P...Signal indicating that there is a phase difference sample within the specified section, Q...Number of samples within the specified section,
R: Total number of samples, S: Phase difference average section selection signal. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. In a digital communication receiving device, an oscillator having an oscillation frequency that is a fixed number multiple of the clock frequency of the received signal, and an oscillator that divides the output signal of this oscillator into a fixed number that is approximately equal to the clock frequency of the received signal. A first phase difference display signal that outputs a frequency reference signal and shows a phase difference with this reference signal, and a second phase difference display signal that shows a phase difference that differs from the first phase difference display signal by a certain phase. An output frequency divider, a change detection circuit that detects logical changes in the received signal, and a phase difference average by determining the proportion of the phase difference between the clock component of the received signal and the reference signal within a specified interval. an average section determination circuit that outputs a section selection signal; and an average section determination circuit that uses each of the phase difference display signals to average the phase difference between the reference signal and the clock component of the received signal in two sections, and determines the average position according to the phase difference average section selection signal. a phase difference averaging circuit that outputs a phase difference; a write determination circuit that outputs a write inhibit signal to a storage circuit described later from the distribution of the phase difference between the reception level or the clock component of the reception signal and the reference signal;
A storage circuit that stores and reads out the average phase difference according to the write inhibit signal and a storage circuit control signal output from the control circuit described later; and a storage circuit that changes and reproduces the phase of the reference signal according to the output of the average phase difference of the storage circuit. a phase shift circuit that outputs a clock; and memory circuit control signals such as address signals, read signals, and write signals in response to the output of the oscillator, and the phase difference averaging circuit, average interval determination circuit, and write determination circuit. and a control circuit that outputs a control signal indicating a phase difference averaging time based on the distribution of the phase difference or After determining whether or not the received signal is valid based on the level of the received signal, controlling generation of the phase difference average section selection signal, the write inhibit signal, and the various control signals so as to be used for subsequent generation of a recovered clock. A clock regeneration circuit featuring: