JPS6028098A - Memory reading circuit - Google Patents

Abstract

PURPOSE:To read a memory at a high speed with a low detecting current by using the drain voltage of a memory element to control the gate voltage of a switching MOSFET. CONSTITUTION:When a memory element 11 is kept on, the drain current of a drain current cut-off MOSFET21 is approximately equal to the ON current of a current detecting MOSFET25 and set at 1/3-1/5 ON current of the element 11. Then the FET21 is cut in response to the reduction of the outputs of inverters 23 and 24. The FET21 has virtually no subthreshold period and performs a high- speed switching performance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory read circuit, and particularly to a current detection circuit suitable for a high-speed read circuit with a small detection current.

[Background of the invention]

As shown in FIG. 1, a conventional nonvolatile memory readout circuit consists of MOS transistors 23 and 24 forming an inverter.
The drain voltage Vn of the memory element 11 is kept constant through a closed circuit consisting of a transistor 22 whose one end is connected to Vcc, and the current flowing through the memory element 11 is converted into a voltage by the transistor 25, which is then sent to the level detection circuit 31. A method is adopted in which the signal is output through the waveform shaping circuit 32. In this circuit, the transistor 22 is set sufficiently large in order to keep the drain voltage VD of the memory element constant.

Therefore, when the memory element 11 is in a conductive state, a DC current corresponding to the on-resistance of this element flows, which is the object of the present invention.
MO8) Cannot be used in low-power memory read circuits composed of transistors.

Another known example of a current detection type readout circuit is the circuit shown in FIG. In this circuit, the common output line of the switch composed of MOS) transistors is connected to the normally-on type M
In this method, the load MO843 is connected to the stain source via the transistor 42 (OS). In this circuit, when all of the switches 411 to 412 are off, the output line v+,
V2 approaches Vcc via load MO843. When the threshold voltage of the transistor 42 is reached, the transistor 42 is cut off and from then on ■! is a constant value.J) Only V2 is above Vcc. In this circuit, when the transistor 42 is cut off, the load capacitance CI of the output line is no longer charged, so that the voltage (2) rapidly rises to Vcc, which has the advantage of allowing high-speed reading with a relatively small charging current.

However, in this circuit, when the potential of Vl approaches the threshold voltage of the transistor 42, the on-resistance of the transistor 42 increases.
It is not possible to reduce the charging current.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory read circuit that improves the drawbacks of the conventional circuits and enables high-speed reading with low detection current.

[Summary of the invention]

This circuit uses a common current detection transistor and a current supply transistor to the memory element, limits the supply current to 1/3 or less of the on-state current of the memory element, and uses a current cutoff transistor between the current supply transistor and the memory element. switch MO8
This circuit enables high-speed reading by inserting a MOS transistor and controlling the gate voltage of this MOS transistor by the drain voltage of the memory element. Details will be explained below using examples.

[Embodiments of the invention]

FIG. 3 shows an embodiment of the present invention. 11 is a non-volatile memory element, 21.23 is an NMOS) transistor, 24.2
5 is a PMO8) transistor, 31 is a level detection circuit, 3
2 is a waveform shaping circuit, and 31 and 32 both have an impark configuration. The on-current of the transistor 25 is the same as that of the memory element 1.
The transistor size is set so that the on-current of 1 is 173 to 115. The drain current cut MOS transistor 21 is sized to allow a sufficiently large current to flow compared to the on-current of the memory element 11, and its gate voltage is controlled by the output of an inverter composed of transistors 23 and 24. Further, the gate voltage of the inverter is inputted with the drain voltage of the memory element. The size of the transistors 23 and 24 is determined so that the current cutting transistor 21 is cut off at a potential higher than the on level (VOL) determined by the transistor 25 and the memory element 11 by Δ■. This ΔV is set so that it is always a positive voltage regardless of variations in VOL due to processing and use. FIG. 4 shows the relationship between drain voltage and drain current.

The operation of this circuit will be explained below. When the memory element 11 is in the on state, it is stabilized at point a in FIG. 4. At this time, if the transistor 21 is made sufficiently large and Vz>VOL+ΔVK is set, VDI = V n = Vat. The drain current in this state is approximately equal to the on-current IM of the current detection transistor 25, and by setting this to 1/3 to 115 of the on-current of the memory element, the detected current can be reduced. On the other hand, the falling multi-speed is the time during which the charge of C2 charged to Vcc and the charge of CI charged to Vcut are discharged by IM. Data line capacity of memory matrix C! is the capacity of the detection circuit Cs compared to C2
>C2, so the fall time Tt is CtV"t/I
Proportional to y. That is, by keeping the cutoff voltage V c u t of the transistor 21 low, the fall time Tt can be shortened.

On the other hand, when the memory element is turned off, VDI * VD
are charged to V cut and VCC, respectively. The startup time Tr at this time is (VCut - Vot, )/
It is proportional to (C+ +Cz)+(V-Vcut)/Cz. In this case, as in the case of falling time, Trol:v
cut/C! is approximately proportional to

On the other hand, the relationship between Vn and (2) near Vn=Vcut can be designed as shown in FIG. That is, 2
3.24 The logical threshold of the inverter is V
If it is designed near V cut, when VD increases slightly near V cut, the inverter output will rapidly decrease and the transistor 21 will be cut. As a result, the transistor 21 has almost no subthreshold period and performs a high-speed switching operation, making it possible to operate at a higher speed than a gate voltage switch as shown in the known example shown in FIG.

If a difference is established between the on-currents of the memory element 11 and the current detection transistor 25, the point a, that is, VOL shown in FIG. Also, CMO
Since the gain of the S inverter is very high, there is no need to make the difference between Vcut and VOL, ie, Δ■, extremely large in FIG.

As mentioned above, reducing ΔV and lowering t, VCt is effective in increasing the operating speed of the detection circuit.

The drain voltage Vn of the memory element 11 is VOL and VCI.
The drain voltage of the nonvolatile memory can be kept below a certain voltage without deteriorating the memory retention characteristics of the memory, as shown in FIG. 1 of the known example.

As explained above, in this embodiment, the on-current of the current detection transistor 25 is set to 1/3 of the on-current of the memory element.
~115 to reduce power consumption, and by controlling the gate voltage of the drain current cut transistor 21 with the inverter output that inputs the drain voltage of the memory element, the cutoff transistor 21 can be set to an ideal value. It operates as a switching element to reduce the charging/discharging voltage of the capacitive load connected to the data line, thereby preventing deterioration in detection speed caused by reducing detection current and realizing variable readout speeds.

[Effects of the Invention] □ Compared to conventional memory detection circuits, the present invention reduces power consumption to 1/3 to 115 times, and reduces the readout speed due to a decrease in detection current by increasing the data line wake-up voltage amplitude with a high gain. To provide a memory read circuit which enables high-speed reading equivalent to the conventional system by supplementing the limitation with a switch circuit.

[Brief explanation of the drawing]

1 and 2 are circuit examples for explaining the prior art, and FIG. 3 is a circuit configuration of the present invention. FIG. 4 shows the operating levels of the readout circuit of the present invention. FIG. 5 shows the load characteristics of the inverter (23.degree. 24) that controls the gate of the transistor 21 when the drain voltage of the memory element is near Vcut'. In FIG. 3, 11... nonvolatile memory element, 25 current detection transistor, 21... current cut transistor, 23
．． 24...NMO8 and PM that constitute the inverter
O8) Transistor, 31 River level detection inverter, 3
2... Waveform shaping inverter, cl... Data line load capacitance, C2... Detection circuit capacitance. 1st Port 2nd Figure 3 Figure 4- Figure

Claims (1)

[Claims] 1. One end of a switch constituted by a field effect transistor 21 is connected to the drain terminal of the memory element 11, and the other end is connected to the source or drain of a current detection field effect transistor 25. In a memory reading circuit in which the other terminal of the transistor 25 is connected to a power source and a voltage change at the connection point between the current detection transistor and the switch is detected by a level detection circuit 31, the gate voltage of the switch 21 is connected to the voltage of the memory element 11. A memory read circuit characterized in that it is controlled by the output of an inverter whose input is a drain. 2. In claim 1 above, the on-current of the current detection transistor 25 is set to 1 of the on-current of the memory element 11.
1. A memory read circuit characterized in that the value is set to /3 to 115.