JPS6027222A - Phase comparator - Google Patents

Abstract

PURPOSE:To reduce power consumption by detecting one specific state of two digital signals and its inverted state and controlling the output period of the detected signal by one digital signal and a gate signal having a fixed phase. CONSTITUTION:The 1st detecting circuit 22 detects a specific state, e.g. A, B= ''1'', ''0'', out of the combination of input signals A, B and the 2nd detecting circuit 23 detects its inverted state A, B=''0'', ''1''. The gate signal is a signal enabled to gate the phase comparing edge (rising edge) of the input signal B and having a fixed phase difference. When the 1st power supply 24 is the constant voltage source of an output voltage VH and the 2nd power supply 25 is the constant voltage source of an output voltage VL, only a switching circuit 26 is conducted and the voltage VH is outputted during the period of an output from the circuit 22, and only a switching circuit 27 is conducted and the voltage VL is outputted during the period of an output from the ciruit 23. In said constitution, both circuits 26, 27 are not conducted simultaneously and the circuit on the output stage consumes its electric power only for the period of a phase difference, so that the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase comparator circuit suitable for a phase locked loop circuit (hereinafter referred to as a PLL circuit).

Conventional configurations and their problems PLL circuits are widely used in many applications such as frequency multipliers, but the characteristics of the phase comparator circuit, which is one of the components of the PLL circuit, greatly affect the characteristics of the PLL circuit itself. To this end, various phase comparator circuits have been devised and put into practical use.

Now, in recent years, especially in the field of consumer electronics products, there has been a strong demand for equipment to be smaller and lighter, lower power consumption, and cost reduction, and one of the solutions to these demands is the use of integrated circuits (hereinafter referred to as ICs) for electronic circuits. is in progress. In the case of integrated circuits, all external elements are integrated into the IC, thereby reducing the number of external parts and reducing the number of pins of the IC in order to reduce the size of the IC package and package cost.

Efforts are being made to devise electronic circuits.

In the following, it is assumed that the input signal is a binary digital signal.

We will discuss two conventional edge comparison type phase comparison circuits and discuss their configuration, operation, and problems.0 The conventional first phase comparison circuit is widely used and consists of a digital circuit that does not require external components. A circuit diagram of the circuit is shown in FIG.

In FIG. 1, 1 to 9 are NAND gates, 10 is an inverter, 11 is a P-channel MOS transistor, 1
2 is an N-channel MOS transistor. NAN
D gates 1 and 2, 3 and 4, 6 and 6° γ and 8 are R respectively
Since it is configured as an S flip-flop, there are 12 states in the phase comparator shown in FIG. 1, depending on the combination of states of each of the seven logic flip-flops. FIG. 2 shows state transitions caused by input signals A and B.

The number shown above the ○mouth in Figure 2 indicates the condition number,
○ The right side of the lower part of the mouth shows the input state of input terminal A, the left side shows the input state of input terminal B, and the arrow shows the direction of state transition.

3(A) to 3(F) are operational waveform diagrams of the phase comparator circuit shown in FIG. 1, and the input signal Ai (A) shown in FIG.
, input signal B'lr (b), output C of NAND gate 2 (/'1, output of NAND gate 8), output 0TJT1 k (e), each time of the phase comparator circuit. state? The status number is shown in (to). Input A
When the rising edge of input B is 9 edges, the output C becomes ○ only when the phase is ahead, and the output p becomes 0 only when the phase is delayed, outputting a phase difference. I understand that. “1” in digital circuits
If it corresponds to the voltage no-y level and "○" to the low level, then during the period when the output C is "0", the P-channel MO3) transistor 11 in Fig. 1 becomes conductive, and the output ○UT1 becomes no- During the period when the output level is "○", the N-channel MO8) transistor 12 is conductive and the output is 0UT1.
becomes low level. As is clear from the state transition diagram shown in FIG. 2, outputs C and D do not become "0" at the same time, so P channel MO3) range meta 11. N-channel MO8) The transistors 12 are not conductive at the same time.0 When the outputs C and D are both "1", both transistors are non-conductive, so the output 0UT1 is in a high impedance output state. Therefore, it is looped to the output OUT1. If you connect a filter, it will be input A.

A potential proportional to the phase difference between the falling edges of B is obtained at the output of the loop filter. Since the phase comparator circuit can be constructed almost entirely of digital circuits, no external components are required, and an output circuit (two MOS transistors in the circuit shown in FIG. 1) that consumes a large amount of power corresponds to the output circuit. ) operates only during periods where there is a phase difference, so it has the advantage of low power consumption.

However, there is a problem when noise is mixed into the input.

FIGS. 4(A) to 4(E) show dynamic waveform diagrams when large noise suddenly mixes into the input A of the phase comparator circuit. In the same figure (a) and (b), the waveform of B is input manually, respectively.
(c), ni), and (e) are outputs C, D, and 0UT1, respectively.
The waveform is shown. The example shown in Figure 4 is the same figure (a).
4 shows the operation when the third negative pulse to the input is missing due to noise, and the broken line in FIG. 4 shows the operation when no noise is mixed. As is clear from the figure, there is a problem in that a very large erroneous phase difference output is output due to noise, and the original state does not return even after the noise disappears. This is because it has an RS flip-flop which is a storage circuit inside.

Therefore, if this phase comparator circuit is used in a PLL circuit, there will be a problem in that if the phase comparator malfunctions due to input noise, it will take a long time to stabilize.

By the way, for example, in a simple video tape recorder, jitter correction of the reproduced color signal is performed using an automatic frequency control circuit (hereinafter referred to as AFC circuit) and an automatic phase control circuit. It is obtained by a continuous signal 2PLL circuit having an integer multiple of . The conventional first phase comparison circuit is inappropriate for the phase comparison circuit forming a part of this PLL circuit. This is because the input signal of the reproduced horizontal synchronization signal, which is one of the phase comparison inputs, may be lost due to dropouts, etc., and the malfunction shown in Figure 4 may occur and the FC circuit may become unstable. be.

A phase comparator circuit suitable for the AFC circuit is disclosed in Japanese Patent Application Laid-Open No. 56-3.
No. 6225. This second phase comparator circuit has a configuration as shown in FIG. In the figure, 13, 14 and 15 are switch circuits, 16 and 17 are constant current sources with equal current values and different polarities, and 18 is a capacitor.

The capacitor 18 can also be regarded as a loop filter of a PLL circuit. 8. B is a phase comparison input, and G is a gate signal. These human forces A, B and gate signal G serve as control inputs to switch circuits 13, 14, and 15, respectively.

FIG. 6 shows an operating waveform diagram of the second phase comparison circuit.

In FIG. 6, (a), (b), (c), and (b) indicate the waveforms of human power, B, gate signal G, and output 0UT2, respectively.

If the gate signal G and input A have the phase relationship shown in FIGS. 6(a) and 6(b), the phase comparison circuit shown in FIG.
The fact that an output proportional to the phase difference between the falling edges of B can be obtained will be explained using the same figure. However, when the gate signal G and inputs A and B are at high level, the switch circuit 15,
13 and 14 are respectively in a conductive state. Since the switch circuit 16 is in a conductive state and the phase difference is output to the output terminal only during the period when the gate signal G is at a high level, the output from time t1 to time t6 shown in FIG. 6 will be considered. Assume that the signal P3 has a waveform shown by a solid line.

From time t1 to time t3, the switch circuit 13゜1
4 becomes conductive, and the current IO from the constant current source 16 passes through the switch circuits 13 and 14'i and is all absorbed by the constant current source 17, so no current flows through the capacitor 18 and the output is 0UT2.
The potential of does not change.

From time t3 to time t, the switch circuit 13
becomes non-conductive, so the capacitor 18 is connected to the switch 15°1.
Since the constant current I0 is absorbed by the constant current source 17 through the four terminals, the potential of the output 0UT2 decreases at a constant slope.

From time t4 to time t6, switch circuit 13.1
4 become non-conductive, no current flows through the capacitor 18, and the potential of the output 0UT2 does not change. Therefore input A
, B, the potential of the output 0UT2 decreases in proportion to the phase delay of the input B with respect to the input A.

Next, consider the operation when input B has the waveform shown by the broken line.

From time t1 to time t2, the switch circuits 13 and 14 are conductive, and the current I from the constant current source 16. passes through the switch circuits 13 and 14'i and is all absorbed by the constant current source 1T, so no current flows to the capacitor 18 and the output is 0UT.
The potential of 2 does not change.

From time t2 to time t3-, the switch circuit 14 becomes non-conductive, so the current Io from the constant current source 16 all flows to the capacitor 18 via the switch circuit 13.16, so the potential of the output 0UT2 rises at a constant slope. do.

From time t3 to time t5, switch circuit 13.1
4 become non-conductive, no current flows through the capacitor 18, and the potential of the output 0UT2 does not change. Therefore, input A,
The potential of the output 0UT2 rises in proportion to the phase advance of the input B with respect to the input A with reference to the falling edge of B. As explained above, the conventional second phase comparator circuit can obtain a potential proportional to the phase difference between the input edges. This second
Unlike the first phase comparison circuit, this phase comparison circuit does not have an internal memory circuit such as a flip-flop, so even if it malfunctions due to sudden noise, it can easily return to its original state and remain dimensional. However, since the phase difference output period is limited by the gate signal G shown in Figs. 5 and 6, a large phase difference will not be output even in the case of the above-mentioned malfunction, so it will not be affected by sudden large noise. It has the advantage of being relatively stable. However, it has the following problems.

This is a power consumption problem, which will be explained with reference to FIG. 6 and FIG. 6. If the input signals B are both at high level, the switch circuits 13 and 1.4 become conductive regardless of the gate signal G, and a current I flows through the switch circuits 13 and 1.4. is the constant current source 16
The current flows from the constant current source 17 to the constant current source 17, and even when the phase difference is zero, power is consumed inside the phase comparator circuit. Moreover, since the output stage circuit is configured so that a large current can be taken out to the outside compared to other circuits in the phase comparator circuit, there is a problem in that the power consumption due to the current generator 0 cannot be ignored.

OBJECTS OF THE INVENTION The present invention solves the problems of the conventional phase comparator circuit as described above, and aims to provide a phase comparator circuit that consumes less power and is relatively stable against sudden noise.

Structure of the Invention The present invention detects a specific state and an inverted state of this specific state from a combination of states of two digital input signals A and B whose phases are compared with each other, and On the other hand, this is a phase comparator circuit configured to control the output period of the detection signal with a gate signal having a constant phase difference, and operate the output circuit with the controlled detection signal of this output period, and only during the period with the phase difference. This phase comparator circuit can reduce power consumption by operating the phase difference output circuit, and has excellent noise resistance.

DESCRIPTION OF EMBODIMENTS FIG. 7 is a circuit diagram of a phase comparator circuit according to an embodiment of the present invention. In the figure, 19, 20 and 21 are respectively terminals for digital input signals, B and gate signal terminals, 22 is a first detection circuit that detects a specific state among the combination of states of input signals A and B, and 23 is a first detection circuit a second detection circuit that detects a state that is inverted from the detection state of the first detection circuit; 24.
25 is a power supply, 26 and 27 are switch circuits, 28 is an output terminal for the phase difference output signal 0UT3, and 29 is a capacitor. If the first power source 24 is a constant voltage source, the second power source 26 is a constant voltage source with a different voltage output than the first power source 24, and the first power source 24 is a constant current source.

If it is a constant current source, the second power supply 25 will have a constant current (-I.

)of? It is a current source.

11" of the digital signal is at the high level of voltage, 10j
corresponds to the low level of voltage.

The first detection circuit 22 combines the states of input signals A and B (
A, B) = (○, ○) + (0,1), (1+O
) + (1, 1), for example, (1°0), and the second detection circuit 23 detects the inverted state (A, B) - (0, 1). Figure 8 shows the operating waveform diagram when this happens. Figure 8 (a) shows the gate signal, (
(b) shows the waveform of the input signal B, and (c) shows the waveform of the input signal A. The gate signal is a signal having a certain phase difference that can gate the phase comparison edge (here, the rising edge) of the input signal B. The first detection circuit 22 is A-1 and B=o
is detected, resulting in the waveform shown in Figure 8), and the second detection circuit 23 detects A-0 and B=1'i, so (E)
The waveform is shown in . If the first power supply 24 is a constant voltage source with an output voltage ■H and the second power supply 25 is a constant voltage source with an output voltage vL, only the switch circuit 26 is conductive during the period when the first detection circuit 22 has an output. , the voltage vH is output, and only the switch circuit 27 is conductive for a certain period of time when the second detection circuit 23 outputs, and the voltage ■L is output, so the output signal 0UT30 is output.
The waveform is as shown in (f).

If the phase of the rising edge of input signal A is advanced as shown by the solid line in FIG. 8 based on the rising edge of input signal B, voltage VH is output only during the phase advance period, which is shown by the broken line in FIG. 8. It can be seen that if the phase of the input signal A is delayed, the voltage vL is output only during the phase delay period. The first power supply 24 has a constant current ■. If the second power source 26 is a constant current source with a constant current (-Io) and a capacitor 29 is connected to the output terminal 28 as shown by the broken line in FIG. During a period when the detection circuit 22 has an output, only the switch circuit 26 is conductive, and a current I is applied to the capacitor 29. flows in, the potential of the output signal UT3 rises, and only the switch circuit 27 is conductive for a period when the second detection circuit 23 outputs, and a current I flows from the capacitor 29. flows out, the potential of the output signal 0UT3 drops, so the output signal 0UT3
The waveform is shown in (g). If the phase of the rising quench of the input signal A advances as shown by the solid line in FIG. 8 based on the rising quench reference of the input signal, the output signal 0UT3 rises only during the phase advance period, and the broken line in FIG. As shown by , if the input signal A is delayed, the potential of the output signal 0UT3 drops only during the phase delay period.

In the configuration according to the present invention, the switch circuits 26 and 27 are not conductive at the same time, and the output stage circuit consumes power only during the period when there is a phase difference, so the width is wider than that of the conventional second phase comparator circuit described above. This has the effect of reducing power consumption. 1st. Since the second power source 24, 26 may be a constant current source or a constant voltage source, it has the effect that it can be selected according to the purpose depending on the IC process. In the explanation of FIG. 8, 1. Combination of input states detected by the second detection circuit (8, B)
are respectively (1, O) and (011), but (1°1)
However, it is clear that (1,1) and (○r Q) or (0°0) and (1,1) may be used.

This differs only in the combination of edges that serve as a reference when performing phase comparison.

Next, an implementation array used in a phase comparison circuit 2-lock droop circuit (hereinafter referred to as a PLL circuit) of the present invention will be explained with reference to FIGS. 9 and 1o.

FIG. 9 shows a PLL circuit that can stably and accurately obtain a frequency 160 times that of the horizontal synchronizing signal used in a simple video tape recorder, and FIG.
FIG. 3 is a waveform diagram of each part in the phase comparator circuit portion of the circuit. In FIG. 9, 30 is a horizontal synchronizing signal input terminal;
1 is a phase difference signal output terminal, 32 is a loop filter, 3
3 is a voltage controlled oscillator (hereinafter referred to as vCO), 34 is 1
60 frequency divider circuit 35 is an output terminal with a frequency 160 times that of the horizontal synchronizing signal. 36 is a pulse generation circuit, 37°38
is the first. The second detection circuit, 39 and 40 are the first and second switch circuits, and 41 and 42 are the power supply lines with vDD, respectively.
line, vss line (the potential relationship is vDD>■ss; one power supply line may be grounded), and 43 is a gate signal generation circuit.

1st. The second detection circuit 37,38 is the first detection circuit in FIG.
．． It corresponds to the second detection circuit 22.23, and similarly corresponds to the first detection circuit 22.23. The second switch circuits 39 and 40 are connected to the first and second switch circuits 26 and 27, and the power supply lines 41 and 42 are connected to the power supply circuit 24.
．． It corresponds to 25.

The pulse generation circuit 36 is a D flip-flop 44°AND
Consisting of a gate 46 and a counter 46, when the change in the horizontal synchronizing signal is quenched, the D flip-flop 44 operates and the Q output changes from "○" to "11", the gate 45 opens, and the counter 46 receives a signal from V CO33. clock is input. Counter 46 resets flip-flop 44 when it counts a set number of clock pulses. When the flip 70 knob 44 is reset, the Q output is 11''.

Since the Q output becomes "o", the gate 45 is closed and the counter 46 is reset, so the pulse generating circuit 36 is stopped until the next horizontal synchronizing pulse is input. Therefore, the pulse generation circuit 36 starts generating a pulse E (
r occurs. It can be considered a type of monomulti circuit,
(1) Output pulse E with a clock pulse whose frequency changes
Since the configuration determines the end timing, the VCO
The pulse width changes according to the frequency change of 33. (I
Since the frequency of the horizontal synchronizing signal D and the frequency of the VCO 33 are not necessarily in a synchronous relationship, the start timing 'f of the pulse E, that is, the rising edge of the horizontal synchronizing signal is at the 9 timing, and the timing at the end of the pulse E has jitter. 2
This is different from a normal mono multi-circuit. Note that the timing of the end of the pulse E is not an edge for phase comparison, so it does not affect the output of the phase comparison circuit. The reason why the pulse width of the input horizontal synchronizing signal is fully expanded in this way is as follows. The pulse width of the horizontal synchronization signal is about 4 μs to 5 μs, which is narrow compared to the horizontal period of about 64 μs.

If the pulse width of the input signal to be phase-compared is narrow compared to the pulse width of the gate signal, as in this horizontal synchronization signal, the correct phase difference may not be obtained, and the data of the input signal to be phase-compared may be incorrect. Utility cycle is too small for 50%. Alternatively, if it is too thick, a problem arises in that the lock range of PLL recording is biased. A circuit for improving this problem is the pulse generation circuit 36. Therefore, if the duty cycle of the phase comparison input signal is not too wide or too small, the pulse generation circuit 36
can be omitted.

Figure 10 (a) shows the input signal, the horizontal synchronization signal (:I
) show the waveforms of the output E of the pulse generating circuit 36, respectively.

The gate signal generation circuit-43 is an RS flip-flop 47
and a timing decoder 48. By decoding the output of the counter of the frequency dividing circuit 34, a timing having an arbitrary phase difference with respect to the output F of the frequency dividing circuit 34, which is a signal whose phase is compared, can be obtained. By setting and resetting the flip-flop 47 using the two timing detection outputs, a get signal that always has a constant phase difference with respect to the phase comparison input signal F can be obtained regardless of the frequency change of the pvco. Since the frequency dividing circuit 34 is a 160 frequency dividing circuit, there is a timing of ◯ or 169 ox. Assume that the output F of the frequency dividing circuit 34 is "○" for a period from timing O to timing 127 and "1" for a period from timing 128 to timing 159, and the decoder 48
is the output F of the frequency dividing circuit 34 when the Flinob flop 47 is set at timing 118 and reset at timing 138.
.

and gate signals are shown in (c) and (b) of FIG. 10, respectively. AND gate 5
0.51 and E- only when the gate signal is “1”.
1 and F=ol The second detection circuit 38 detects the inverter 52. to ND game) 53.54, and detects E=O and F=1'i only when the gate signal is "1" 0
The first switch circuit 39 is connected to
.

Channel M'O8) consists of a transistor 56, and the first
P channel M only when the output of the detection circuit 37 is 11''
O8) The transistor 56 becomes conductive and the output terminal 31
The 0th grade is defined as vDD.

The second switch circuit 4o is composed of an N-channel MOS transistor 57, and the output of the second detection circuit 38 is "1".
Only when this happens, the N-channel MOS transistor 5 becomes conductive, and the potential of the output terminal 31 becomes approximately SS. Figure 10 (e) shows the gate 50.

In Fig. 12, the output waveform of the gate 53 is shown, the output waveform of the gate 51 is shown in (g), the output waveform of the gate 54 is shown in (g), and the output waveform of the terminal 31 is shown in (IJ). The solid line indicates the operating waveform when the output F is ahead based on each rising edge standard, and the broken line indicates the operating waveform when the phase is delayed. It can be seen that the vDD potential is output only during the phase lead period, the v88 potential is output only during the phase lag period, and the phase difference between the two manual forces E and F is output accurately.

As described above, according to this embodiment, the phase difference output circuit is the first. The second detection circuits 37 and 38 operate only during periods where there is a phase difference, reducing power consumption and eliminating the need for monomulti circuits that require external components for setting time constants.

By configuring a digital circuit using a clock pulse from the pulse width ffVco, a phase comparison circuit configuration that does not require adjustment or external components can be achieved, and a small and inexpensive package with a small number of pins can be used. It is. In addition, the output pulse width of the pulse generation circuit 36 is set to be more than half the period H of the horizontal synchronization signal in the range of change of vCO. Even if a composite synchronization signal including a synchronization signal is input to the pulse generation circuit 36 instead of the horizontal synchronization signal, only the horizontal synchronization signal is output, so that a function of separating the horizontal synchronization signal can be provided.

- Also, since the pulse generating circuit 36 does not accept any input chips during the pulse output period, it is not affected by noise during the pulse output period. It has many advantages and is highly effective in practical use.

In the above embodiment, an example in which the present invention is applied to such a phase comparison circuit 1 PLL circuit has been described, but it goes without saying that the phase comparison circuit according to the present invention can be used in circuits other than PLL circuits.

Effects of the Invention The phase comparator circuit of the present invention detects one specific state and the inverted state of the combination of states of digital signals A and B whose phases are compared with each other, and changes the output period of this detection signal to one side. Since the circuit is configured to be controlled by a gate signal having a constant phase difference with the digital signal, and the output circuit is operated by the detected signal controlled during this output period, the influence of noise can be reduced, and the power consumption can be reduced by 1. The practical effects are great.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the first conventional phase comparison circuit, Figure 2 is a state transition diagram of the same phase comparison circuit, Figures 3 (a) to (f) are operational waveform diagrams of the same phase comparison circuit, Figures 4 (A) to (E) are operational waveform diagrams when a sudden noisy signal is input to the same phase ratio soft circuit. Figure 6 is a configuration diagram of a conventional second phase comparison circuit. Figures 6 (a) to (g) are operational waveform diagrams of the in-phase comparison circuit, Figure 7 is a circuit diagram of the phase comparison circuit in one embodiment of the present invention, and Figures 8 (a) to (g) are the same embodiment. FIG. 9 is a circuit diagram of a PLL circuit using a phase comparator circuit according to an embodiment of the present invention, and FIGS. 37...first detection circuit, 23.38...
...Second detection circuit, 24...First power supply, 2
6-... Second power supply, 26.39... First switch circuit, 27.40... Second switch circuit, 43... Gate signal generation circuit. Name of agent: Patent attorney Toshio Nakao (1st person)
Fig. 3 also - Fig. 4 $3). uT, -1--3-Ax-11111 Figure 5 Figure 6 Word Figure 7 (A) K ug No. □ +11) B ()) OυT3 -- 11 Ho 1 No. 1 O Figure May ε/ ri 11d l and υ /3b 0 Written amendment November 7, 1988 1 Display of the case 1988 Patent Application No. 134565 2 Name of the invention Phase comparator circuit 3 Relationship with the amended person case Patent issued Request Address: 1006 Kadoma, Kadoma City, Osaka Prefecture Name (
5 & 2) Matsushita Electric Industrial Co., Ltd. Representative Toshihiko Yamashita 4 Agent 571 Address 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 6 Amendment Order Date 7, Contents of Amendment (1) Specification No. In the 6th line of page 2, correct [Figure 6 (a) to (d)] to ``Figure 6 is''. (2) On page 24, line 11 of the same book, "Fig. 10 (a) to (su) wa" was corrected to "Fig. 10 wa" (1).

Claims (2)

[Claims] (1) A gate signal generation circuit that receives digital signals A and B whose phases are compared with each other and generates a gate signal having a constant phase difference with respect to the digital signal B; Combination (A+B)-(
o+o), (o+1)+c1+o)+ (1+1), one specific state (A, B) - (A1 r B1)
a first detection circuit whose output period is controlled by the gate signal; and the combination state detected by the first detection circuit (A, B) - (A1.B1 inverted combination state). Detected at (A, B)-(A11B1)',
and a second detection circuit whose output period is controlled by the gate signal; A second constant voltage source or a first constant voltage source having equal absolute values and different polarities. a second constant current source, a first switch circuit connected between the first constant voltage source or the first constant current source and an output terminal and controlled by the output of the first detection circuit; A second switch circuit connected between the second constant voltage source or the second constant current source and the output terminal and controlled by the output of the second detection circuit. Phase comparison circuit. (2) Digital signal A is an input signal of a phase-locked loop circuit composed of a voltage controlled oscillator, a loop filter, a frequency divider, and a phase comparison circuit, digital signal B is an output signal of the frequency divider, and the gate signal generation Claim (1) characterized in that the circuit generates the gate signal having a constant phase difference with respect to the digital signal B using timing obtained by counting outputs of the voltage controlled oscillator. phase comparison circuit.