JPH0468813B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a phase locked loop (Phase locked loop).
The present invention relates to a phase comparator circuit suitable for PLL circuits (hereinafter referred to as PLL circuits) and the like.

Conventional configurations and their problems PLL circuits are widely used in many applications such as frequency multipliers, but one of the components of the PLL circuit is
Since the characteristics of the phase comparator circuit greatly influence the characteristics of the PLL circuit itself, various phase comparator circuits have been devised and put into practical use.

Now, in recent years, especially in the field of consumer electronics products, there has been a strong demand for equipment to be smaller and lighter, lower power consumption, and lower costs, and one of the solutions to these demands is the use of integrated circuits (hereinafter referred to as ICs) for electronic circuits. is in progress. Even when converting to IC, external elements can be integrated into IC.
internally, reducing the number of external parts and
Efforts are being made to develop block configurations and electronic circuits that can reduce the number of IC pins in order to miniaturize IC packages and lower package costs.

In the following, it is assumed that the input signal is a binary digital signal.

First, we will discuss two conventional edge comparison type phase comparator circuits and discuss their configurations, operations, and problems.

Constructed of a digital circuit that does not require external components,
FIG. 1 shows a circuit diagram of a conventional first phase comparator circuit that is widely used.

In Figure 1, 1 to 9 are NAND gates;
0 is an inverter, 11 is a P-channel MOS transistor, and 12 is an N-channel MOS transistor. NAND gates 1 and 2, 3 and 4,
Since RS flip-flops 5 and 6, and 7 and 8 constitute RS flip-flops, depending on the combination of the states of each flip-flop, the phase comparator shown in FIG.
Two states exist. FIG. 2 shows state transitions caused by input signals A and B.

The numbers shown at the top of the circle in Figure 2 indicate the state number, the right side of the bottom of the circle indicates the input status of input terminal A, the left side of the circle indicates the input status of input terminal B, and the arrow indicates the direction of state transition. ing.

3A to 3F are operational waveform diagrams of the phase comparator circuit shown in FIG. 1, in which the input signal A shown in FIG. C, output D of NAND gate 8 to D,
The output OUT1 is shown in E, and the state of the phase comparator circuit at each time is shown in F by state number. Output C becomes 0 only during the period when the rising edge of input A is ahead of the falling edge of input B in phase, and output D becomes 0 only during the period when the phase lags, outputting a phase difference. I understand that. In a digital circuit, "1" is a high voltage level,
If “0” corresponds to low level, output C “0”
During the period, the P-channel MOS transistor 11 in FIG.
The MOS transistor 12 becomes conductive and the output OUT1 becomes low level. As is clear from the state transition diagram shown in FIG. 2, the outputs C and D never become "0" at the same time, so the P channel MOS transistor 11 and the N channel MOS transistor 12 never become conductive at the same time. When the outputs C and D are both "1", both transistors are non-conductive, so the output OUT1 is in a high impedance output state. Therefore, if a loop filter is connected to the output OUT1, a potential proportional to the phase difference between the falling edges of inputs A and B can be obtained at the output of the loop filter. Since the phase comparator circuit can be constructed almost entirely from digital circuits, there is no need for external components, and the output circuit, which consumes a large amount of power (in the circuit shown in Figure 1, two
The MOS transistor corresponds to the output circuit. ) operates only during periods where there is a phase difference, so it has the advantage of low power consumption.

However, there is a problem when noise is mixed into the input.

FIGS. 4A to 4E show dynamic waveform diagrams when a large noise suddenly enters the input A of the phase comparator circuit. Dynamic diagrams A and B are the waveforms of inputs A and B, respectively, and C, D, and H are the outputs C, D, and OUT1, respectively.
The waveform is shown. The example shown in Fig. 4 shows the operation when the third negative pulse of input A is missing due to noise, as shown in Fig. 4A, and the broken line in Fig. 4 shows the operation when noise is mixed in. This shows what happens if you do not do so. As is clear from the figure, there is a problem in that a very large erroneous phase difference output is output due to noise, and the original state does not return even after the noise disappears. This is because it has an RS flip-flop which is a memory circuit inside.
Therefore, if this phase comparator circuit is used in a PLL circuit, a problem arises in that if the phase comparator malfunctions due to input noise, it will take a long time to stabilize.

By the way, for example, in a simple video tape recorder, an automatic frequency control circuit (hereinafter referred to as AFC) is used.
The jitter correction of the reproduced color signal is performed by an automatic phase control circuit and an automatic phase control circuit. In this AFC circuit, a continuous signal having an integral multiple of the reproduced horizontal synchronization signal is obtained by a PLL circuit. A PLL like this
The conventional first phase comparison circuit is not suitable for the phase comparison circuit forming part of the circuit. This is because the input signal of the reproduced horizontal synchronization signal, which is one phase comparison input, may be lost due to dropouts, etc., and the malfunction shown in Figure 4 may occur, making the AFC circuit unstable. .

A phase comparator circuit suitable for the AFC circuit was developed by Japanese Patent Laid-Open No.
No. 56-36225. This second phase comparator circuit has a configuration as shown in FIG. In the figure, 13, 14 and 15 are switch circuits, 16 and 17 are constant current sources with the same current value and different polarities, and 18 is a capacitor. The capacitor 18 can also be regarded as a loop filter of the PLL circuit. A and B are phase comparison inputs, and G is a gate signal. These inputs A, B and gate signal G serve as control inputs for switch circuits 13, 14, and 15, respectively.

FIG. 6 shows an operating waveform diagram of the second phase comparator circuit. In FIG. 6, A, B, C, and D indicate the waveforms of inputs A, B, gate signal G, and output OUT2, respectively.

If gate signal G and input A have the phase relationships shown in Figure 6 A and B, the phase comparator circuit shown in Figure 5 can obtain an output proportional to the phase difference between the falling edges of inputs A and B. This will be explained using the same figure. However, when the gate signal G and the inputs A and B are each at a high level, the switch circuits 15, 13, and 14 are respectively rendered conductive. The switch circuit 15 becomes conductive only during the period when the gate signal G is at a high level, and the phase difference is output to the output terminal.
Consider the output from time t ₁ to time t ₅ shown in the figure. Assume that the signal P ₃ has the waveform shown by the solid line.

From time t ₁ to time t ₃ , switch circuit 1
3 and 14 conduct, and the current _I0 from the constant current source 16 passes through the switch circuits 13 and 14 and is all absorbed by the constant current source 17, so no current flows through the capacitor 18 and the potential of the output OUT2 does not change. .

From time _t3 to time _t4 , the switch circuit 13
becomes non-conductive, and the constant current I ₀ from the capacitor 18 is absorbed by the constant current source 17 via the switches 15 and 14, so that the potential of the output OUT2 decreases at a constant slope.

From time t ₄ to time t ₅ , switch circuit 1
Since capacitors 3 and 14 are both non-conductive, capacitor 1
No current flows through 8, and the potential of output OUT2 does not change. Therefore, based on the falling edges of inputs A and B, the output is proportional to the phase delay of input B with respect to input A.
The potential of OUT2 decreases.

Next, consider the operation when input B has the waveform shown by the broken line.

Switch circuit 1 from time t ₁ to time t ₂
3 and 14 conduct, and the current _I0 from the constant current source 16 passes through the switch circuits 13 and 14 and is all absorbed by the constant current source 17, so no current flows through the capacitor 18 and the potential of the output OUT2 does not change. .

From time t ₂ to time t ₃ , the switch circuit 14
becomes non-conductive, so that the current _I0 from the constant current source 16 all flows to the capacitor 18 via the switch circuits 13 and 15, so that the potential of the output OUT2 rises at a constant slope.

From time t ₃ to time t ₅ , switch circuit 1
Since capacitors 3 and 14 are both non-conductive, capacitor 1
No current flows through 8 and the potential of output OUT2 does not change. Therefore, based on the falling edges of inputs A and B, the output is proportional to the phase advance of input B with respect to input A.
The potential of OUT2 increases. As explained above, the conventional second phase comparator circuit can obtain a potential proportional to the phase difference between the input edges. This second
Unlike the first phase comparison circuit, this phase comparison circuit does not have an internal memory circuit such as a flip-flop, so even if it malfunctions once due to sudden noise, it can easily return to its original state. Since the phase difference output period is limited by the gate signal G shown in Figures 5 and 6, even if there is a malfunction in the previous period, a large phase difference will not be output by mistake, so a sudden large phase difference will not be output. It has the advantage of being relatively stable against noise. However, it has the following problems.

This is a power consumption problem, which will be explained with reference to FIGS. 5 and 6. If inputs A and B are both at high level, switch circuits 13 and 14 become conductive regardless of gate signal G, and current _I0 flows from constant current source 16 to constant current source 17.
Even when the phase difference is zero, power is consumed inside the phase comparator circuit. Moreover, since the output stage circuit is configured so that a large current can be taken out to the outside compared to other circuits in the phase comparator circuit, there is a problem in that the power consumption due to the current I ₀ cannot be ignored. Furthermore, there are the following problems. The conventional phase comparator uses a monomulti circuit to obtain a signal having a predetermined phase difference with respect to the signals whose phases are to be compared. Mono-multi circuits require large-capacity capacitors and resistors in order to generate long pulses on the microsecond scale, but large-capacity capacitors and high-precision resistors are extremely difficult to convert into semiconductors in practical terms. When integrating a phase comparison circuit or the like into an integrated circuit, these capacitors and resistors must be externally attached. Therefore, even if integrated circuits were implemented, the effect of miniaturizing the circuits and reducing costs was small and the efficiency was poor.

Therefore, Japanese Patent Laid-Open No. 56-36225 briefly describes a method that does not use a monomulti circuit. It is a phase locked loop (PLL)
In the circuit, a signal obtained by dividing the output of the voltage controlled oscillator by a frequency dividing circuit is used as a signal b for phase comparison,
A gate signal g having a constant phase difference with respect to this signal b is created using the output of the frequency dividing circuit. In order not to use a monomulti circuit at all, the first current source is directly controlled by the input signal a, not by the signal a'.

However, although not mentioned in JP-A-56-36225, the following problem may occur depending on the input signal a. That is, when the pulse width of the input signal a is smaller than the gate signal g, the output becomes saturated when the phase difference becomes large, and the range in which a correct phase difference signal can be obtained becomes narrow. Furthermore, if the duty cycle of input signal a deviates significantly from about 50%, the pull-in range will deviate greatly from the center of the input change of the voltage controlled oscillator, making it difficult for the PLL circuit to lock. This is because in an asynchronous state, the output of the phase comparator that has passed through the loop filter changes within a predetermined range determined by the characteristics of the loop filter, centered on the average potential determined by the duty cycle of the input signal, and this change This is because the range determines the pull-in range.

OBJECT OF THE INVENTION The present invention solves the problems of the conventional phase comparator circuit as described above, and enables efficient integration of the circuit.
It is an object of the present invention to provide a phase comparator circuit that has stable pull-in range characteristics, does not narrow the phase difference output range, consumes little power, and is stable against sudden noise.

Structure of the Invention The present invention provides a phase comparator circuit that constitutes a phase locked loop (PLL) circuit together with a loop filter, a voltage controlled oscillator, and a frequency dividing circuit.
a pulse generating circuit that generates a digital signal A that starts at an edge that compares the phase of an input signal of the phase-locked loop circuit and stops the clock from the voltage controlled oscillator or the frequency dividing circuit after a predetermined number of counts; a gate signal generation circuit that generates a gate signal having a predetermined phase difference with respect to a digital signal B that is an output of the circuit from a signal inside the frequency dividing circuit; and a gate signal generation circuit that specifies the digital signals A and B only during the output period of the gate signal. A first detection circuit detects one state combination A1, B1 of the digital signals A, B, and a first detection circuit detects an inverted combination /A1, /B1 of the state combination A1, B1 of the digital signals A, B only during the output period of the gate signal. 2 detection circuit;
a first power supply operated by the output of the first detection circuit; and a second power supply operated by the output of the second detection circuit; This is a phase comparator configured to connect the output of a power supply and use this as an output terminal for a phase difference signal.

The phase comparator circuit of the present invention has the following effects due to the above configuration.

(a) Since it can be constructed entirely from digital circuits, it is suitable for integrated circuits, and integrated circuits can efficiently reduce costs and miniaturize circuits.

(b) The pulse generation circuit that generates pulses for detecting phase differences only holds the edge of the input signal whose phase should be compared for a predetermined period of time, so even if sudden large noise is input, the circuit can quickly return to normal state. to return to.

(c) The pulse width of digital signal A can always be set larger than the pulse width of the gate signal,
This allows an accurate phase difference signal to be output over a wide range without being affected by the pulse width of the input signal.

(D) Since the duty cycle of digital signal A can be approximately 50%, the PLL can be stably locked without the pull-in range being affected by the duty cycle of input signal a.

(e) Power consumption can be reduced because a phase difference signal is output only during periods when there is a phase difference.

DESCRIPTION OF EMBODIMENTS FIG. 7 is a basic configuration diagram of a phase comparator circuit according to the present invention. In the figure, 19, 20, and 21 are digital input signal A, B and gate signal terminals, respectively; 22 is a first detection circuit that detects one specific state among the combination of states of input signals A and B;
23 is a second detection circuit that detects a state inverted from the detection state of the first detection circuit; 24 and 25 are power supplies; 26 and 27 are switch circuits; 28 is an output terminal for the phase difference output signal OUT3; It is a capacitor. If the first power source 24 is a constant voltage source, the second power source 25 is a constant voltage source with a different voltage output from the first power source 24, and the first power source 24 is a constant current I ₀
The second current 25 is a constant current source of constant current (-I ₀ ).

It is assumed that "1" of the digital signal corresponds to a high level of voltage, and "0" of the digital signal corresponds to a low level of voltage. The first detection circuit 22 has a combination of states of input signals A and B (A, B) = (0, 0), (0, 1),
A specific state of (1, 0), (1, 1), for example, (1, 0) is detected, and the second detection circuit 23
FIG. 8 shows an operating waveform diagram when the inverted state (A, B)=(0,1) is detected.
FIG. 8A shows the waveform of the gate signal, B shows the waveform of the input signal B, and C shows the waveform of the input signal A. The gate signal is a signal having a certain phase difference that can gate the phase comparison edge (here, the rising edge) of the input signal B. The first detection circuit 22 detects A=1 and B=0, resulting in the waveform shown in FIG. 8D, and the second detection circuit 23 detects A=0 and B=1, resulting in the waveform shown in Become. The first power supply 24 has an output voltage
If the second power supply 25 is a constant voltage source with an output voltage of _VH and a constant voltage source with an output voltage of _VL , only the switch circuit 26 is conductive during a certain period of time when the output of the first detection circuit 22 is output, and the voltage
V _H is output, and only the switch circuit 27 is conductive for a period when the second detection circuit 23 outputs, and the voltage V _L
is output, so the waveform of the output signal OUT3 becomes the waveform shown in F. If the phase of the rising edge of input signal A is advanced as shown by the solid line in FIG. 8 based on the rising edge of input signal B, voltage V _H is output only during the phase advance period, as shown by the broken line in FIG. It can be seen that if the phase of the input signal A is delayed, the voltage V _L is output only during the phase delay period. The first power supply 24 is a constant current source with a constant current I ₀ , and the second power supply 2
5 is a constant current source with a constant current (-I ₀ ), and when a capacitor 29 is connected to the output terminal 28 as shown by the broken line in FIG. 7, the first detection circuit 22
During the period when there is an _output of
During the period when there is an _output of
The waveform of No. 3 is the waveform shown in G. If the phase of the rising edge of input signal A advances as shown by the solid line in FIG. 8 based on the rising edge of the input signal, the output signal OUT3 rises only during the phase advance period,
As shown by the broken line in the figure, if the phase of the input signal A is delayed, the potential of the output signal OUT3 drops only during the phase delay period. In the configuration according to the present invention, the switch circuits 26 and 27 are not conductive at the same time, and the output stage circuit consumes power only during the period when there is a phase difference. This has the effect of reducing power consumption. Since the first and second power supplies 24 and 25 may be constant current sources or low voltage sources, they can be selected according to the purpose depending on the IC process. In the explanation of FIG. 8, the combinations (A, B) of the input states detected by the first and second detection circuits are respectively (1,0) and (0,1), but (1,1) and ( 0,0) or (0,0) and (1,1). The only difference is the combination of edges that serve as a reference when performing phase comparison.

Next, an embodiment in which the phase comparison circuit of the present invention is used in a phase-locked loop circuit (hereinafter referred to as a PLL circuit) will be described with reference to FIGS. 9 and 10.
Figure 9 shows a PLL circuit that can stably and accurately obtain a frequency 160 times the horizontal synchronization signal used in a simple video tape recorder.
FIG. 0 is a waveform diagram of each part in the phase comparator circuit portion of the PLL circuit. In Figure 9, 30
is an input terminal for the horizontal synchronization signal, 31 is an output terminal for the phase difference signal, 32 is a loop filter, 33 is a voltage controlled oscillator (hereinafter referred to as VCO), 34 is a 160 frequency divider circuit, and 35 is 160 times the horizontal synchronization signal. This is the output terminal for the frequency of . 36 is a pulse generation circuit, 37, 3
8 is the first and second detection circuit, 39 and 40 are the first,
In the second switch circuit, 41 and 42 are power supply lines, respectively, V _DD line and V _SS line (potential relationship is V _DD
>V _SS Note that one power supply line may be grounded. ), 43 is a gate signal generation circuit. First,
The second detection circuits 37 and 38 correspond to the first and second detection circuits 22 and 23 in FIG. 7, and similarly, the first and second switch circuits 39 and 40 correspond to the first and second switch circuits. 26, 27, power line 4
1 and 42 correspond to power supply circuits 24 and 25.

The pulse generation circuit 36 is a D flip-flop 4.
4. Consists of an AND gate 45 and a counter 46, the D flip-flop 44 operates at the rising edge of the horizontal synchronizing signal, the Q output changes from "0" to "1", the gate 45 opens, and the counter 46
The clock from VCO 33 is input to . Counter 46 resets flip-flop 44 when it has counted a set number of clock pulses. When flip-flop 44 is reset, Q
Since the output is "1" and the output is "0", the gate 45 is closed and the counter 46 is reset, so the pulse generating circuit 36 stops until the next horizontal synchronizing pulse is input. Therefore, the pulse generation circuit 36
starts at the rising edge of the horizontal sync signal,
A pulse E is generated that stops at a timing obtained by counting a fixed number of clock pulses from the VCO 33. Although it can be considered as a type of monomulti circuit, () the timing of the end of the output pulse E is determined by a clock pulse with a varying number of cycles, so the pulse width changes as the frequency of the VCO 33 changes, () horizontal synchronization. Since the signal frequency and the frequency of the VCO 33 are not necessarily in a synchronous relationship, the end timing of pulse E has jitter with respect to the start timing of pulse E, that is, the rise timing of the horizontal synchronization signal. is different. Note that since the timing of the end of pulse E is not the edge for phase comparison, it does not affect the output of the phase comparison circuit. The reason why the pulse width of the input horizontal synchronizing signal is expanded in this way is as follows. The pulse width of the horizontal synchronization signal is about 4 μs to 5 μs, which is narrow compared to the horizontal period of about 64 μs. If the pulse width of the input signal whose phase is compared is narrow compared to the pulse width of the gate signal, as in this horizontal synchronization signal, the phase difference detection signal may become saturated and the correct phase difference may not be obtained, and the phase comparison The input signal duty cycle is too small for 50%. Or, if it is too large, the lock range of the PLL circuit will be biased, causing problems such as this. A circuit for improving this problem is the pulse generation circuit 36.

FIG. 10A shows the waveform of the horizontal synchronizing signal which is the input signal, and FIG. 10B shows the waveform of the output E of the pulse generating circuit 36.

The gate signal generation circuit 43 consists of an RS flip-flop 47 and a timing decoder 48. By decoding the output of the counter of the frequency dividing circuit 34, a timing having an arbitrary phase difference with respect to the output F of the frequency dividing circuit 34, which is a signal whose phase is compared, can be obtained. By setting and resetting the flip-flop 47 using the two timing detection outputs, a gate signal that always has a constant phase difference with respect to the phase comparison input signal F is obtained regardless of changes in the frequency of the VCO. The frequency dividing circuit 34 is 160
Since it is a frequency dividing circuit, there are timings from 0 to 159. Assume that the output F of the frequency dividing circuit 34 is "0" for a period from timing 0 to timing 127 and "1" for a period from timing 128 to timing 159, and the decoder 48 outputs a signal at timing 1.
18 and 138 are configured so that the flip-flop 47 is set at the detection timing 118 and reset at the timing 138, the output F of the frequency divider circuit 34 and the gate signal are respectively shown in FIG.
Shown in D.

The first detection circuit 37 is an inverter 49, AND
Consists of gates 50 and 51, the gate signal is "1"
E=1 and F=0 are detected only when .

The second detection circuit 38 is an inverter 52, AND
Consists of gates 53 and 54, gate signal is "1"
E=0 and F=1 are detected only when .

The first switch circuit 39 is connected to an inverter 55, P
Consists of channel MOS transistor 56,
Only when the output of the first detection circuit 37 is "1", the P channel MOS transistor 56 becomes conductive, and the potential of the output terminal 31 becomes approximately _VDD .

The second switch circuit 40 is an N-channel MOS
A second detection circuit 38 consisting of a transistor 57
Only when the output is "1", the N-channel MOS transistor 57 becomes conductive, and the potential of the output terminal 31 becomes approximately V _SS . Figure 10 Gate 50
The output waveforms of the gate 53, the gate 51, the gate 54, and the terminal 31 are shown in FIG.
In FIG. 12, the phase of the horizontal synchronizing signal is determined by the frequency dividing circuit 34.
The solid line indicates the operating waveform when the output F is advanced based on the respective rising edges, and the broken line indicates the operating waveform when the phase is delayed. As is clear from the figure, the V _DD potential is output only during the phase advance period, the V _SS potential is output only during the phase lag period, and it can be seen that the phase difference between the two inputs E and F is output accurately.

As described above, according to this embodiment, the phase difference output circuit operates only during the period when there is a phase difference due to the first and second detection circuits 37 and 38, so power consumption can be reduced, and the time constant The required phase,
By configuring the pulse width using a digital circuit using a clock pulse from the VCO, a phase comparator circuit can be configured that does not require adjustment or external components, and is an integrated circuit that uses a small and inexpensive package with a small number of pins. This allows cost reduction and circuit miniaturization to be carried out efficiently. In addition, if the output pulse width of the pulse generation circuit 36 is set to be more than half the period H of the horizontal synchronization signal within the range of VCO change, equalization pulses arranged at intervals of 1/2H in addition to the horizontal synchronization signal, Even if a composite synchronization signal including a vertical synchronization signal is input to the pulse generation circuit 36 instead of a horizontal synchronization signal, only the horizontal synchronization signal is output, so that a horizontal synchronization signal separation function can be provided. Further, since the pulse generating circuit 36 does not receive input during the pulse output period, it is not affected by noise during the pulse output period. Furthermore, the pulse generation circuit 36
Since the input signal retains the arrival of the edge whose phase should be compared only for a predetermined period of time, even if an erroneous phase difference signal is output due to noise, the normal state can be quickly restored. It has many advantages and is highly effective in practical use.

Effects of the Invention By using a pulse generation circuit, the phase comparator circuit of the present invention can be efficiently integrated into a circuit, has stable pull-in range characteristics, does not narrow the phase difference output range, and is resistant to sudden noise. In addition, the power consumption can be reduced by operating the power supply only during the period when there is a phase difference, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional first phase comparator circuit,
Figure 2 is a state transition diagram of the in-phase comparison circuit, Figure 3 A to F are operational waveform diagrams of the in-phase comparison circuit, and Figure 4 I to F are operational waveform diagrams of the in-phase comparison circuit.
E is an operation waveform diagram when a sudden noisy signal is input to the in-phase comparison circuit, Figure 5 is a configuration diagram of the conventional second phase comparison circuit, and Figure 6 is the operation of the in-phase comparison circuit. Waveform diagrams, FIG. 7 is a basic configuration diagram of the present invention, FIG. 8 I to I are operational waveform diagrams of the same embodiment, and FIG.
The figure is a circuit diagram of a PLL circuit using a phase comparator circuit according to an embodiment of the present invention, and FIG. 10 is an operational waveform diagram in the same embodiment. 22, 37...first detection circuit, 23, 38...
...Second detection circuit, 24...First power supply, 25...
...Second power supply, 26, 39...First switch circuit, 27,40...Second switch circuit, 43...
...Gate signal generation circuit.

Claims (1)

[Claims] 1. In a phase comparator circuit that constitutes a phase-locked loop circuit together with a loop filter, a voltage-controlled oscillator, and a frequency divider circuit, starting at the edge where the phase of the input signal of the phase-locked loop circuit is compared, A pulse generating circuit that generates a digital signal A that stops the clock from the circuit after a predetermined number of counts, and a pulse generating circuit that has a predetermined phase difference with respect to the digital signal B that is the output of the frequency dividing circuit and has a pulse width that is greater than the pulse width of the digital signal A. a gate signal generating circuit that generates a gate signal having a small pulse width from a signal inside the frequency dividing circuit; and a gate signal generating circuit that detects one specific state combination A1, B1 of the digital signals A, B only during the output period of the gate signal. 1 detection circuit, and the digital signal A, only during the output period of the gate signal.
State combination A1 of B, inverted combination of B1/A
1, /B1, and a first detection circuit that is operated by the output of the first detection circuit.
and a second power supply operated by the output of the second detection circuit, the output of the first power supply and the output of the second power supply are connected to output a phase difference signal. A phase comparison circuit characterized by having a terminal.