JPS602631B2 - Pulse selection erase gate circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse selection and cancellation gate circuit, and more particularly to a pulse selection and cancellation gate circuit for removing false pulse signals generated in a small radar sensor due to radio wave interference that performs frequency reduction.

Generally, small radar sensors using the OW Doppler radar system are used to detect the presence of targets approaching at relative speeds around the speed of sound, but these small radar sensors currently in use do not have countermeasures against radio wave interference that causes frequency distortion. Since no modifications were made, there was a problem with malfunctions.

For this reason, the inventor of the present invention invented a small radar sensor with a malfunction prevention function shown in FIG. 1 as having the function of preventing the above-mentioned malfunction, and has filed a simultaneous application. In FIG. 1, an antenna 2 is connected to an excited oscillator 1 that generates a high-frequency signal.
is connected, and a high frequency signal is radiated into space from this antenna 2.

At the same time, the self-excited oscillator 1 receives, via the antenna 2, reflected waves from the target that occur when the target approaches the antenna 2. Further, a wideband amplifier 3 is connected to the self-excited oscillator 1 in order to amplify fluctuations in the consumption flow (autodyne detection output) caused by reflected wave signals and the like. This wideband amplifier 3 has a bandwidth that allows passing both the Doppler repeat signal generated by approaching the target and the necessary portion (usually 100 KHz to IMHz) of the beat signal generated by interference radio waves. Then, the output of the wideband amplifier 3 is applied as an input signal a to a pulse selection cancellation gate circuit 6 via a low frequency filter 4 whose cutoff frequency is set so as not to pass the latter beat signal, and a waveform shaping circuit 5. That is, a Doppler repeat signal indicating the approach of a target and a low-frequency false signal due to interference radio waves are input as the input signal a of the pulse selection/elimination gate circuit 6. On the other hand, the output of wideband amplifier 3 is also applied to bandpass amplifier 7. This Obijo amplifier 7 extracts and amplifies only the beat signal caused by interference radio waves,
It is supplied to the pulse selection/elimination gate circuit 6 as an opening/closing signal b via a waveform shaping circuit 8. The pulse selection/elimination gate circuit 6 is configured to remove the false signal when a false signal arrives as an input upon receiving the opening/closing signal b, and to operate the trigger circuit 9 by passing only the pulse due to the original Doppler repeat signal. It's summery. In the above configuration, when a target approaches when there is no radio wave interference, the eye-exciting oscillator 1 causes fluctuations in its current consumption due to the reflected wave signal from the target, and the output of the broadband amplifier 3 is a low-frequency Doppler beat signal. This is waveform-shaped by the waveform shaping circuit 5 and becomes the input signal a of the pulse selection erase gate circuit 6.

At this time, since there is no beat signal due to interference radio waves, the opening/closing signal b of the pulse selection/elimination gate circuit 6 is zero. That is, both signals a and b have a relationship as shown in FIG. 2A and B. In this case, the pulse selection/elimination gate circuit 6 is opened, the trigger circuit 9 is activated, and a trigger signal indicating that the target has approached is outputted to the output terminal 101.
On the other hand, if there is an interfering radio wave that sweeps the frequency,
A beat signal having a frequency difference between the interference radio wave signal and the high frequency signal of the self-excited oscillator 1 is generated.

This beat signal continues until the frequency of the interfering radio wave approaches the frequency of the self-excited oscillator 1 and a pull-in phenomenon occurs,
At the time when the self-excited oscillator 1 is pulled in, the frequency of the self-excited oscillator 1 matches the frequency of the interference radio wave, and the beat signal no longer appears because it continues to be dragged along by the dark interference radio wave. When the beat signal disappears, interference radio waves cause fluctuations in the current consumption of the self-excited oscillator 1, and as a result, a false signal similar to the signal generated when the main button approaches the target appears. As the frequency of the interfering radio waves changes further, it will eventually reach the limit of the pull-in, and the pull-in will no longer be possible. As a result, the self-excited oscillator 1
Based on the difference in the frequency of the interfering radio waves, the beat signal is generated again. This beat signal is selectively amplified by the Obishiro amplifier 7, then waveform-shaped by the waveform shaping circuit 8, and is applied to the pulse selective erasure gate circuit 6 as an opening/closing signal b. On the other hand, the false signal passes through a low frequency filter 4, is waveform-shaped by a waveform shaping circuit 5, and is applied as an input signal a to a pulse selection erasure gate circuit 6. At this time, the relationship between both signals a and b is as shown in FIGS. 3A and 3B. In this way, when a false signal pulse is applied as the input signal a, two lucky pulses appear immediately before and after the false signal as the opening/closing signal b. The pulse selective erase gate circuit 6 is closed for a period between at least two pulses to remove false signal pulses, thereby preventing malfunctions due to turtle wave interference. Now, as the above-mentioned pulse selective erase gate selective erase gate circuit 6, a configuration as shown in FIG. 4 has conventionally been proposed.

In this figure, an input signal a is supplied to an input signal terminal 11, and this input signal a is inverted by an inverter 12 and applied to a monostable multipipulator 13. This monostable multipipelator 13 is provided for time delay, and drives the monostable multipipelator 14 after a predetermined delay time has elapsed. Therefore, the monostable multivibrator 4 generates a pulse having a predetermined delay with respect to the pulse arriving at the input signal terminal 11, and applies it to the AND gate 16 via the inverter 15. On the other hand, AND gate 1 6
The opening/closing signal b supplied to the opening/closing signal terminal 17 is
is inverted by an inverter 18 and added. This AND
The output of the gate 16 is sent to the gate output terminal 20 via an AND gate 19 which receives the output of the inverter 112. In the above configuration, an input signal pulse having a pulse width To as shown in FIG. 5A is input to the input signal terminal 11.
When a pulse is input to the AND gate 16, a pulse as shown in FIG. Added.

If there is no radio wave interference, no pulse will arrive at the switching signal input terminal 17, so the output of the inverter 18 is "1", and the pulse with the width L is passed through the AND gate 16 to the NA
The signal is transmitted to ND gate 19. At this time, since the other inputs of the NAND gate 19 are "1", the NAND
A gate output terminal 20 is used as a trigger signal to notify the presence of a target in the vicinity of the pulse having the same width as inverted by the D gate 19.
Sent from On the other hand, if there is an interference radio wave that stripes the frequency, an input signal pulse with a width To as shown in FIG. 5A arrives at the input signal terminal 11, and at the same time
The switching signal b, which is a pulse of 3.2 and whose falling edge and second rising edge of the first pulse coincide with the rising and falling edges of the pulse having the width To, respectively, is input to the switching signal input terminal 17. Arrival.

In this case, when the pulse of width T2 shown in FIG. do not have. This prevents malfunctions. By the way, in order for the above erasing operation to be executed correctly, the pulse of width T2 in FIG.
It is necessary to adjust the delay times T, L of each monostable multipipelator 13, 14 so that the pulses are included inside the width circle pulse in FIG.

However, the pulse width T of the input signal a changes depending on the relative speed to the target and the size of the target, and the pulse width T3 of the opening/closing signal b changes depending on the strength of the interfering radio waves and the speed of the sweep repetition frequency. In this case, it is impossible to satisfy the above conditions. For example, if the sweep repetition frequency of the interfering radio wave becomes faster, the pulse width L becomes shorter, and there is a risk that it will not be possible to eliminate false signals.If the pulse width To becomes larger than the delay time T, the real trigger signal will also be erased. There is. It is an object of the present invention to provide pulse selective erasure that eliminates the above-mentioned disadvantages, eliminates the need for time-based waiting adjustments, uses the order of arriving pulses as the basis for selective erasure operation, and improves performance and stabilizes operation. To provide gate circuit.

Embodiments of the pulse selective erase gate circuit according to the present invention will be described below with reference to the drawings.

In FIG. 6, the input signal a from the input signal terminal 11 is applied to the non-inverting input of the AND gate 21, and the opening/closing signal b from the opening/closing signal terminal 17 is applied to the inverting input thereof.

The output of the AND gate 21 is applied to a counting input terminal CK of a 1-bit binary counter (flip-flop) 22. As a result, when the open/close signal b is in the rOJ state, the pulse of the input signal a is transmitted to the input terminal C of the binary counter 22.
K, and its output terminal Q^ is set to "1". On the other hand, the open/close signal b from the open/close signal terminal 17 is applied to the non-inverting input of the AND gate 23, and the input signal a from the input signal terminal 11 is applied to the inverting input thereof.

The output of the AND gate 23 is applied to the input terminal S of the 2-bit shift register 24 and also to the clock input terminal CK. Therefore, when the input signal a is in the "0" state, the open/close signal b enters the input terminal S of the shift register 24, which appears at the first stage output terminal Q^ and then at the second stage output terminal Q8. . The AND gate 26 receives the output from the output terminal Q^ of the binary counter 22 as a non-inverting input, and receives the output from the output terminal Q^ of the shift register 24 as an inverting input. As a result, the AND gate 26 sends the output of the binary counter 22 as a trigger signal to the gate output terminal 201 when the output terminal Q^ of the shift register 24 is in the "0" state. Further, the output of the binary counter 22 and the output from the output terminal Q8 of the shift register 24 are applied to a NAND gate 27.
The monostable multipipulators 28 and 30 are driven by the output of 7.

This monostable multipipulator 28 generates a reset pulse, and the reset pulse is sent to the clear terminal CL of the shift register 24 via an AND gate 29.
The output of the NAND gate 27 is also branched and applied to the clear terminal CLR of the binary counter 22 to reset both. Furthermore, in order to stabilize the circuit operation, a binary counter 25 is provided, whose input terminal CK is connected to the input signal terminal 11, and this clear terminal CLR is connected to the open/close signal terminal 17, and its output terminal Q^
is connected to the non-inverting input of AND gate 29. In the above configuration, if there is no radio wave interference, when a pulse of the input signal a as shown in FIG. , set its output terminal Q^ to "1"
Set to .

At this time, since no pulse arrives at the opening/closing signal terminal 17, the output terminals Q^ and QB of the shift register 24 are at "0". Therefore, the binary counter 2 as shown in Figure 7B
The output of 2 passes through the AND gate 26 and is sent to the gate output terminal 20. This serves as a trigger signal that indicates the presence of a nearby target. On the other hand, when there is frequency-sweeping radio wave interference, a false signal pulse as shown in Figure 7C appears at the input signal terminal 11, and at the same time a two-lotus pulse as shown in Figure 7D appears at the open/close signal terminal 17. .

Therefore, due to the arrival of the first pulse shown in ○ in Fig. 7, E in Fig. 7
The output terminal Q^ of the first stage of the shift register 24 is "
1". Then, the false signal pulse of FIG. 7C causes the seventh
As shown in Figure F, the output terminal Q^ of the binary counter 22 is “1”.
” However, since the AND gate 26 is in the cutoff state, no trigger signal appears on its output side. As a result, malfunctions due to false signals are prevented. After that, the second pulse indicated by ◯ in FIG. 7 arrives, and as a result, both the output terminals Q^ and QB of the shift register 24 become "1". As a result, the monostable multipipulators 28 and 30 are driven,
The reset pulse as shown in Fig. 7G is sent to the binary counter 22.
, in addition to the shift register 24. Then, prepare for the arrival of the next pulse. As explained above, in the above embodiment, the pulses of the input signal a and the pulses of the switching signal b are temporarily stored in the order in which they arrive, and the order of arrival is used as the basis for the pulse selection criteria, so that the frequency of the interfering radio waves can be calculated. It is possible to respond correctly regardless of repetition, frequency, target size, etc. Therefore, it is possible to significantly improve characteristics and reliability. FIG. 8 shows another embodiment of the invention.

In this figure, an AND gate 31,
32 is added. That is, the output of the binary counter 22 and the output of the output terminal Q^ of the shift register 24 are applied to the non-inverting input of the AND gate 31, and the input signal a and the open/close signal b are applied to the inverting input. The output of this AND gate 31 is applied to the clear terminal CLR of the shift register 24 via an AND gate 32. According to this embodiment, due to accidental radio wave interference, a single opening/closing pulse as shown in FIG. 9B arrives before the true input signal pulse shown in FIG. 9A, and the output terminal Q^ of the shift register 24 is Even if it becomes "1" as shown in FIG. 9D, a reset pulse as shown in FIG. 9C is generated at the output of the AND gate 31 at the falling edge of the input signal pulse, and the shift register 24 is reset.

Therefore, at the same time as the output of the output terminal Q^ shown in FIG. Therefore, it is possible to reliably prevent malfunctions caused by accidental radio wave interference that may cause the true signal to be erased in the embodiment shown in FIG. 6 described above. As described above, according to the present invention, by making the order of arriving pulses the basis of the selective cancellation operation, false pulses can be canceled regardless of the frequency of the frequency sweep of the interfering radio wave, the size of the target, etc. Thus, a pulse selective erase gate circuit with improved performance and stable operation is obtained.

[Brief explanation of drawings]

Figure 1 shows a block of a small radar sensor with a malfunction prevention function to which the present invention is applied. , Figures 2A and B are waveform diagrams showing the signal waveforms supplied to the pulse selection and cancellation gate circuit when there is no radio wave interference, and Figures 3A and B are pulse selection when there is interference radio waves for frequency sweeping. A waveform diagram showing the signal waveform supplied to the erase gate circuit, FIG. 4 is a block diagram of a conventionally proposed pulse selection erase gate circuit, and FIGS. 5 A, B, and C are waveform diagrams for explaining its operation. , FIG. 6 is a block diagram showing an embodiment of the pulse selection erase gate circuit according to the present invention, FIG. 7 is a waveform diagram for explaining its operation, and FIG. 8 is a block diagram showing another embodiment of the present invention. 9 are waveform diagrams for explaining the effect. 6... Pulse selection erase gate circuit, 11... Input signal terminal, 21, 23, 26, 29
, 31, 32...AND gate, 22, 25.../
ゞInary counter, 24...Shift register, 27.
...NAND gate, 28,30...monostable multipipulator. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure l6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1 receives the input signal a and the opening/closing signal b, and receives the opening/closing signal b.
a first gate element 21 that allows the pulse of the input signal a to pass in a state where the pulse of the input signal a has not arrived; A second gate element 23 that passes the pulse of the opening/closing signal b, a 1-bit temporary memory circuit 22 that receives the pulse of the input signal a that has passed through the first gate element 21, and the second gate element 23. A 2-bit temporary memory circuit 24 that receives the pulse of the passed opening/closing signal b, an output terminal Q_A of the 1-bit temporary memory circuit 22, and an output terminal Q_A of the first stage of the 2-bit temporary memory circuit 24.
a third gate element that receives the output of the first stage and enters a cutoff state when the output of the output terminal Q_A of the first stage indicates that the first pulse of the opening/closing signal b has arrived immediately before the pulse of the input signal a; 26, and the 1-bit temporary storage circuit 2
2 output terminal Q_A and the 2-bit temporary storage circuit 2
4, the output of the second stage output terminal Q_B indicates that the second pulse of the opening/closing signal b has arrived immediately after the pulse of the input signal a. a reset pulse generation circuit that generates a reset pulse that clears the 1-bit temporary storage circuit 22 and the 2-bit temporary storage circuit 24 when the 1-bit temporary storage circuit 22 and the 2-bit temporary storage circuit 24 indicates that the pulse of the opening/closing signal b has not arrived, the output terminal Q of the 1-bit temporary storage circuit 22
A pulse selection erase gate circuit characterized in that the output of _A is passed through the third gate element 26 and sent out as a trigger signal.