JPS6026238B2 - Code conversion circuit for driving 7 segment display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code conversion circuit that converts the count output code of a counter circuit into a code for driving a 7-segment display device, and in particular, it is capable of converting the count output code of some different counter circuits. The present invention relates to a code conversion circuit for driving a 7-segment display device.

FIG. 1 is a circuit configuration diagram showing an IQ Hayabusa counter circuit 3 consisting of a binary counter 1 and a quinary counter 2 as an example of a counter circuit, and FIG. 2 is a circuit diagram showing this decimal counter circuit 3.
3 is a time chart showing the transition state of count output codes Q, to Q4 when clock pulses are sequentially counted in FIG.

Furthermore, FIG. 3 is a circuit configuration diagram showing a hexadecimal counter circuit 6 consisting of a binary counter 4 and a hexadecimal counter 5.
FIG. 4 shows this hexadecimal counter circuit 6. Count output code Q, ~Q when sequentially counting clock pulses J
4 is a time chart showing the transition state of No. 4. As is clear from the time charts of FIG. 2 and FIG.
4 is equal. However, if the count output "0" of the IG Hayabusa counter circuit 3 is expressed by a count output code, then Q, = Q2
=Q=Q4="1", whereas in the hexadecimal counter circuit 6, this count output code is the count output r2
”. Furthermore, the hexadecimal counter circuit 6 is 10
The advance counter circuit 3 outputs a non-existent count output code. For this reason, conventionally, the above 1G ship counter 3
The 4-bit count output code outputted from the hexadecimal counter circuit 6 is divided into seven display segments a to g formed in the shape of a Japanese character, as shown in FIG.
In order to convert the code for driving the segment display device, separate code conversion circuits for decimal and decimal were required. Therefore, if the same device has a hexadecimal counter circuit and an IQ Hayabusa counter circuit, and it is not necessary to display the count outputs of both counter circuits at the same time, the code conversion circuit that converts the count output code of one counter circuit is It will be wasted. Furthermore, providing a code conversion circuit for each counter circuit with a different count number is extremely disadvantageous in terms of manufacturing costs. This invention was made in consideration of the above-mentioned circumstances, and its purpose is to create a common 7-segment display that can convert the count output codes of several counter circuits with different count numbers into codes for driving a display device. An object of the present invention is to provide a code conversion circuit for driving a device.

Hereinafter, with reference to the drawings, an embodiment of the present invention will be described, in which the IG Hayabusa counter circuit 3 shown in FIGS.
A code conversion circuit commonly used in the hexadecimal counter circuit 6 and the hexadecimal counter circuit 6 will be explained.

FIG. 6 is a circuit configuration diagram showing a detection section, and this detection section is of the so-called 〇M06 type (clock A NAND gate 10 (complementary MOS type), an inverter 11 for inverting the output signal of the NAND gate 10, a drain (source) connected to a connection point between the output terminal of the NAND gate 10 and the input terminal of the inverter 11; It is composed of a p-channel MOS transistor 12 whose source (drain) is connected to the application point of power supply voltage Voo. And the above M
The gate of the OS type transistor 12 has a "1" level when converting the count output code output from the IG Hayabusa Kawanta circuit 3, and a level "1" when converting the count output code output from the hexadecimal counter circuit 6. “0” to
An inverted conversion switching signal TD, which is an inversion of the conversion switching signal TD serving as the level, is supplied. Furthermore, the two clock input terminals of the NAND gate 10 are supplied with the conversion switching signal TD and the inverted conversion switching signal TD, respectively. Furthermore, the output terminal of the above Nando game 10 and the inverter 1
The signal 0 at the connection point with the input terminal of the inverter 1 and the signal at the output terminal of the inverter 11 are respectively supplied to the correction circuit section. 7th
The figure is a circuit configuration diagram of a code conversion section and a correction circuit section, and the code conversion section and correction circuit section are connected to the power supply voltage V.

. It is composed of a plurality of p-channel and n-channel MOB type transistors wired in a matrix between an application point and a power supply voltage Vss application point. To explain this configuration in detail below, an n-channel MOS transistor (hereinafter n - abbreviated as Tr) n, and p channel MO
S-type transistors (hereinafter abbreviated as p-Tr) p, are connected in series. Similarly, Vss point and V. . Between the points are n-Trn2 and p-Trp2, n-Trn3 and p-T.
rp3, n-Tr mountain and p-Trp5 are each connected in series. Furthermore, between the vertical Vss and the terminal 20, n-T
A series circuit consisting of rn5 to n7 and an n-Tr ratio to n, . Series circuits consisting of are connected in parallel. Similarly, between Vss and the terminal 21, n-Trn. A series circuit consisting of 2 to n, 5 and a series circuit consisting of n-Trn, 6 to n, 9 are connected in parallel. Between the Vss point and terminal 22,
A series circuit consisting of an n-Trn fox, an n-Tr Buddha, and an n-devil are connected in parallel. Between the Vss point and the screw 23, a series circuit consisting of n-Trns 25 to n27, a series circuit consisting of n-Trs 8 to n3, and an n-Tr ratio 2 to n3 are connected.
5 series circuits are connected in parallel. Between the Vss point and the terminal 24, there are a series circuit consisting of n-Tr~6~n bait, a series circuit consisting of n-Tr side 9~mount, a series circuit consisting of n-Tr mountain 2~n44, and n- Trn flight ~ Yama 7
Series circuits consisting of are connected in parallel. Between the Vss point and the terminal 25, there is an n-Trn axis and n-Trn49 to
A series circuit consisting of n5, a series circuit consisting of n-Trn 4 and a series circuit consisting of n-Trn 8 are connected in parallel. Between the Vss point and the terminal 26, there is a series circuit consisting of n-Trn to n-Tr, and an n-Tr.
Series circuit consisting of n63 to 6 and n-Tr 7 to n
A series circuit consisting of 7 and 7 is connected in parallel. Furthermore, p-Tr is ~p7 between the terminal 20 and the Voo point.
A parallel circuit consisting of p-Trp8~p, . Parallel circuits consisting of are connected in series. In addition, the terminal 21 and Vo
A parallel circuit consisting of p-T[p8 to p,5 and a parallel circuit consisting of p-Trp,6 to p,9 are connected in series between point o. Between the terminal 22 and the V point, there is a p
A parallel circuit consisting of -Trp1, p-Trp2, and -p24 is connected in series. Between the terminal 23 and the Voo point, there is a parallel circuit consisting of p-Trp25 to p27;
A parallel circuit consisting of p-Trp28 to p and p-Tr
Parallel circuits consisting of p32 to p35 are connected in series. said terminal 24 and VD. Between the points, p-Trp3
A parallel circuit consisting of p-Trp 6 to p38, a parallel circuit consisting of p-Trp39 to p-ri, a parallel circuit consisting of p-Trp42 to p44, and a parallel circuit consisting of p-Trp street to p47 are connected in series. Between the terminal 25 and the Voo point, there is a parallel circuit consisting of p-Trp 48, p-Tr p field ~ body, a parallel circuit consisting of p-Trp moth ~ p54, and p-Tr body 5 ~ snake 6. Parallel circuits are connected in series. said terminal 26 and V. . Between the points, p-T
Parallel circuit consisting of r technique 9~p6, p-Trp62~
Parallel circuit consisting of p mother and p-Trp65 to p68
Parallel circuits consisting of p-T are connected in series, and p-T
rp69 is connected. and said n1 Trn2o
, L6 and the gates of p-Trp2o and p48 are supplied in parallel with a signal Q outputted from the correction circuit section via a terminal 27. Furthermore, the n-Tr n,, Takumi, n, 2, n25, 28, ratio 6, n39, mountain 2, mountain 9,
Takumi 5, n-board, ratio 8 and p-Trp,, technique, p, 2, P
turbidity, P crab, P $, P false, P bamboo' P place, Q monkey' Pji9
' The inverted code Q of the count output code Q of the 1G ship counter circuit 3 or the hexadecimal counter circuit 6 is supplied in parallel to the gates of seats P62 and P through the terminal 28, respectively. Said n-Tr payment, ~. n, 3, n1
7'&2'~9'n33, mountain 3, naki, n52, Takumi 6,
n69 and p-Tr p2,p9,P,3,PI? ，
P-Ko'P29'P33'P8'P45'Toki2'Mr.6,
The gate of p66 has the count output code Q2 of the 1G ship counter circuit 3 or the hexadecimal counter circuit 6, respectively.
An inverted code Q2 of V is supplied in parallel through the terminal 29. Said n-Tr n3,nl. , n14, n1
8, nyu, Hi 4, n Ko, ~6, Takumi 7, n7. and p-
Tr p3, P・o, P・4'P18'P3 and P side P4
The inverted code Q3 of the count output code Q3 of the IG Hayabusa counter circuit 3 or the hexadecimal counter circuit 6 is supplied in parallel to the gates of the 4'P side horses 7 and P67 via the terminal 30. . Said n-Tr 〜,n,9,
~,, n4,, n plaque, p7, and p-TrP4'PI
9'P31'P skin Qyellow and p magnetic gates are connected to the inverted code Q4 of the count output code Q4 of the IG Hayabusa counter circuit 3 or the hexadecimal counter circuit 6 in parallel via the terminal 31. has been done. Furthermore, the n-Tr
The connection point A between n, and p-Trp is the n-Trn8
, n, 6, na, scold 2, n iso and p-Trp8, p
,6, p2,. It is connected in parallel with the gates of p32 and p. The connection point between the n-Tr mountain and p-Trp2 is the n-Trn6, mountain 6, n4o, and Takumi. " is connected in parallel with the gates of n-Tr and p-Tr p6, p26, p4., p-law, p6o, p63. The connection point between n-Tr~ and p-Trp3 is , the n-Tr ratio, n23, n27' touch 7'n51' skill 3
, n62, n mother and p-Tr p7, p23, p27
, p illusion, k, , Q insect, p nail, p64 The connection point 2 between the n-Tr mountain and p-Trp4, which are arranged in parallel with the respective gates, is connected to the n-Trn, . ,n・5,n24'n
35'n crab'~7, store 4 and p1Tr p,. , P.
5'P24'P35' p-side p47 is connected in parallel to the gates of each body 4. Furthermore, the n-Tr is 9,n
63, each gate of Buddha 7 and p-Trp69,
A signal Q outputted from the correction circuit section is supplied in parallel via a terminal 32. and the terminals 20-2
6 outputs codes a to g for driving the display device. Next, the operation of the circuit configured as described above will be explained.

First, the code converter and correction circuit shown in FIG.
A case will be described in which the count output codes Q, -Q output from the G ship counter circuit 3 are converted into codes a - g for driving the display device. When converting the count output codes Q, -Q4 output from the 1G ship counter circuit 3, a clock input device is applied to one of the gate of the MOS transistor 12 and the NAND gate 10 of the detection section shown in FIG. 6, respectively. an inverted conversion switching signal TD,
The conversion switching signal TD supplied to the other clock input device of the NAND gate 10 is at the "0" level and the "1" level, respectively.

The conversion switching signal TD and the inverted one conversion switching signal TD supplied to the two clock input terminals are respectively at "0" level, '11
" level, the output state of the NAND gate 17 becomes a high impedance state regardless of the supplied count output codes Q, -Q4.

On the other hand, at this time, since the conversion switching signal TD of "0" level is input to the gate of p-Tr12, this p-T "
12 is conductive. As a result, the signal at the output end of the NAND gate 10, ie, Q, is held at the "1" level (Vop level). Further, the output signal of the inverter 11, that is, the signal output, is held at the "0" level, contrary to the signal Q mentioned above. “0” level and “1” level signals Q and Q
are input to terminals 27 and 32, respectively, in the code converter. By inputting the signal Q of "0" level to the terminal 27, this signal Q is input to the gate n-Trn2.
o, n48 are each in a non-conducting state, while this signal Q
p-Trp2o and p48, which are input to the gate, are respectively in a conductive state. Furthermore, by inputting a signal Q of "1" level to the terminal 32, this signal Q is input to the gate n
-Trn59, mountain 3, and n67 are each in a conductive state. On the other hand, the p-Trp spots to which this signal Q is input to the gate become non-conductive. Next, a case will be described in which the count output code Q,=Q2=Q=Q="1" level corresponding to the "0" count state of the 1G ship counter circuit 3 is converted under such a state.

Count output code Q corresponding to “0” count state,
When ~Q4 are each at the "1" level, the inverted codes Q and ~Q4 input to the terminals 28-31 of the code converter and correction circuit shown in FIG. 7 are respectively at the "0" level. “0
``When the level inversion code Q, ~Q4 is input, p-T
r false, p9, p,. , and n-Tr is, ~,n,.
becomes non-conductive, and the terminal 20 has the above p-Tr body, p9,
Voo level is output via pm. As a result, the code a at the terminal 20 becomes the "1" level. Furthermore p1T
r p, 2 to p, 4, Fn to p, 9 are conductive, and n-Tr
n, 2 to n, 4, n, 7 to n, 9 become non-conductive, and the terminal 21 has the above p-Trp, 2 to p, 4, p, 7 to p, 9.
The code b of the terminal 21 becomes "1" level because the Voo level is outputted through the terminal 21. Similarly, p-Trp22
becomes conductive, and n-Trn22 becomes non-conductive. Also, since the p-Trp and n-Trn have already become conductive and non-conductive, respectively, the p-Tr and p2 are connected to the terminal 22.
, p2o, the Voo level is output. As a result, the code c at the terminal 22 also goes to the "1" level. Similarly, p-Trp illusion, p cooperation p3,, p33, p34 are conductive, n-Tr mountain 5, Buddha 8~touch,, ratio 3, ~4 are non-conductive, and the terminal 23 has the above-mentioned p-Trp25, p28-p3,
, p33, and the VoD level is outputted through the p box. As a result, the code d output from the terminal 23 also becomes the ``1'' level.Furthermore, when the inverted codes Q, ~Q of the ``0'' level are similarly input, the p-Trp36, p mother, P41
, P side~P44'P45'p marriage is conductive, n-Tr~6
,~9'mountain・'~2~n axis mountain 5, n marriage becomes non-conductive,
The terminal 24 has the above p-Trp36, p39, p4,, p
The Voo level is outputted through 42 to p45, p45, and p46. As a result, the code e at the terminal 24 becomes "1" level. Furthermore, p-Trp side p52, snake 5 to P spots are conductive, n-Tr stop 9, n spot, and master 5 to 8 are non-conductive, and p-Trp crab and n-Trn crab are already conducting and non-conducting, respectively. Since it is conductive, the above p-Trp48 is connected to the terminal 25.
, p49, p52, and the Voo level is outputted through the output signals 5 to 8. As a result, the code f at the terminal 25 also goes to the "1" level. In addition, p-Trp, ~p3 to which the "0" level inversion codes Q, ~Q are input to the gates are conductive, and n-Trn, ~n3, to which the inversion codes A to C are input to the gates are conductive.
becomes non-conducting. As a result, the above points A to C are each "1"
level, and this "1" level signal inputs n-T
2 of rn are respectively suitable. Further, the n-Trs to which the "1" level signal Q is inputted to the gates are 9, . Further, at this time, signals of the "1" level are also input to the gates of the p-Trs p8 to p8, respectively, so these p-Trs s to p6 become non-conductive. Also “1
Since the p-Trp 69 to which the level signal Q is input to the gate is already non-conductive, the terminal 26 is connected to the above n-T.
The Vss level is output through the pins 2 and 2. As a result, the code g at the terminal 26 becomes "0" level. That is, the conversion switching signal TD is set to "1" level, and the count output code Q, ~Q4 (Q, = Q2 = Q
3=Q4=“1” level), each of the display device drive codes a to “1” level becomes “1” level, and only code g becomes “0” level.The codes a to “3=Q4=“1” level) obtained in this way become “1” level. At g, “1” level is lit, “0”
When the levels are associated with the non-lighting state, "OJ" is displayed on the display shown in FIG. " level to "0" level. In response to the inversion of the code Q, the inverted code Q, which has been input to the terminal 28, is inverted from the "0" level to the "1" level. n-Trn, which has been non-conducting until now, Takumi, n・21n25'n finished'
n illusion・~9'mountain 2'~9' is 5, ratio 4, n spot is conductive,
On the contrary, p-Trp,, Mr., p
,2,P turbidity,P28,P36,P mother,P42,P Tsuru,P
55, p62, and p degrees are respectively non-conductive. As a result, until now Vo. Terminal 2 connected to the point, n-Tr
is connected to the Vss point via the ratio. That is, terminal 2
The code a output from 0 is inverted from the "1" level to the "0" level. Similarly, terminal 23 is n-Tr 5 to 7.
It is followed to the Vss point via. Also, the terminal 24 is n-T
Connected to Vs3 point via rn36~n, terminal 25
is connected to the Vss point via n-Trn49 to n5. Furthermore, the terminal 21 is p-Trp・3, p, 4, p, 6
~p,9 remains connected to the VoD point, and the terminal 22 also remains connected to the V addition point via p-Trp22, p2o. Terminal 26 is n-Trn63~n
66 to the Vss point. As a result, after the one-shot Hayabusa counter circuit 3 counts one clock pulse, only the codes b and c output from the terminals 21 and 22, respectively, become "1" level, and the other terminals 20,
Codes a, b to g outputted from 23 to 26, respectively, are at the "0" level. When the display device shown in FIG. 5 is driven using the codes a to g obtained here, "IJ
is displayed. Thereafter, as the IQ Hayabusa counter circuit 3 sequentially counts clock pulses 0,
The count output codes Q, to Q4 change sequentially.

Table 1 below shows the results of code conversion of the inverted codes Q, -Q4 of the count output codes Q, -Q4 output from the IQ Hayabusa counter circuit 3 into codes a to g for driving the display device. Table 1 and the logical formula for code conversion in Table 1 above are as follows:
It is expressed by Equation 11 to Equation {7).

a=Q.・Q2・Q30Q.・Q2・Q・Q4...
[1'b=Q.・Q2・Q3・Q4 10Q.・Q2・Q3
・Q.・・・． ...[21c=Q.・Q2・Q3・Q4
...'3'd=Q.・Q2・Q3・10Q.・Q2・Q・Q40Q.・Q2・Q3・Q4
...{4'c=Q.・Q3・Q+Q.・Q2・
Q40 Q.・Q2・Q3 10Q2・Q3・Q4
...[51f=Q.・Q2・Q30Q2・Q3・Q+Q.・Q2・Q・Q4
・・・・・・【6'g=Q.・Q2・Q
30 Q.・Q2・Q+Q.・Q2・Q・Q4
......{71 Next, the code converter and correction circuit shown in FIG. 7 convert the count output codes Q, ~Q4 output from the hexadecimal counter circuit 6 into
The case of code conversion into codes a to g for driving a display device will be explained.

When converting the count output codes Q, . The inverted conversion switching signal TD and the conversion switching signal TD supplied to the other clock input terminal of the NAND gate 10 are at the "1" level and "1" level, respectively.
0” level.

As a result, the p-Tr 12 becomes non-conductive, and the signal Q is influenced by the inverted codes Q, -Q4 fed to the NAND gate 10. That is, in the time chart shown in FIG. 4, the count output codes Q, ~Q are all "1".
” level (corresponding to count “12”), the output signal of the NAND gate 10, that is, the signal Q, is “0” level (corresponding to count “12”).
At this time, the output signal of the inverter 11, that is, the signal Q, becomes the "1" level. Then, when the count output codes Q, ~Q4 are all "1" and other than the bell, the output signal of the inverter 11 becomes the "1" level. Count output code Q
, -Q4, signal q and signal Q become "0" level and "1" level, respectively. So 1
The case where the count output codes Q, -Q4 of the binary counter circuit 6 are converted will be described. The operation of the hexadecimal counter circuit 6 in the range of the count state from "1" to "9" is the same as the operation of the IG Hayabusa counter circuit 3, so a description thereof will be omitted.

Further, since the operations are the same, the codes a to g output from the terminals 20 to 26, respectively, are also the same. Then, the decimal counter circuit 6 inputs the clock pulse number by 10.
Count output code (Q,
=Q2=Q3=“1” level, Q4=“0” level)
The signals input to terminals 7 and 32 and Q are at the "0" level and the "1" level, respectively. Further, the inverted codes Q and -Q4 inputted to the terminals 28 to 30 respectively are at "0" level, and the inverted code Q4 inputted to Satoko 31 is "0" level.
1" level. As a result, p-Trp5, p9~p,
．． is conductive and terminal 20 is V. . Connected to points. As a result, the code a output from the terminal 20 becomes "1" level. Furthermore, p-Trp, 2 to p, 5, p, 7, p, and 8 are rendered conductive, and the code b output from the terminal 21 becomes "1" level. Further, since p-Trp22 and p24 are conductive and the p-Trp is already suitable for conduction, terminal 22 is connected to the Voo point. As a result, an output from terminal 22 is obtained. The code c that is entered is at the "1" level. Furthermore, p-Tr
p25, p28 to p3o, and p33 to p35 are conductive, and the terminal 23 is at V. . Connected to points. As a result, the code d output from the terminal 23 becomes "1" level. Furthermore, p-Trp$, p38, P mother, P42~P44'P45
~P47 becomes conductive and the terminal 24 is connected to the Voo point.
As a result, the code e output from the terminal 24 becomes "1" level. Furthermore, p-Tr p monument, body 2, p54, Q
The terminal 25 is electrically connected to the V addition point. As a result, the code f output from the terminal 25 becomes "1" level. Furthermore, the n-Tr connected in series is 9, 2B
conducts, and the terminal 26 is connected to the Vss point. As a result, the code g output from the terminal 26 becomes the "0" level. That is, after the hexadecimal counter circuit 6 counts the clock pulse ◇ by 1, the terminals 20 to 25 of the code conversion section
From the terminal 26, codes a to f of "1" level are output, respectively, and from the terminal 26, a code g of "0" level is output. When the display device shown in FIG. 5 is driven using the codes a to g obtained here, "0" is displayed. Next, the hexadecimal counter circuit 6 counts the clock pulses ◇ once more. After this, the count output code is Q. =Q4="0"
level, Q2=Q3=“1” level. At this time, the signal Q and the signal input to the terminal 27 and the terminal 32 of the code converting section, respectively, remain at the "0" level and the "1" level, respectively. The inverted codes Q, Q4 inputted to the terminals 28 and 31 respectively become "1" level, and the inverted codes Q2 and Q inputted to the terminals 29 and 30 respectively become "0" level.
As a result, the series-connected n-Trns 5 to n7 become conductive, and the terminal 20 is connected to the Vss point. As a result, terminal 2
The code a output from 0 becomes the "0" level. Further, p-Tr p, 3 to p, 5, p, 6 to p, and 8 are made conductive, and the terminal 21 is connected to the Voo point. As a result, terminal 2
The code b output from 1 becomes the "1'1 level. Furthermore, p-Tr p2,, p22, p-Trp2o is conductive. Since p-Trp2o is already conductive, the terminal 22 is connected to the Voo point. As a result, the code c output from the terminal 22 becomes the "1" level.Furthermore, the series-connected n-hn 7 becomes conductive, and the terminal 23 is connected to the Vss point.As a result, The code d output from the terminal 23 becomes "0" level. Furthermore, the n-T connected in series
rn is conductive, and the terminal 24 is connected to the Vss point. As a result, the code e output from the terminal 24 is “0”.
” level.Furthermore, n-Trn49 connected in series
~n5, becomes conductive and the terminal 25 is connected to the Vss point.
As a result, the code f output from the terminal 25 is “0”
level. Furthermore, n-Tr stops 4 to n connected in series
66 is suitable. Also, since the n-Trn spots connected in series with the h-Trn64 to n lines are already conductive, the terminal 26 is connected to the Vss point. As a result, the code g output from the terminal 26 becomes the "0" level. That is, the hexadecimal counter circuit 6 converts clock pulse 0 to 11.
After counting the number of times, codes b and c become "1" level, and the other codes a, d to g become "0" level. When the display device shown in FIG. 5 is driven using the codes a to g obtained here, "1" is displayed. Next, the hexadecimal counter circuit 6 counts the clock pulses J once more. After this, the count output code is Q, =Q2=Q3=Q4='
At this time, as described above, the signal q and the signal Q change to the "1" level and the "0" level, respectively.The signal Q input to the terminal 27 of the code conversion section becomes "1".
When the level is reached, the n-Tr ratio o which was non-conducting until now
, peak 8 becomes conductive, and p-T, which was suitable for conduction until now, becomes conductive.
rp illusion, p45 becomes necessary conduction. Furthermore, when the signal Q input to the terminal 32 reaches the "0" level, the n-Tr n-axis, ratio 3, and n-axis, which had been suitable for conduction, become non-conductive, and the p-Tr, which had been non-conductive, becomes non-conductive. Spots are suitable.
Further, the inverted codes Q, -Q4 inputted to the terminals 28 - 31 are all at "0" level. As a result, p-Tr, p
8, p. conducts, and the terminal 20 is connected to the Voo point. As a result, the code a output from the terminal 20 is “1”
level. Furthermore, p-Tr p,2~p,4,p,
7 to p and 9 are electrically connected, and the terminal 21 is connected to the Voo point. As a result, the code b output from the terminal 21 is ''1
" level. Furthermore, since n-Trwo is already conductive, the terminal 22 is connected to the Vss point. As a result,
The code c output from the terminal 22 is at the "0" level. Furthermore, p-Trp25, p28-p3,, p33, p
34 becomes conductive, and the terminal 23 is connected to the VDo point. As a result, the code d output from the terminal 23 becomes "1" level. The p-Trs p38, p, p41, p44, p45, and p are conductive, and the terminal 24 is connected to the Voo point. As a result, the code e output from the terminal 24 becomes "1" level. Moreover, already n-Trn4
Since the terminal 8 is conductive, the terminal 25 is connected to the Vss point. As a result, the code f output from terminal 25 is “0”
level. Furthermore, since the p-Trp motherboard is already conductive, the terminal 26 is connected to the Voo point. As a result, the code g output from the terminal 26 becomes "1" level.
In other words, the hexadecimal counter circuit 6 counts the clock pulse as 1.
After counting four times, terminals 20, 21,
From 23, 24, and 26, the “1” level code a,
b, d, e, g, and “0” from terminals 22 and 25, respectively.
"Level codes c and f are output. When the display device shown in FIG. 5 is driven to display using the codes a to g obtained here, "2" is displayed. Table 2 below shows the count output codes Q, ~ output from the hexadecimal counter circuit 6.
This shows the result of code conversion of the inverted codes Q, -Q4 of Q4 into display bag counterfeit driving codes a - g. The logical formula for code conversion in Table 2 and Table 2 above is as follows:
8-Formula to (expressed by 14th expression)

a=Q.・Q2・Q30Q.・Q.・Q・Q4...
'8'b=Q.・Q2・Q3Q40Q.・Q2・Q3・
Q...[91c=Q.・Q2・Q3・Q4 10Q
......(100d=Q.・Q2・Q30Q.・
Q2・Q・Q410Q.・Q2・Q3・Q4
...(11) e=Q.・Q3・Q4 10Q.・Q2・Q10Q.・Q2・Q3 10Q2・Q3・Q4
...(12) f=Q.・Q2・Q30Q2・Q3・Q
+Q.・Q2・Q3・Q410Q...(13)g
=(Q.・Q2・Q30Q.・Q2・Q+Q.・Q2・
Q3・Q4) Q... (IQ In this way, in addition to the code conversion section, a detection section and a correction circuit section with a simple configuration are provided, and the signals Q and Q output from this detection section are input to the correction circuit section. Accordingly, 1 Bo Hayabusa counter circuit 3 and 12
It becomes possible to convert the count output codes Q, .about.Q output from the advance counter circuit 6, respectively, into codes a.about.g for driving the display device.

As explained above, according to the present invention, in the detection section, 1
When a count output code corresponding to the maximum count of the binary counter is detected, a count output code corresponding to the count other than the maximum count of the hexadecimal counter and a count corresponding to all counts of the 1G ship Kawanta are detected. The code conversion section that converts the output code into a code for driving a display device is corrected by the correction circuit section so that a code for driving the display device is obtained in accordance with the count output code corresponding to the maximum count number of the above-mentioned hexadecimal counter. By doing so, it is possible to provide a common code conversion circuit for driving a 7-segment display device that can convert count output codes of several counter circuits having different count numbers into codes for driving a display device. can.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the 1-bo Hayabusa counter circuit, Fig. 2 is a time chart for explaining the operation of this counter circuit, Fig. 3 is a block diagram of the hexadecimal counter circuit, and Fig. 4 is a block diagram of this counter circuit. Time chart for explaining operation, 5th
6 is a diagram showing the configuration of a display device, FIG. 6 is a circuit diagram showing the configuration of a detection section for explaining the above embodiment, and FIG. 7 is a circuit diagram showing an embodiment of the present invention. 10...NAND gate, 11...Inverter, 12...p
Channel MOS type transistors, 20-32...terminals, n, to n7. ...n channel MOS type transistor, p, ~p mother...p channel MOS type transistor. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Bell chicks

Claims (1)

[Claims] 1 A P-channel MOS transistor and an N-channel MOS transistor are inserted in series or parallel between a pair of power supply voltage supply points to form a signal path, and the count output code of a decimal counter and a decimal counter is connected to the gates of these transistors. A code conversion unit that converts the supplied count output codes corresponding to counts other than the maximum count of the hexadecimal counter and count output codes for all counts of the decimal counter into codes for driving the 7-segment display device. and a detection unit that detects a count output code corresponding to the maximum count number of the hexadecimal counter, and a transistor connected in series or parallel to a predetermined transistor in the code conversion unit,
When the detection section detects a count output code corresponding to the maximum count number of the hexadecimal counter, these transistors are selectively turned off or on to control a specific signal path in the code conversion section. By forcibly switching, the code converter converts the count output code corresponding to the maximum count number of the hexadecimal counter to 7.
1. A code conversion circuit for driving a 7-segment display device, comprising a correction circuit unit for converting the code into a code for driving a 7-segment display device.