JPS60262073A - Disturbance monitor for digital signal processor - Google Patents

Abstract

PURPOSE:To enable a constant monitoring by extracting and storing input/output data into first and second memories to obtain the results of disturbance monitoring at the output of a means for comparing the results with a simulation processor and the output data. CONSTITUTION:A necessary data from an input signal line IL is extracted with a simulation processor 8 to be stored into a first memory 6 and a data processed with a digital signal processor 1 based on the data is extracted from an output signal line OL to be stored into a second memory 7. Then, the data of the first memory 6 is simulated with the processor 8 and the stored data controlled in the output action of the second memory 7 is compared with the results of simulation by a comparator 3. When both of the data coincide with each other, the unit 1 is reset while when they do not, an alarm is lighted judging that some disturbance occurs while a terminal 5 is notified thereof. This enables constant monitoring without interruption of the unit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault monitoring device for a digital signal processing device.

As a digital signal processing device that receives a series of digital signals and converts the code through arithmetic processing, for example, a cyclic or acyclic filter, or an adaptive differential PC that converts input digital signals on a digital telephone line.
An ADPCM conversion filter that performs M (ADPCM) conversion and an FDM conversion filter that performs frequency division multiplexing (FDM) conversion are known. The present invention relates to a device for monitoring failures in these digital signal processing devices.

[Prior art and its problems]

Conventionally, in order to monitor digital processing by a digital signal processing device, for example, as shown in FIG. A test pattern generator 2 is prepared, and when performing regular maintenance, the switch is switched from the input signal line IL to the test pattern generator 2, and the test pattern data is sent from the test pattern generator 2 to the current device 1. At the same time as the current device 1 performs digital processing, the test pattern generator 2 also generates a pattern to be generated by the digital signal processing device according to the test pattern, and the respective processing results are sent to the comparison circuit 3.
The comparison was made by As a result of the comparison, if the respective processing results are different, the warning lamp (LED) 4 is turned on or the terminal device 5 is notified of the fact fc, t).

In this conventional system, the input signal line IL and the currently used digital signal processing circuit 1 are disconnected by the switch SW during maintenance, so that the input digital signal applied to the input terminal IN during that time is not processed. For example, in a telephone line, this means that the telephone service function is temporarily stopped, which is undesirable.

Furthermore, as shown in FIG. 5, a conventional system has been used in which digital signal processing devices 1 and 2 having the same configuration are connected to input terminals IN, and their outputs are constantly compared by a comparator circuit 3. In the methods shown in Figures 4 and 5, both
Digital signal processing equipment is required.
The problem is that the fault monitoring equipment becomes expensive because the system (signal processing equipment) is generally expensive. .

[Purpose of the invention]

In view of the above-mentioned problems in the conventional system, the present invention is based on the concept of simulating the calculation contents of digital, digital, and digital signal processing devices on a general-purpose processor. 0 [Structure of the Invention] An object of the present invention is to provide an inexpensive fault monitoring device that can constantly monitor faults and damage without interrupting processing.

To achieve the above object, what is provided by the present invention is a digital signal, signal processing, v! A first memory that extracts and stores input data input to a digital signal processing device, which is a device fault monitoring device, and output data obtained by digitally processing the digital signal processing device based on the input data. , a second memory for extracting and storing the Hi-Q memo, and a simulation processor for simulating digital processing by the digital signal processing device at a speed lower than the processing speed of the digital processing based on the input data stored in the second memory; The present invention is characterized by comprising a comparison means for comparing the simulation result obtained by the method with the output deguter stored in the second memory, and the failure monitoring result of the digital signal processing device is obtained as an output of the comparison means. This is a fault monitoring device.

[work, use]

The simulation processor can simulate arbitrary processing of input data by the digital signal processing device by controlling the memory, and furthermore, processing of input data by the digital signal processing device is interrupted even during simulation. Never. Even if the simulation operation by the simulation processor is slower than the processing speed of the digital signal processing device, this does not pose a particular problem in diagnosing a fault.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a failure monitoring result position of a digital signal processing device according to an embodiment of the present invention. In the figure, l is a digital, left signal processing device, 3 is a comparison circuit,
4 is a lamp, 5 is a terminal device, 6 is a first memory, 7 is a second memo, and 8 is a simulation processor.

The simulation processor 8 is a general-purpose micro combinator with a built-in program for simulating the arithmetic processing performed by the digital signal processing device 1.

The simulation processor 8 controls the input operation of the first memory 6, extracts data necessary for the operation to be simulated from the input signal line IL, and inputs the data to the first memory 6.
Store in. The simulation processor 8 also controls the input operations of the second memory 6 and the memory 6.
The data processed by the digital signal processing device 1 based on the same data stored in the output signal line OL is extracted from the output signal line OL and stored in the second memory 7. K
The data stored in the memory 6 of the digital signal processing device 1 is retrieved at an appropriate time by the shimmy range processor 8, and the operation of the digital signal processing device 1 is simulated. When the simulation 1/- is completed, the simulation processor 8 controls the output operation of the second memory 7 and provides the stored data to the comparator circuit 3, and also provides the simulator result to the comparator 3. The comparator compares the two data, and if they match, it resets the simulation processor 8 to perform the same simulation operation as above again, and if they do not match, it is determined that a failure has occurred and the alarm lamp 4 is turned off. It lights up or notifies the terminal device 5. ,
.

By the above-mentioned operation, the digital signal processing device #1 can constantly simulate the digital processing without interrupting the processing production by the digital signal processing device #1.
failures can be monitored.

Pound - Shiminire -. The John processor 8 is extremely inexpensive compared to the digital signal processing device 1, and the cost of the fault monitoring device is reduced.

1 Furthermore, it has the advantage of being able to simulate partial digital processing within the signal processing device 1. Conventionally, rounding to monitor faults in partial digital processing involves the use of this partial processing. It is necessary to prepare a separate digital signal processing device for each process, which is extremely expensive, but according to the present invention, a single and inexpensive simulation processor can handle general-purpose processing. can.

FIG. 2 is a block circuit diagram showing an acyclic filter as an example of a digital signal processing device.

In the figure, a new sample value is input in parallel to the input terminal IN as a digital signal of, for example, 16° Bi/So every specific sampling period.

"0n-1*"'n-21"..."I"O
nm is each bit of input data of 16 pits.
11°, which is a shift register that shifts bit by bit.
11. .

112...+11m respectively apply coefficients aOs aim a2s... to 16-bit input data.
·, 3 is a multiplier that multiplies am, and 12 is a multiplier 11°, ], 1,.

This is an adder that adds the multiplication results of 112, . . . , 11rn. The value y'n obtained at the output terminal OUT by the acyclic filter shown in Fig. 2 is)'n = aox* + alXfi-s + ""
ljmxn-m, ,;・(1).

FIG. .beta. is a flowchart showing the flow of processing within the simulation processor 8 for simulating the above calculation by the acyclic filter shown in FIG. 2 by the simulator W/processor 8. In FIG. 3, in steps 81 to 8m, 16-bit data IN,
Convert xl xn-s*10°,, X1l-, +1 to XHg
...+”mxn is calculated. Step 8111
4-'', this calculation result is compared with 8 of the above equation (1).

If they match, move on to the next fault detection operation. If there is a mismatch, a warning lamp is turned on and the terminal device is notified of this fact.

In this way, failure monitoring of the acyclic filter is performed by the smudge processor 8.

Of course, the present invention is not limited to failure monitoring of acyclic filters. For example, fault monitoring of various digital signal processing devices such as cyclic filters, ADPCM conversion filters and FDM conversion filters on digital telephone lines.
It is possible to carry out the simulation by the simulation processor 8.

[Effect of clear nose]

As explained above, according to the present invention, it is possible to interrupt the processing by the currently used digital signal processing device by simulating the operation of the digital signal processing device in a general-purpose program. Cost sheet failure monitoring 1ii can be used to constantly monitor failures without any problems. Further, since partial arbitrary digital processing within the digital signal processing device can be shimmy-reduced by a single general-purpose processor, an inexpensive and versatile fault monitoring device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a fault monitoring device for a digital signal processing device according to an embodiment of the present invention, and FIG. 2 is an example of a digital signal processing device. A block diagram showing an acyclic filter. Fig. 3 is a flowchart showing the flow of processing for simulating the calculations by the circuit shown in Fig. 2 by a simulation processor, and Fig. 4 is a four-step diagram for explaining an example of a conventional fault monitoring method. figure,
FIG. 5 is a diagram for explaining another example of the conventional fault monitoring system. 1...Digital signal processing device, 3...
・Comparison circuit, 6...First memory, 7...
...Second memory, 8...Simulator 1 processor. Patent Applicant Fujitsu Limited Patent Application Agent Akira Aoki Patent Attorney Kazuyuki Nishidate (1) Yukio Patent Attorney Akira Yamaguchi Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A failure monitoring device for a digital signal processing device, comprising: a first memory for extracting and storing input data input to the digital signal processing device; a second memory for extracting and storing output data obtained by digital processing; a second memory for extracting and storing output data obtained by digitally processing the digital signal processing device; The second memory includes a simulation processor that performs simulation at a low speed, and comparison means that compares the simulation results of the simulation processor with the output data stored in the second memory, and a digital signal is supplied to the output of the nuclear comparison means. 9. A fault monitoring device characterized in that it obtains fault monitoring results of a management device. 2. Fault monitoring according to claim 1, wherein the simulation processor controls input/output operations of the first and second memories. 3.' The fault monitoring device according to claim 1 or claim 11E2, wherein the digital signal geography device is an acyclic filter. 4. # When the digital signal processing device converts the digital signal on the telephone line into an adaptive differential PCM converter using an ADPCM conversion filter, the result of fault monitoring as described in claim 1 or 2. 5.' The fault monitoring device according to claim 1 or 2, wherein the digital signal processing device is an FDM conversion filter that performs frequency division multiplex conversion on a digital signal on a telephone line.