JPS60259022A - Synchronizing oscillating circuit and phase analyzer using it - Google Patents

Abstract

PURPOSE:To attain synchronizing oscillation at an optional phase to an input signal and to decrease the error by delaying an output of an intermediate stage of a frequency divider as a clock so as to retard an output of the frequency divider by means of a shift register. CONSTITUTION:The shift register 12 using a signal of a prescribed stage of a frequency divider 8A of a PLL circuit section 8 as a clock input is used so as to obtain a synchronizing oscillating circuit retarding the input pulse phase to a D flip-flop 10 by a prescribed value. The input pulse phase to the D flip-flop 10 is delayed by, e.g., pi/6 so as to generate a gate pulse having one period of a signal S1 from a point of a phase delayed by pi/6, the sampling pulse is inputted to sample and hold circuits 3, 4 during the gate pulse period so as to obtain a phase analyzer reducing the error generated in the vicinity of the phase difference pi/2 and 3pi/2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a synchronous oscillation circuit and a phase analyzer using the same.

Configuration of the conventional example and its problems The conventional waveform analyzer, as shown in FIG.
, s2, the amplitude and phase of the fundamental wave component and the harmonic component, and the phase difference between both signals sl and s2. After that, the outputs of the sample and hold circuits 3 and 4 are each digitized by an A/D converter 5.6 and input to the CPLI 7, where the data is processed within the CPUV. By doing so, the above is obtained.

Regarding the timing of digitization in the above, in the case of extracting only general frequency components, sampling may be performed using a fixed internally generated clock, but if the frequency of the input signals S, S2 fluctuates, In addition, in harmonic analysis of a power supply waveform in which it is desired to extract harmonic components of the fluctuating frequency, this sample timing is set to signal 3+ by the PLL circuit section 8.

Synchronization is established with either S2. Specifically, for example, a zero cross signal of the signal S1 is detected by the zero cross detection circuit 9, and this is applied to the PLL circuit section 8 to periodically generate a sampling pulse synchronized with the signal S1, and the PLL circuit section A pulse having the same frequency as the signal S1 is extracted from the signal S1, and based on this pulse, a gate pulse for one period of the signal S1 from the zero cross rising point of the signal S1 is generated by the D flip-flop 10. By controlling the signal S1, a sampling pulse for one period of the signal S1 is applied to the sample and hold circuit 3.4 from the zero cross rising point of the signal S1, and the signals Si and s2 are sampled, and the signals S, , s2 are
The sampling values at each timing are sequentially A/D converted.

The PLL circuit unit 8 compares the zero-cross signal from the zero-cross detection circuit 9 and the output signal of the frequency divider 8A through a phase frequency detection circuit (phase comparison!') 8B, passes this comparison output through a low-pass filter 8C, The oscillation frequency of the voltage-controlled oscillator 8D is controlled by the output of the low-pass filter 8C, and the oscillation signal of the voltage-controlled oscillator 8D is input to the frequency divider 88. In this case, the sampling pulse with a period T/H obtained by dividing the period 1'' of the signal S1 into N equal parts is sent to the frequency divider 8.
The output signal from the final stage of the frequency divider 8A is input to the phase frequency detection circuit 8B and the D flip-flop 9.

FIG. 4 shows a timing diagram of each part in FIG. 3, and shows the signal S1
If the waveform is as shown in FIG. 4(A), a sampling pulse as shown in FIG. 4(B) is input from the PLL circuit section 8 to the ant gate 11, and a pulse signal as shown in FIG. 4(C) is inputted to the ant gate 11. (same period as signal S1) is the phase frequency detection circuit 8B
and is input to the D flip-flop 10. As a result, the D flip-flop 10 generates a gate pulse for one period of the signal S1 from the zero cross rising point of the signal S1 as shown in FIG. In circuits 3 and 4, from the zero cross rising point of the signal S1 to the period of one cycle of the signal S1 (see FIG. 4),
A sampling pulse is input as shown in E').

In the waveform analyzer as described above, in order to calculate the phase difference between the two signals s, , s2 (the phase difference between the synchronization signal and the signal S2) without being affected by distorted waves, it is necessary to The PLL circuit unit 8 generates a sampling pulse that divides the interval up to the next zero-cross rising point into N equal parts, samples the signal S2 with this sampling pulse, performs A/D conversion, and converts the resulting N pieces of A/D conversion data. It is sufficient to perform a discrete Fourier transform on .

The method of determining the phase by discrete Fourier transform is N A/D
The coefficient 21 of the cosine function and the coefficient b1 of the sine function of the fundamental wave are determined by calculating equations (1) and (2) on the converted data, and the phase θ1 is determined by equation (3).

θ-tan-' (at/b+) ・・・・・・・-(
3) However, when determining the coefficient 21°bl by discrete Fourier transform and calculating the phase of the fundamental wave from the synchronization signal from this (here, since the synchronization signal is taken from the signal S1, the signals S, , S2 ), bl
is close to 0 i', when bl is positive, θ-tan-' (at /l)+ ) -n/2, and when bl is negative, θ-jan-' (a+/b+) # 3 π /
2, and when b becomes even slightly positive or negative around -0, the phase difference of π is detected. When bl is around 0, the measurement system error causes bl to be measured even though it is actually positive. If the value is negative or vice versa, the phase will have approximately π
There was a problem that this resulted in errors. This error is jan
It is at the singularity of .

To eliminate problems caused by such singularities, the signal S2
The problem caused by the singularity can be solved by shifting the sampling start timing of the signal S1 from the rising zero cross point of the signal S1. However, in the PLL circuit section 8, the phase of the oscillation output becomes the same as the signal S, and the phase of the oscillation output becomes the same as the signal S.
1 could not be changed arbitrarily. Also,
If the signal S1 is simply delayed by a delay circuit, when the frequency of the signal S1 fluctuates, the phase fluctuates accordingly, making it impossible to set an accurate phase.

Purpose of the Invention The present invention provides a synchronous oscillation circuit that can perform synchronous oscillation at an arbitrary phase with respect to an input signal, and that can prevent phase fluctuations due to frequency fluctuations of the input signal, and a synchronous oscillation circuit that has a phase difference of π/2 and It is an object of the present invention to provide a phase analyzer that can reduce errors that occur near 3π/2.

Structure of the Invention The synchronous oscillation circuit of the present invention includes a voltage controlled oscillator that oscillates at a frequency according to a control input voltage, a frequency divider that divides the output of the voltage controlled oscillator, and an input signal and the output of the frequency divider. a low-pass filter that applies the low frequency component of the output of the phase comparator to the voltage controlled oscillator as a control voltage; and a shift register that delays the signal as a clock, and the phase analyzer is a phase analyzer that measures the phase difference between the first and second signals, and the phase analyzer measures the phase difference between the first and second signals, a voltage controlled oscillator that oscillates at a frequency, a frequency divider that divides the output of the voltage controlled oscillator, and a phase comparator that compares the phases of the first signal and the output of the final stage of the frequency divider; A low-pass filter that applies the low frequency component of the output of the phase comparator as a control voltage to the voltage controlled oscillator, and a shift register that delays the output of the final stage of the frequency divider using the output of the intermediate stage of the frequency divider as a clock. and a gate pulse generating means for generating a gate pulse for one period of the first signal in response to the output of the shift register, and a gate pulse generating means for generating a gate pulse for one period of the first signal, and a gate pulse generating means for generating the gate pulse for one period of the first signal, and a gate pulse generating means for generating the gate pulse for one period of the first signal. a gate for passing the output of the intermediate stage of the circuit, a sample hold circuit for sampling the second signal using the output of this gate as a sampling clock, and an A/D converter for A/D converting the output of the sample hold circuit. A converter, and phase difference calculation means for calculating the phase difference between the first and second signals from the data string from the A/D converter and the delay amount of the shift register. It is something to do.

DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 and 2. As shown in FIG. 1, this waveform analyzer includes a shift register 12 that receives a signal from a predetermined stage of a frequency divider 8A as a clock input, and inserts the shift register 12 on the input side of a D flip-flop 10. The phase of the pulse is
For example, the signal S is delayed by about π/6 from a phase point delayed by π/6 from the zero cross rising point of the signal S1.

A gate pulse for one period is generated, and the sampling pulse is sent to sample and hold circuits 3 and 4 during this gate pulse period.
.

To shift the phase by π/6, the pulse of the synchronizing signal before frequency division by 12 may be extracted from the frequency divider 8A and used as the clock input to the shift register 12.

Then, the CPU 7 performs a discrete Fourier transform on the A/D converted data, and performs a phase correction of π/6 on the phase estimated by the calculations of equations (1) to (3). Accurate phase difference can be determined.

This is near the phase of π/2 or 3π/2,
Even if bl takes a value near 0 as it is, by shifting the phase of the sampling pulse, the phase can be changed to π/2.
Alternatively, the value of bl becomes a relatively large positive or negative value away from the vicinity of 3π/2, and polarity fluctuation does not occur even if there is a measurement error.

Furthermore, since the delay amount of the shift register 12 is determined by the output to the frequency divider 8, when the frequency of the signal S1 changes, the delay time changes accordingly, making it possible to keep the phase constant. , the phase can be set accurately.

FIG. 2 shows a timing diagram of each part in the circuit of FIG. 1, FIG. 2(A) shows the waveform of signal S1, and FIG.
B) shows the sampling pulse from the PLI circuit section 8, FIG. 2(1C) shows the input signal from the frequency divider 8A to the phase frequency detection circuit 8B and the shift register 12, and FIG. ) shows the waveform of the input signal from the shift register 12 to the D flip-flop 10, and FIG.
shows the output waveform of the D flip-flop 10, and FIG.
F) shows the input waveform to the sample and hold circuits 3 and 4. As is clear from this figure, the gate pulse from the D flip-flop 10 is delayed by an arbitrary phase X due to the action of the shift register 12.

Note that whether or not to shift the phase is determined by collecting data without shifting the phase, performing Fourier transformation, and determining whether the value of coefficient Sl is larger or smaller than a predetermined value. If it is large, the calculation result of the phase difference without phase shift is used as the phase difference between the two signals, and if the value of coefficient S is smaller than the predetermined value, the phase of the sampling pulse is shifted and data collection is performed again. Based on this data, Fourier transform is performed to calculate the phase difference, and the result is corrected and used as the phase difference between the two signals.

Note that the sampling pulse can be shifted from the synchronization signal by the following method. That is, N data strings f (
0), f (1), f (2).

..., f (N-1) and the data string g(0
).

g (1), g (2), . . . g (N-1) are used to separate the signal from the synchronization signal. Assuming that the data is shifted by π/6, the data strings to be calculated are f (N/12), f ((N/12) +1),
....

f ((N/12) + (1111-12) /12
).

g(0), ..., g ((N/12)-1). Perform the same operations for each, and calculate the phase.

By subtracting the difference between these results, the exact phase can be determined.

Effects of the Invention The synchronous oscillation circuit of the first aspect of the invention is capable of synchronizing oscillation with an arbitrary phase with respect to an input signal, and can prevent phase fluctuations due to frequency fluctuations of the input signal. Further, the phase analysis device of the second invention can reduce errors that occur when the phase difference is near π/2 and 3π/2.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing diagram of each part thereof, FIG. 3 is a block diagram of a conventional waveform analyzer, and FIG. 4 is a timing diagram of each part thereof. 1.2... Signal conditioner, 3.4... Sample hold circuit, 5, 6... A/D converter, 7.
... CPU, 8 ... PLL circuit section, 8A ... frequency divider, 8B ... phase frequency detection circuit, 8C ... low pass filter, 8D ... voltage controlled oscillator, 9 ... zero cross detection Circuit, 10...D flip-flop, 11.
...and gate, 12...shift register

Claims (2)

[Claims] (1) A voltage controlled oscillator that oscillates at a frequency according to the control input voltage, a frequency divider that divides the output of the voltage controlled oscillator, and a phase comparator that compares the phase of the input signal and the output of the frequency divider. a low-pass filter that applies a low-frequency component of the output of the phase comparator as a control voltage to the voltage-controlled oscillator; and a shift register that delays the output of the frequency divider using the output of an intermediate stage of the frequency divider as a clock. Synchronous oscillation circuit with (2) A phase analysis device that measures the phase difference between the first and second signals, which includes a voltage-controlled oscillator that oscillates at a frequency that corresponds to the control input voltage, and a frequency divider that divides the output of the voltage-controlled oscillator. a phase comparator that compares the phases of the first signal and the output of the final stage of the frequency divider, and a low-pass filter that applies a low frequency component of the output of the phase comparator to the voltage controlled oscillator as a control voltage. a shift register that delays the output of the final stage of the frequency divider using the output of the intermediate stage of the frequency divider as a clock; and a gate for one period of the first signal in response to the output of the shift register. gate pulse generating means for generating a pulse; a gate for passing the output of the intermediate stage of the frequency divider during a period when the gate pulse is generated from the gate pulse generating means; 2, an A/D converter that A/D converts the output of this sample and hold circuit, and this A/D converter that samples the output of this sample hold circuit.
A phase analysis device comprising: a phase difference calculating means for calculating a phase difference between the first and second signals from a data string from a converter and a delay amount of the shift register.