JPS60258963A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60258963A JPS60258963A JP11398284A JP11398284A JPS60258963A JP S60258963 A JPS60258963 A JP S60258963A JP 11398284 A JP11398284 A JP 11398284A JP 11398284 A JP11398284 A JP 11398284A JP S60258963 A JPS60258963 A JP S60258963A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- region
- voltage
- semiconductor device
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 58
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 230000003321 amplification Effects 0.000 claims abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 11
- 239000002131 composite material Substances 0.000 abstract description 7
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 238000001514 detection method Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 101100299614 Homo sapiens PTPN13 gene Proteins 0.000 description 1
- 101100352663 Mus musculus Pnp gene Proteins 0.000 description 1
- 101150069896 PNP1 gene Proteins 0.000 description 1
- 102100033014 Tyrosine-protein phosphatase non-receptor type 13 Human genes 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、半導体装置に関し、特にスイッチング電源
やモータ制御回路等の出力段に使用するトランジスタに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a transistor used in an output stage of a switching power supply, a motor control circuit, or the like.
［発明の技術的背景１
パワートランジスタ等の電力用半導体素子は、過電圧及
び過電流などの通電によって素子破壊が起こらぬように
過電圧及び過電流の検知回路及び保護回路を接続して用
いられる。 たとえばパワートランジスタの場合、出力
電圧及び出力電流の検知回路を設けておき、過電圧もし
くは過Ｎ流がパワートランジスタに印加または通電され
た時に該検知回路が作動してトランジスタのベースコン
トロール部を制御し該パワートランジスタがオフされる
ように回路設計を行なっていた。 このような検知回路
及び保護回路は一般に外付は回路であり、素子自身の中
に過負荷検知機能や保護機能を備えているトランジスタ
はなかった。[Technical Background of the Invention 1] Power semiconductor devices such as power transistors are used by connecting overvoltage and overcurrent detection circuits and protection circuits to prevent device destruction due to overvoltage and overcurrent. For example, in the case of a power transistor, a detection circuit for output voltage and output current is provided, and when an overvoltage or an excessive N current is applied or energized to the power transistor, the detection circuit is activated and controls the base control section of the transistor. The circuit was designed so that the power transistor was turned off. Such detection circuits and protection circuits are generally external circuits, and there is no transistor within the device itself that has an overload detection function or protection function.
［背景技術の問題点コ
従来のパワートランジスタでは検知回路や保護回路が半
導体素子とは別体の外付は回路であったため、構成部品
数が多く、従ってコストが高いうえ、電子回路が大型に
なる等の問題点があった。[Problems with the background technology] In conventional power transistors, the detection circuit and protection circuit were external circuits that were separate from the semiconductor element, so the number of components was large, resulting in high cost and a large electronic circuit. There were some problems.
［発明の目的］
この発明の目的は、前記問題点を解決し、素子自身の中
に保護機能を備えた電力用半導体装置を提供することで
ある。 更に詳細には、この発明の目的は、自己保護機
能を備えた複合型トランジスタを提供することである。[Object of the Invention] An object of the present invention is to solve the above problems and provide a power semiconductor device having a protection function within the element itself. More specifically, it is an object of the invention to provide a composite transistor with self-protection functionality.
［発明の概要］
この発明による半導体装置は、負荷電流が流入する第一
の電極と、ｎ荷電流が流出する第二の電１．． 極と、
該第−及び第二の電極間の電流を開閉する機能を有した
第三の電極とを有して成り、該第−乃至第三の電極が共
通の半導体基板内に形成されている各領域に接続されて
おり、該半導体装置は該第−及び第二の電極の電圧が所
定値を越えた時には該第−及び第二の電極間の電流をし
ゃ断する機能を有している。 そして、本発明の半導体
装置においては２個のバイポーラトランジスタを絹み合
わせたモノリシック複合型トランジスタとして構成され
ている。 この複合型トランジスタは、例えばＰＮＰ型
トランジスタとＮＰＮ型トランジスタとの組合せから成
り、ＰＮＰ型のコレクタがＮＰＮ型のベースに接続され
るとともにＰＮＰ型のベースがＮＰＮ型のコレクタに接
続されて、ＮＰＮ型が出力段をまたＰＮＰ型が入力段を
それぞれ構成している。 従って、ＮＰＮ型のコレクタ
、エミッタ間における電圧の大きざに応じてＰＮＰ型の
出力電流が開閉されると同時にＰＮＰ型の出力電流の開
閉に応じてＮＰＮ型の出力電流が開閉されることになり
、その結果、該複合型トランジスタは自己保Ｉｎ能を発
生する。[Summary of the Invention] A semiconductor device according to the present invention includes a first electrode into which a load current flows, and a second electrode into which an n-charge current flows out. ．． pole and
and a third electrode having a function of opening and closing a current between the first and second electrodes, each region in which the third to third electrodes are formed in a common semiconductor substrate. The semiconductor device has a function of cutting off the current between the first and second electrodes when the voltages of the first and second electrodes exceed a predetermined value. The semiconductor device of the present invention is constructed as a monolithic composite transistor in which two bipolar transistors are connected together. This composite transistor is composed of, for example, a combination of a PNP type transistor and an NPN type transistor. constitutes the output stage, and the PNP type constitutes the input stage. Therefore, the output current of the PNP type opens and closes depending on the voltage difference between the collector and emitter of the NPN type, and at the same time, the output current of the NPN type opens and closes according to the opening and closing of the output current of the PNP type. , As a result, the composite transistor generates a self-maintenance In ability.
［発明の実施例］
第１図は本発明による半導体装置の概念を等何回路とし
て表わしたものである。[Embodiments of the Invention] FIG. 1 shows the concept of a semiconductor device according to the present invention as a circuit.
第１図に示すように、本発明の半導体装置１はたとえば
Ｐ Ｎ Ｐ型のトランジスタ２とＮＰＮ型のトランジス
タ３とを組合わせて構成されるモノリシック複合型トラ
ンジスタとして実現することができるものである。 こ
の半導体装置１においてはトランジスタ２０ベースと］
レクタとがそれぞれトランジスタ３のコレクタとベース
とに接続されており、また、トランジスタ３のコレクタ
及びエミッタが該半導体装置１の外部の第一電極Ｃ及び
第二電極Ｅにそれぞれ接続されるとともにトランジスタ
２のエミッタが該半導体装置１の外部の第三電極Ｂに接
続されている。 ここに、第一電極Ｃは従来のバイポー
ラトランジスタにおけるコレクタ電極に該当し負荷電流
の流入を司り、第二電極Ｅは従来のトランジスタにおけ
るエミッタ電極に該当し、また第三電極Ｂはベース電極
に該当する。As shown in FIG. 1, the semiconductor device 1 of the present invention can be realized as a monolithic composite transistor configured by combining a PNP type transistor 2 and an NPN type transistor 3, for example. . In this semiconductor device 1, the transistor 20 base]
The collector and emitter of the transistor 3 are respectively connected to the first electrode C and the second electrode E outside the semiconductor device 1, and the transistor 2 is connected to the collector and the base of the transistor 3, respectively. The emitter of is connected to a third electrode B outside the semiconductor device 1. Here, the first electrode C corresponds to the collector electrode in a conventional bipolar transistor and controls the inflow of load current, the second electrode E corresponds to the emitter electrode in the conventional transistor, and the third electrode B corresponds to the base electrode. do.
前記構成の半導体装置１では、第−電極Ｃと第２電極Ｅ
にかかる電圧がある値より高くなるとト５−
ランジスタ２が非導通となって、そのコレクタ電流がし
ゃ断されるのでトランジスタ３のベース電流もカットさ
れてトランジスタ３も非導通になる。In the semiconductor device 1 having the above configuration, the -th electrode C and the second electrode E
When the voltage applied to transistor 5 becomes higher than a certain value, transistor 2 becomes non-conductive and its collector current is cut off, so that the base current of transistor 3 is also cut and transistor 3 also becomes non-conductive.
従って、本発明の半導体装置１が自己しゃ断機能すなわ
ち自己保護機能を有していることは明らかである。Therefore, it is clear that the semiconductor device 1 of the present invention has a self-shutoff function, that is, a self-protection function.
第２図は第１図のごとき概念の本発明の半導体装置１の
具体的な実施例を示したものである。FIG. 2 shows a specific embodiment of the semiconductor device 1 of the present invention based on the concept shown in FIG.
第２図において、４はＮ型の半導体基板であり、該半導
体基板４の上下両面には互いに対向しない位置にＰ型の
第一領域５と第二領域６とが形成されている。 第二領
域６内にはＮ型の第三領域７が形成され、第二領域６に
対向する半導体基板下面部には第一電極Ｃが設けられる
とともに第三領域７には第二電極Ｅが設けられ、また第
一領域５には第三電極Ｂが設けられている。 従って、
第一電極Ｃが設けられている半導体基板の部分と第二及
び第三領域とによってＮＰＮトランジスタ３が形成され
、また第一領域５と半導体基板４及び第二領域６とによ
ってＰＮＰトランジスタ２が形６−
成されており、ＰＮＰｔ−ランジスタ２のベースとＮＰ
Ｎトランジスタ３のコレクタとが共通の半導体基板によ
って構成され、さらにＰＮＰトランジスタのコレクタと
ＮＰＮトランジスタ３のベースとが共通の第二領域６に
よって構成されることになる。 それゆえ、第２図の半
導体装置は第１図の半導体装置と同じく自己保護機能を
有しており、以下のＪ：うに動作する。In FIG. 2, reference numeral 4 denotes an N-type semiconductor substrate, and a P-type first region 5 and a second region 6 are formed on both upper and lower surfaces of the semiconductor substrate 4 at positions that do not face each other. An N-type third region 7 is formed in the second region 6, a first electrode C is provided on the lower surface of the semiconductor substrate facing the second region 6, and a second electrode E is provided in the third region 7. A third electrode B is also provided in the first region 5. Therefore,
An NPN transistor 3 is formed by the portion of the semiconductor substrate where the first electrode C is provided and the second and third regions, and a PNP transistor 2 is formed by the first region 5, the semiconductor substrate 4, and the second region 6. 6- The base of PNPt-transistor 2 and the NP
The collectors of the N transistors 3 are formed by a common semiconductor substrate, and the collectors of the PNP transistors and the bases of the NPN transistors 3 are formed by a common second region 6. Therefore, the semiconductor device shown in FIG. 2 has a self-protection function like the semiconductor device shown in FIG. 1, and operates as shown below.
第一電極Ｃど第二電極Ｆとの間の電圧が低い時には第一
電極Ｃと第三電極Ｂとの間の電圧は第一領域５からホー
ルの注入が行なわれるような順方向電圧となる。 従っ
て第一領域５から半導体基板４に注入されたホールは半
導体基板４のＮ領域を横切って第二領域６に拡散する。When the voltage between the first electrode C and the second electrode F is low, the voltage between the first electrode C and the third electrode B becomes a forward voltage such that holes are injected from the first region 5. . Therefore, the holes injected into the semiconductor substrate 4 from the first region 5 cross the N region of the semiconductor substrate 4 and diffuse into the second region 6.
このホールの移動によって生じた電流がこの半導体装
置くすなわち複合形トランジスタ）におけるベース電流
となって第一電極Ｃと第二電極「との間にＣＥの方向の
増幅された電流が流れる。 この場合の増）
幅動作は通常のトランジスタと同じである。The current generated by the movement of the holes becomes the base current in this semiconductor device (ie, a composite transistor), and an amplified current flows between the first electrode C and the second electrode in the CE direction. (increase in width) The width operation is the same as a normal transistor.
一方、第一電極Ｃと第二電極Ｅとの間の電圧がある値（
Ｖｔｈ）ＬＪ、上になった時には、第一電極Ｃと第三電
極Ｂとの間の電圧が第一領域５と半導体基板４との間の
ＰＮ接合を逆バイアスするため、第一領域５から半導体
基板４へのホールの注入が停止され、その結果、半導体
基板のＮ領域と第二及び第三領域とで構成されるＮＰＮ
トランジスタがオフされて第−電極Ｃと第二電極トとの
間の電流がしゃ断される。 従って、この半導体装置は
自己保護機能を有していることになる。On the other hand, the voltage between the first electrode C and the second electrode E has a certain value (
Vth)LJ, when the voltage between the first electrode C and the third electrode B reverse biases the PN junction between the first region 5 and the semiconductor substrate 4, the voltage from the first region 5 increases. The injection of holes into the semiconductor substrate 4 is stopped, and as a result, an NPN composed of an N region and second and third regions of the semiconductor substrate is formed.
The transistor is turned off and the current between the negative electrode C and the second electrode T is cut off. Therefore, this semiconductor device has a self-protection function.
第３図は第２図の半導体装置をラテラル形に構成した実
施例を示している。 このようにラテラル配置とした構
成によると、第一領域５から注入されたホールがＮＰＮ
トランジスタ部分のベース電流となりやすいためＮＰＮ
トランジスタ部分の電流増幅率ｈｆｅが増大し、第２図
の半導体装置よりも大きな増幅率を有した半導体装置が
得られることになる。FIG. 3 shows an embodiment in which the semiconductor device of FIG. 2 is configured in a lateral type. According to this lateral arrangement, the holes injected from the first region 5 become NPN
NPN because it tends to become the base current of the transistor part.
The current amplification factor hfe of the transistor portion increases, and a semiconductor device having a larger amplification factor than the semiconductor device shown in FIG. 2 can be obtained.
また、前記のごとき構造の半導体装置において第−及び
第二電極間の電流がしゃ断された状態で・第−及び第二
電極Ｃ，Ｅ間の電圧を増大させると、第一電極Ｃと第三
電極Ｂとの間に印加されている逆バイアスが更に大きく
なり、ついには第一領域５と半導体基板のＮ領域との境
界のＰＮ接合がブレークダウンし始め、ボールとエレク
トロンが生じる。 その結果、第二領域６及び第三領域
７並びに半導体基板のＮ領域で構成されるＮＰＮＩ−ラ
ンジスタが再び導通状態になってリーク電流として現わ
れる。 それゆえ、このような現象の発生を防ぐために
はＰＮＰ１〜ランジスタ部分の耐圧をＮＰＮトランジス
タ部分のベースの耐■（以上にすることが必要であり、
それを実現するためには、たとえば第一領域５の拡散深
さｄ、を第三領域の拡散深さｄ２よりも同等かもしくは
大きくすることが好ましい。、
なお、第３図において第２図と同一符号で表示された部
分は第２図の半導体装置と同一の部分を示しているので
、この同一部分についての説明を省略する。Furthermore, in a semiconductor device having the above structure, when the voltage between the first and second electrodes C and E is increased while the current between the first and second electrodes is cut off, The reverse bias applied between electrode B further increases, and finally the PN junction at the boundary between first region 5 and the N region of the semiconductor substrate begins to break down, producing balls and electrons. As a result, the NPNI transistor composed of the second region 6, the third region 7, and the N region of the semiconductor substrate becomes conductive again and appears as a leakage current. Therefore, in order to prevent the occurrence of such a phenomenon, it is necessary to make the withstand voltage of the PNP1~transistor part higher than the withstand voltage of the base of the NPN transistor part.
In order to achieve this, for example, it is preferable that the diffusion depth d of the first region 5 is equal to or larger than the diffusion depth d2 of the third region. Note that in FIG. 3, the parts indicated by the same reference numerals as those in FIG. 2 indicate the same parts as in the semiconductor device of FIG. 2, and therefore explanations of these same parts will be omitted.
［発明の効果］ 第２図及び第３図のごとき構成の半導体装置を９− 製作し、これらについて静特性を調べた。[Effect of the invention] A semiconductor device having a configuration as shown in FIGS. 2 and 3 is 9- They were manufactured and their static characteristics were investigated.
第４図は前記半導体装置の静特性であり、同図において
横軸は第一電極Ｃと第二電極Ｅとの間の電圧Ｖｃ＋＝、
縦軸は第一電極Ｃと第二電極Ｅとの間に流れる負荷電流
ＩＣＥ、であり各静特性曲線はベース電流（す１．Ｉわ
ち第三電極Ｂに流入する電流）を変化させて得られたも
のである。 ＮＰＮＩ−ランジスタ部分をオフさせる電
圧Ｖｔｈはほぼ１２ボルトとなっている。 Ｖ ｔｈは
半導体基板内の拡散領域の設計寸法によって自由に変更
することができ、たとえば、第三電極Ｂの入カインビ、
−ダンスを変えることによりＶ ｔｈを大幅に変更する
ことができる。FIG. 4 shows the static characteristics of the semiconductor device, in which the horizontal axis is the voltage between the first electrode C and the second electrode E, Vc+=,
The vertical axis is the load current ICE flowing between the first electrode C and the second electrode E, and each static characteristic curve represents the change in the base current (i.e., the current flowing into the third electrode B). This is what was obtained. The voltage Vth that turns off the NPNI transistor portion is approximately 12 volts. V th can be freely changed depending on the design dimensions of the diffusion region in the semiconductor substrate, for example, the input voltage of the third electrode B,
-V th can be changed significantly by changing the dance.
第５図は、前記半導体装置におけるカットオフ電圧より
も＾電圧における特性を、第４図には示されていない範
囲についてもスケール単位を小さくして示したものであ
る。 第５図において、実線は第一領域５の拡散深さを
第二領域の拡散深さよりも小さくした場合の特性であり
、破線は第一領域５の拡散深さを第二領域の拡散深さと
同等か１０−
大きくした場合の特性である。 第５図に示されるよう
に、負荷電流■。Ｅのカットオフ後、ブレークダウン電
流によるリークが現われるが、第一領域５の拡散深さｄ
、を第二領域６の拡散深さｄ２よりも同等かもしくは大
きくすることによりリーク電流をを抑制することができ
る。FIG. 5 shows the characteristics of the semiconductor device at a voltage lower than the cutoff voltage, with the scale unit being made smaller in a range not shown in FIG. In FIG. 5, the solid line shows the characteristic when the diffusion depth of the first region 5 is made smaller than the diffusion depth of the second region, and the broken line shows the characteristic when the diffusion depth of the first region 5 is made smaller than the diffusion depth of the second region. Equal or 10- This is the characteristic when increased. As shown in Figure 5, the load current ■. After the cutoff of E, leakage due to breakdown current appears, but the diffusion depth d of the first region 5
By making , equal to or larger than the diffusion depth d2 of the second region 6, leakage current can be suppressed.
なお、本発明の半導体装置の破壊耐力を調べたところ、
同じ大きさの従来のトランジスタにくらべて大幅に向上
していることがわかった。In addition, when the breakdown strength of the semiconductor device of the present invention was investigated, it was found that
It was found that this is a significant improvement over conventional transistors of the same size.
以上に説明したように、この発明によれば、自己保護機
能を有した電力用半導体装置が得られ、従って、外付け
の保護回路が不要となり、電子回路の小形化及びコスト
低減が可能となる。 前記の実施例は本発明を限定する
ものではなく、本発明は図示以外の構造の半導体装置と
しても実現しうろことは当然である。As explained above, according to the present invention, a power semiconductor device having a self-protection function can be obtained, thus eliminating the need for an external protection circuit, making it possible to downsize and reduce costs of electronic circuits. . The embodiments described above do not limit the present invention, and it goes without saying that the present invention may be realized as a semiconductor device having a structure other than that shown in the drawings.
第１図は本発明の半導体装向の概念を等価回路で表わし
た本発明の概念図、第２図及び第３図は本発明の半導体
装置の実施例の断面図、第４図及び第５図は本発明の半
導体装置に関する静特性を表わした図である。
１・・・半導体装向、 ２・・・ＰＮＰＩ−ランジスタ
、３・・・ＮＰＮトランジスタ、 ４・・・半導体基板
、５・・・第一領域、 ６・・・第二領域、 ７・・・
第三領域、Ｃ・・・第一電極、 Ｆ・・・第二電極、
Ｂ・・・第三電極。FIG. 1 is a conceptual diagram of the present invention expressing the concept of the semiconductor device of the present invention as an equivalent circuit, FIGS. 2 and 3 are cross-sectional views of embodiments of the semiconductor device of the present invention, and FIGS. The figure is a diagram showing static characteristics regarding the semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor device, 2... PNPI-transistor, 3... NPN transistor, 4... Semiconductor substrate, 5... First region, 6... Second region, 7...
Third region, C...first electrode, F...second electrode,
B...Third electrode.
Claims (1)
互いに相隔てて形成された第二導電型の第−及び第二領
域と、該第二領域の中に形成された第一導電型の第三領
域と、該半導体基板の表面に設けられた第一電極と、該
第三領域りに設けられた第三電極と、該第−領域上に設
けられた第三電極とを有して成り、該第−及び第二電極
間の電圧が所定値以Ｆの時にのみ、該第−電極をコレク
タ電極、該第二電極をエミッタ電極、そして該第三電極
をベース電極とするトランジスタ増幅動作が行なわれ、
該第−及び第二電極間の電圧が所定値を越えた時に該第
−及び第二電極間の電流がしゃ断されるように構成され
ていることを特徴とする半導体装置。 ２ 第一領域と第二領域とが半導体基板の同じ側の表面
に形成され、該第−領域の拡散深さが該第二領域の拡散
深さよりも同等かもしくは大きい特許請求の範囲第１項
記載の半導体装置。[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, second and second regions of a second conductivity type formed spaced apart from each other on the surface of the semiconductor substrate, and a semiconductor substrate formed in the second region. a third region of the first conductivity type, a first electrode provided on the surface of the semiconductor substrate, a third electrode provided on the third region, and a third region provided on the third region. It has three electrodes, and only when the voltage between the first and second electrodes is a predetermined value or more, the first electrode becomes the collector electrode, the second electrode becomes the emitter electrode, and the third electrode becomes the emitter electrode. Transistor amplification operation is performed using the base electrode.
A semiconductor device characterized in that the current between the first and second electrodes is cut off when the voltage between the first and second electrodes exceeds a predetermined value. 2. The first region and the second region are formed on the same surface of the semiconductor substrate, and the diffusion depth of the first region is equal to or larger than the diffusion depth of the second region. The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11398284A JPS60258963A (en) | 1984-06-05 | 1984-06-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11398284A JPS60258963A (en) | 1984-06-05 | 1984-06-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60258963A true JPS60258963A (en) | 1985-12-20 |
Family
ID=14626089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11398284A Pending JPS60258963A (en) | 1984-06-05 | 1984-06-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60258963A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58108768A (en) * | 1981-11-20 | 1983-06-28 | Fujitsu Ltd | Semiconductor memory device |
-
1984
- 1984-06-05 JP JP11398284A patent/JPS60258963A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58108768A (en) * | 1981-11-20 | 1983-06-28 | Fujitsu Ltd | Semiconductor memory device |
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