JPS60257677A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To attain still picture image pickup with the shutter effect in the unit of one frame by controlling a clock pulse and applying frame image pickup and read in an optional shutter time in a solid-state image pickup element using a charge coupled element as an image sensor. CONSTITUTION:Photo sensors 10(10-11-10mn) are arranged in a matrix, horizontal shift registers 11(11-1-11-n) are arranged adjacently in the horizontal direction to the photo sensor 10 and transfer gates 12 (12-1-12-m) are arranged between the horizontal shift register 11 and the photo sensors 10. A vertical shift register 15 is connected to one end of the horizontal shift registers 11, overflow drains 22(22-11-22mn) are arranged to the photo sensors 10 adjacently in the vertical direction and overflow control gates 23(23-1-23-n) are arranged between the overflow drain 22 and the photo sensors 10. Then the clock pulse is controlled and frame image pickup/read are executed in an optional shutter time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a solid-state image sensor using a charge-coupled device (hereinafter abbreviated as COD) as an image sensor.

(Prior Art) Conventionally, image pickup tubes have been used as image sensors, but recently, solid-state RI elements have become smaller and more compact.

Because it has features such as long life and low power consumption, it has come to be widely used as an image sensor instead of an image pickup tube. In particular, interline CCD type solid-state imaging devices have excellent performance and are widely used.

Figure 1 shows the previously used interline type CC.
FIG. 2 is a diagram showing the configuration of a D-type solid-state image sensor. In the figure, reference numeral 1 denotes a photosensor consisting of a pn diode or a MOS diode, in which a photoelectric charge proportional to the amount of incident light is accumulated. The photoelectric charges accumulated in the photosensor 1 are transferred to the vertical shift registers 1 to 2 made up of CODs every one field period, and then transferred one horizontal line at a time to the horizontal shift register 3 made up of CODs, and then transferred to the output section 4. is continuously output as a horizontal line signal. Thus, one field is scanned and 41 is returned.

In addition, in such a solid-state image sensor, each) yr l
- The light accumulation time of the sensor 1 is determined based on the timing of transferring the photoelectric charge from FF1t to SEM+J1 to the vertical shift 1 register 2. In other words, the light accumulation time is one field period. However, with this light accumulation time, if the subject is moving quickly, image (3) will be 75;
This will cause a problem. Therefore, when the solid-state image element mentioned above is used as the darkest part of a still image in an electronic camera or the like, only 1q of good images can be produced.

Therefore, in order to solve the above-mentioned problem, the 7711-
Place overflow 1 to rain 5 adjacent to sensor 1 (
An appropriate period for this overflow drain 5 is considered. 1) It is thought that the light accumulation time is shortened by discharging the photocharges stored in the 741 to sen → node, thereby creating a Shack effect. There is.

By the way, COD normally performs -r interlacing using the following method. That is, among the photo sensors 1, the photosensor 1a read out in even fields and the photosensor 1b read out in odd fields are arranged adjacent to the N poles of the shift registers having mutually different phases. In other words, the fil-sensor 1a has a pulse φV1
The photosensor 1b is placed next to the N pole to which the pulse φV2 is applied. Since the pulses φv1 and φV2 transfer photocharges by setting one to the 11'' level and the other to the ``o'' level, it is not possible to transfer photocharges to the two electrodes at the same time. Therefore, the photocharges stored in the photosensor 1a are not transferred to the even fields, and the photocharges stored in the photosensor 1b are transferred to the odd fields.

Although this method does not pose a problem when photographing a moving image, it is not preferable when photographing a still image because the exposure timing is shifted between even and odd fields. especially,
When the above-mentioned shutter imaging is performed, there is a time difference of 1/60 second between the two fields, and when a moving subject is photographed as a still image, the image will be blurred.

In this way, the conventional interline CCD type solid-state image sensor has one field i-
The drawback was that only every image could be reproduced, and the number of scanning lines was 1.'2.

〔the purpose〕

An object of the present invention is to use a solid-state imaging system that is capable of capturing still images with a silletta effect on a frame-by-frame basis, that does not cause blur even for moving subjects, and that can obtain good images with high resolution. The purpose is to provide devices.

(Summary) In order to achieve the above object, the present invention is characterized by the following configuration. A horizontal shift register is arranged horizontally adjacent to the photosensor, and between this horizontal shift register and the photosensor, A transfer train 1~ is placed in the horizontal shift 1~ register, and a vertical shift resistor is connected to one end of the horizontal shift 1~ register, and an overflow train is placed adjacent to the photosensor in the vertical direction. The invention is characterized in that an overflow controller 1 to a roll gate are arranged between the overflow train and the photosensor.

[Embodiment] FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. In the figure, the symbols 10-11, 10-12°...1O-
1n, -to-10-ml, 10-rn2.・・1Q-
mn (collectively referred to as 10 below) is a photo sensor consisting of n'''p Al-Quio 1- arrayed in a 71 to 60x shape, and horizontally to this foot sensor 10. Horizontal shift consisting of adjacent COD shift 1 to register]-register 11-1.11-2...1l
-ITT (hereinafter collectively referred to as 11) is arranged. 12-1.1 To the horizontal shift 1 to the register 11 to the FO 1 to the DIO 1' 10 to the transfer goo]
2-2. . . 12-m (generally referred to as 12) are arranged, and transfer gate pulses φ are supplied from the terminal 13 to the transfer gates 1 to 12. In addition, the horizontal shift]-register 11 receives COD transfer pulses φH1, φH2, .-φt from the drive circuit 14.
−1 m (hereinafter collectively referred to as φH) is supplied. On the other hand, one end of the horizontal shift register 11 is connected to a vertical shift register 15, and one basic clock pulse φV is supplied from a terminal 16 to the vertical shift register 15.

Also, one end of the vertical shift me register 15 is a floating tiff collision area (hereinafter abbreviated as FD area).
17, and the FD region 7 is connected to the output transistor 18. Above output] -
The source of the transistor 18 is connected to the output terminal 19. Further, a beam set I/transistor 20 is connected to the FD area 7, and the reset 1-transistor 2
0, the reset pulse φR is supplied from the terminal 21.

On the other hand, in the same figure, the numbers 22-11, 21-21,...
22-ml, ~22-1n, 2l-2n.

...22-mn (hereinafter collectively referred to as 22) is an i-bar flow drain disposed vertically adjacent to the phytosensor 10, and this overflow drain 22 and the phytosensor 10 are connected to each other. -10 and 1.
J, Δ-bar flow control game 1 2.3-1.
23-2. ...23-n (hereinafter collectively referred to as 23 dozuru) is arranged, and this overflow controller [・
A clock pulse φ is applied to the roll goo 1-23 from the terminal 24.
D is being supplied. Further, the overflow drains 22 are connected in common to -C, and the terminal 25
A voltage V is applied from .

FIG. 3 shows signal waveform diagrams of various parts in FIG. 2.

The signal read operation will be described below with reference to FIGS. 2 and 3. Note that in FIG. 3, VD is a vertical synchronization pulse.

First, when light is incident on the photosensor 10, a photoelectric charge proportional to the amount of incident light is accumulated on the photosensor 10.

After light enters the photosensor 10 for a certain period of time, when the pulse φ becomes "1" to the transfer sensor 10, the photocharges stored in the A photo sensor 1o are transferred from the transfer sensor 1 to the transfer sensor 10.
12 to horizontal shift 1 to register 11.

After that, from the drive circuit 14, first the horizontal shift register 1
1-1, the CCD transfer pulse φH1 continues for a certain period (NT
If it is SC standard, it is supplied for approximately 63.5 μs). Then, the photocharges transferred to the horizontal shift 1 register 11-1 are transferred to the vertical shift 1 register 15, and are further carried to the FD area 17, where a potential change is brought about, and then the output An output voltage signal VO (Hl
) is output.

Here, the COD transfer pulse φ supplied to the horizontal shift 1 register 11-1, the vertical shift 1 register 15
φV supplied to
The reset pulses φR supplied to the gates of 0 and 0 are both driven at a common frequency fH. Therefore, the FD area 7 is reset every time the signal of one pixel is read out. That is, the photocharges transferred from the horizontal shift register 11-1 to the vertical shift register 15 are transferred to the photosensors 10-11.
The photocharges stored in 10-12, . . . 10, -, In are read out in order.

On the other hand, when all the photocharges transferred to the horizontal shift register 11-1 are transferred to the vertical shift register 15,
C from the drive circuit 14 to the horizontal shift register 11-3
The CD transfer pulse φH3 is supplied with +11, and the photocharge transferred to the horizontal shift register 11-3) A1 to sensor 10
-31.10-32°...10-3n are transferred to the vertical shift 1-register 15 in the order of the photocharges stored therein. Then, it is outputted from the output terminal 19 as an output video signal VO (H3) via the above-mentioned path. Below, horizontal shift register 11, -5.11-7. In this way, in the interlaced successive mode, the photocharges are transferred to the vertical shift register 15, and the photocharges transferred to the horizontal shift register 11-(m-1) are vertically shifted.
- When all data is transferred to register 15, odd field O
Reading of the NF signal is completed.

Next, the CCD transfer pulse φ)''2 is supplied from the drive circuit 14 to the horizontal shift register 11-2, and the photocharges in the horizontal shift 1-register 112 are transferred to the vertical shift 1-register 15. Then, when all the photocharges in the horizontal shift registers 1 to 11-2 are transferred to the vertical shift register 15, the horizontal shift registers 1 to 11-7!1.11-6.
The photocharge is transferred in the following order. Then, when all of the photocharges in the horizontal shift register 11-m are transferred to the vertical shift register 15, the signal succession of the even field ENF is completed. Thus said odd field EN'
As soon as the reading of the signals of and the reading of the signals of the even fields i to NF are completed, the successive signal output of one frame is completed.

Next, exposure time control will be explained with reference to the signal waveform diagram shown in FIG. 4. In addition, in Fig. 4, Fl, F2
．． F3 represents a frame.

First, in frame F1, the clock pulse φD supplied to the overflow control gate 23 is always "0". At this time, there is no outflow of photocharges from the photo 1 to the sensor 10 to the overflow 1 to the rain 22. Therefore, photocharges are accumulated in the D771 sensor 10 during one field period. Therefore, the exposure time is
The period indicated by A in the figure is loud.

Next, in frame F2, at time t1, the above φD
After time t1, φD becomes rOJ.

At this time, 77F1 to sensor 10 are in a conductive state with respect to overflow drain 22 until time t1. Therefore, no photocharge is accumulated. On the other hand, after time t1, from F A1 Hesen 1 F 10 to A-Half load rain 2
In contrast to 2, since there is no outflow of photocharges, photocharges are accumulated.

Therefore, the exposure time is the period indicated by B in the figure. In other words, the exposure time B of frame F2 is one frame "
The exposure time of 1 is shortened and the shutter effect becomes more effective.

In frame 3, the timing at which φD reaches rOJ is delayed from frame F2. Therefore, exposure time C is even shorter than exposure time B of frame F2.

In addition, in frame ``2'' or frame ``3'', the exposure time in odd-numbered frames 1- and the exposure time in even-numbered fields 1~ are the same. During photographing, there is no difference in exposure time between the two fields, and the shutter operation becomes possible.Therefore, when this embodiment is applied to electronic camera cameras, etc. It is possible to take good-quality, high-resolution images with no blurring, even for subjects with bright backgrounds.

As described above, according to this embodiment, by controlling the clock pulse φD, it is possible to perform frame imaging/reading in an arbitrary shift time (130 seconds or less). Furthermore, as is clear from FIG. 4, this embodiment can 1) support reading in the moving image mode; For example, by continuously performing a shutter operation with exposure time B for a plurality of frames, a moving image output with a jack effect is outputted as a video signal with intermediate frames. Therefore, double images will not occur even if the sprue gate shape of each frame is changed.

By the way, in this embodiment, the register 11 and the register 11 are vertically shifted to the horizontal shift 1, and the transfer j* degrees with the sister 15 are made the same. For example, according to the NTSC standard, a horizontal transfer rate of approximately 7.16 MHz is used for a horizontal 38484 pixel element, and a horizontal transfer rate of approximately 10.74 MHz is used for a horizontal 510 pixel element. is used.

Also, as is clear from FIG. 2 J5 and FIG. 3, in this embodiment, horizontal shift 1 - register 11, vertical shift 1 - register 1! :] are in series configuration, there is a time difference τ1 between the output start timing of φ1"1 output from the 1 drive circuit 14 and the output timing of the output video signal V○(+-11>). This time difference τ1 is generated by the number of vertical shift registers 150 stages/time. Therefore, the above time difference τ1 is φl−(1.

φH2,... becomes smaller as it progresses, and φHm and V
The time difference τm with O(1-1+η) is the smallest.

Therefore, the drive circuit 14 needs to delay the output start timing on the φ day little by little.

FIG. 5 is a diagram showing the configuration of the drive circuit 14. As shown in FIG. The drive circuit 14 includes line selection switches 30-1, 30-2, . ...
30-m (hereinafter collectively referred to as 30) and 31-
1.31-2. ...31-m (hereinafter collectively referred to as 31
), interlace selection switch 32-1.32
-, -2. . . 32-m (hereinafter collectively referred to as 32) 1 is composed of a frequency divider 33, digital shift 1 to register 34, etc.

Now, the number of horizontal pixels is 384, and the transfer clock frequency is 7.
It is assumed to be 16fvlHz. At this time, the frequency is 15.75t
< Hz horizontal synchronization pulse (q) is possible by dividing the clock frequency 7.16tvlHz by 455 using the frequency divider 33. In this case, the frequency division ratio of the frequency divider 33 is set to 455 =456.Then, the output CK of the frequency divider 33 is 7°16MH2,'456=15.
It becomes 70KHz.

The difference between this output C'K pulse and the horizontal synchronizing pulse (bright pulse width) is ΔT-(456/(7,16x10111))
-(455・'(7,16X10"))=[L
'(7,16xiO'))=140[ns. This corresponds to the same amount of delay for one stage of the vertical shift register 15. Therefore, the CK pulse drives the digital shift register 34, and as a result, the shift pulse φ31. By selecting the basic clock pulse φV with φS2... (hereinafter collectively referred to as φS), C
CD transfer pulse φH is obtained. In other words, the shift pulse φS is controlled by the field selection switch 32, and in odd fields, the CCD transfer pulses φH1, φH3, . . .
H(m-1), and in even fields, CCD transfer pulses φH2, φH4, . . . φHm are output. Note that φF is a pulse that is "1" during the odd field period and rOJ during the even field period.

Now, φS1. If both φF are "1", select switch 3
When 0 to 1 are ON and 31-1 is OFF, φV is output to φH1. Next, φS2 becomes rlJ and φF becomes “
1", the selection switch 30-1 is OFF, 3
1-1 becomes ON, φ(]1 becomes "0", and
The selection switch 30-2 is turned on, the selection switch 31-2 is turned off, and φV is output to φH3. Similarly, φH5,
φ1-17.

・・・φH(m-1), φH2, φl-14, ・・
- φV is read out in the order of φHm. As a result, the CCD transfer pulse φH shown in FIG. 3 is obtained.

Note that even when the number of horizontal pixels is other than 384, the division ratio of the frequency divider 33 is p+1 (N) is the ratio of the frequency of the basic clock pulse φV and the frequency of the horizontal synchronizing pulse).
The video signal output is synchronized to the horizontal sync pulse.

(Effect between lights) As detailed above, according to the present invention, photosensors are arranged in a matrix, horizontal shift registers are arranged horizontally adjacent to the photosensors, and the horizontal shift registers and the horizontal shift registers are arranged horizontally adjacent to the photosensors. A transfer gate is arranged between the photosensor, a vertical shift register is connected to one end of the horizontal shift register, and an overfloat l-twin is arranged vertically adjacent to the first sensor. , this over 7 days-train and said F711-sen υ
Since the overflow control game 1~ is placed between the camera and the camera, it is possible to take still images with a shutter effect in one frame, without blur even for moving subjects, and with high resolution. It is possible to provide a solid-state image sensing device that can obtain a wide range of images.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of a conventionally used interline type CCD type solid-state image sensor, and Figs. 2 to 5 are diagrams showing an embodiment of the present invention, and Fig. 2 shows the configuration. 3 is a signal waveform diagram shown in FIG. 2, FIG. 4 is a signal waveform diagram for explaining exposure time control, and FIG. 5 is a diagram showing the configuration of a drive circuit. 10 (1,0-11,10-12,・1O-1n. ~10-ml, 10-rn2.・10-mn)-
・・Photo sensor, 11 (1'l-1, 11-2,・
...11-m)...Horizontal shift register, 12 (12
'-1゜12-2,...'12-m)...Transfer gate, 14...Drive circuit, 15...Vertical shift 1 register, 17...Float ink eye caution area (F
D area, 18...output transistor, 20...reset transistor-ml. -22- 1 11.22-2rl, -21-
ITn)...Overflow 1-Rain, 23 (23
-123-2. ...2 3-n) ... Overf day - Control Gut, 30.31 (30-1.3
0-2...30-m and 31-1.31-2.・
・31-m)...Line selection switch, 32 (32
-1.32-2,...32-m>...Interlace selection switch, 33...Frequency divider, 34...Digital shift 1 to register. Applicant Representative Patent Attorney Atsushi Tsuboi Figure 1

Claims (1)

[Claims] 71 ~ photosensors arranged in a matrix, horizontal shift 1 ~ register adjacent to this photosensor and arranged in the horizontal direction, and transfer placed between this horizontal shift 1 ~ register and the photosensor a gate, a vertical shift register connected to one end of the horizontal shift register, an overflow drain arranged vertically adjacent to the photosensor, and an overflow drain arranged between the overflow train and the photosensor. A solid-state imaging device comprising: an overflow controller 1; a roll controller 1;